JP2789584B2 - High efficiency coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention compresses the data amount of a television signal,
The present invention relates to a high-efficiency coding apparatus applied to record a compressed digital signal by a VTR. [Prior Art] The present applicant seeks a dynamic range defined by a maximum value and a minimum value of a plurality of pixels included in a two-dimensional block as described in Japanese Patent Application No. 59-266407. Has proposed a high-efficiency coding apparatus that performs coding adapted to this dynamic range. In addition, Japanese Patent Application No. 60-
As described in the specification of Japanese Patent No. 232789, there has been proposed a high-efficiency encoding apparatus that performs encoding adaptive to a dynamic range with respect to a three-dimensional block formed from pixels in an area included in each of a plurality of frames. Furthermore, Japanese Patent Application No. 60-
As described in the specification of Japanese Patent No. 268817, there has been proposed a variable-length encoding method in which the number of bits changes according to a dynamic range so that the maximum distortion generated when performing quantization is constant. High-efficiency code (AD
RC) is suitable for application to a digital VTR because it can significantly reduce the amount of data to be transmitted. Especially,
The variable length ADRC can increase the compression ratio. However, the variable-length ADRC uses a buffering process when using a fixed-rate transmission path such as a digital VTR that records a predetermined amount of data as one track because the amount of transmission data varies depending on the content of the image. is required.
As described in Japanese Patent Application No. 61-257586, for example, the applicant of the present application obtains a power distribution of a dynamic lens, converts this power distribution into an integral type distribution, and sets a coding threshold value. A buffering device has been proposed which obtains the amount of generated information by applying it to a frequency distribution of an integrating type and controls the generated information amount so as not to exceed the transmission rate. [Problems to be Solved by the Invention] In order to perform the above-described buffering processing, a variable length
It takes time to calculate the amount of information generated when ADRC encoding is performed. Therefore, it is necessary to delay the data encoded with the variable length ADRC during this time. When the delay time increases, there is a problem that the capacity of the delay memory increases. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a high-efficiency encoding device capable of reducing the capacity of a delay memory for buffering processing. [Means for Solving the Problems] The present invention divides a digital television signal into a plurality of blocks formed over one to a plurality of continuous frames, and a maximum value, a minimum value, and a maximum value of each block. And a dynamic range, which is a difference between the minimum value and the dynamic range, and performs coding adapted to the dynamic range. A digital signal having a data absence period other than valid data in a digital television signal is read out in order, and the digital signal is supplied to an encoding device corresponding to a dynamic range. Is used to calculate the amount of information generated by encoding, There are a high-efficiency encoding apparatus characterized by controlling the amount of information generated. [Operation] In the present invention, only valid data excluding the blanking period is written into the memory of the blocking circuit that converts the data in the order of the scanning lines of the television signal into the order of the blocks. By controlling the write address or the read address of the memory, the conversion to the block order is performed. The digital signal read from this blocking circuit is a series of valid data from which the blacking period has been removed. Therefore, in a unit for forming a block, for example, a two-frame period, a data absence period in which no data is present occurs. The amount of generated information can be calculated and the threshold value can be controlled using this data absence period. For buffering, the data delay time is, for example, two frames, and the capacity of the delay memory is reduced. Can be small. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of the recording circuit of this embodiment. In FIG. 1, red (R), green (G) and blue (B) of three primary color signals are supplied to input terminals denoted by 1, 2, and 3, respectively. ) Is supplied. The A / D converter shown at 4 converts the three primary color signals into digital signals. The luminance signal (Y) and the color difference signal (U,
V) is formed. The luminance signal and the color difference signal are represented by (Y:
U: V) has a sampling frequency of (4: 4: 4). Since the digital component signal of (4: 4: 4) has a large amount of information, it is converted by the rate conversion circuit 6 into a time-division multiplexed signal 7 at a sampling rate of (3: 1: 0). That is, the sampling frequency of the luminance signal is (3/4), the sampling frequency of the chrominance signal is (1/4), and the U and V of the chrominance signal are line-sequential signals. The output signal of the rate conversion circuit 6 is
To convert the signals in the order of television scanning into signals in the order of blocks. In this embodiment, as shown in FIG. 3, two areas A11 and A12 occupying the same position (4 lines × 4 pixels) on two consecutive frames constitute one block.
The block includes 32 pixels. In addition, in the blocking circuit 8, the blanking period in the input signal is removed, the valid data is made continuous, and a data absence period is formed in the data sequence. 858 samples are included in one line, the valid data of which is 720 samples, the number of lines in one frame is 525 lines,
Since the number of valid lines is 488, the number of data and the number of valid data in the two-frame period are as follows. Number of valid data: 720 × 488 × 2 = 702,720 Number of data in two frame periods: 858 × 525 × 2 = 900,900 Blocking circuit 8 is composed of four frame memories, and only valid data of two frame periods is stored in two frame memories. At the same time, the valid data converted into the block order is read from the other two-frame memories.
By setting the read addresses of the two-frame memory to the order of the blocks, the order of the scanning lines can be converted to the order of the blocks. Accordingly, the output signal 9 of the blocking circuit 8 includes a data absence period of 231H (H: horizontal cycle) as in the following equation. (900,900-702,720) {858} 231H The output signal 9 of the blocking circuit 8 is supplied to the ADRC encoder 10. In the ADRC encoder 10, the maximum value MAX, the minimum value MIN, and the dynamic range that is the difference between the two
DR is detected, and variable-length coding is performed in accordance with the dynamic range DR. For example, four threshold values TH1, TH2, TH
3, TH4 (TH4 <TH3 <TH2 <TH1) is set. When the dynamic range DR of the block is (0 ≦ DR <TH4), the number of allocated bits is set to 0, and only the dynamic range DR and the minimum value MIN of the block are transmitted. (TH4 ≦
When DR <TH3), the number of allocated bits is 1 bit. When (TH3 ≦ DR <TH2), the number of allocated bits is 2 bits. When (TH2 ≦ DR <TH1), the number of allocated bits is 3 bits. When (TH1 ≦ DR <255), the number of allocated bits is 4 bits. As described above, when encoding the variable length ADRC of 0 to 4 bits, the buffering process is performed so that the information amount in the two frame period does not exceed the predetermined value. The buffering calculates the frequency of occurrence of the dynamic range DR in the two-frame period, determines the optimal threshold values TH1 to TH4 from the distribution of the frequency of occurrence of the dynamic range DR, and further prepares the dynamic range DR to prepare for the next processing. Consists of a series of processes for clearing the memory in which the frequency is stored. Using the threshold value determined by this buffering, encoding of the variable length ADRC is performed. FIG. 4 is a timing chart showing a process of processing by the blocking circuit 8 and the ADRC encoder 10. FIG. 4A
Pulse FRD is synchronized with the data frame period
FIG. 4B shows the pulse DBFR synchronized with the two-frame period of the data. As shown in FIG. 4C, the rate conversion circuit 6 in which data F1, F2,...
Is supplied to the blocking circuit 8 from the
As shown in FIG. 4D, the output signal 9 of the blocking circuit 8
Consists of two frames of valid data F11, F12,... Converted into a block order, and has a data absence period of about 231H as described above. FIG. 4E shows a pulse signal DTEN which becomes "1" in correspondence with the period of valid data and becomes "0" in correspondence with the data lack period. The ADRC encoder 10 collects the frequency of the dynamic range DR while the pulse signal DTEN is “1” and
During the period in which DTEN is “0”, the process of creating an integrated frequency distribution table, determining the threshold value, and clearing the memory is performed. Next, variable-length ADRC encoding is performed according to the threshold value, and as shown in FIG. 4F, encoded outputs F111 and F12 corresponding to data F11 of two frames and encoded outputs F112 and so on corresponding to two frames. Is obtained from the ADRC encoder 10. In addition, motion adaptive frame drop is used, and a motion / still block is determined for each block.
One of A2 and A13 is ADRC encoded. After the two frame data F11 is supplied to the ADRC encoder 10, the ADRC
The delay time until the encoded output F111 is output from the encoder 10 can be set to two frames. The output signal of the ADRC encoder 10 includes a code signal (referred to as a bit plane) 11 corresponding to each pixel and additional data 12.
Consists of The additional data 12 includes a dynamic range DR for each block, a minimum value MIN, data of a bit length, respective threshold values of a luminance signal and a color difference signal, a block number, a two-frame identification signal DBFR, a motion detection signal, and the like. . Output signals 11 and 12 of the ADRC encoder 10 are supplied to a framing circuit 13 and converted into data having a frame configuration.
The output signal 14 of the framing circuit 13 is supplied to an error correction code parity generation circuit 15 and, for example, an error correction code having a product code configuration is encoded. An output signal 16 of the parity generation circuit 15 is supplied to a parallel-to-serial conversion circuit 17, and a recording signal 18 of serial data is obtained at an output terminal 19. FIG. 2 shows the configuration of the reproducing circuit. In FIG.
A reproduction signal reproduced by the rotary head is supplied to an input terminal indicated by 21 via a reproduction amplifier or the like. The playback signal is converted into a parallel signal by the
(Time axis correction device) 23. Output signal 2 of TBC23
4 is supplied to the error correction circuit 25, and the error is corrected by the error correction code. The error correction circuit 25 outputs a corrected data 26 and an error flag 27 indicating the presence or absence of an error.
Occurs. Output signals 26 and 27 of the error correction circuit 25 are supplied to a frame decomposition circuit 28. The frame decomposing circuit 28 separates the bit plane 29, the additional data 30, and the error flag 27, and the output signals 27, 29, and 30 of the frame decomposing circuit 28
It is supplied to the ADRC decoder 31. In the ADRC decoder 31, the bit plane 29 is decoded using the additional data 30,
8-bit data corresponding to each pixel is obtained. Output signals 27 and 32 of the ADRC decoder 31 are supplied to a block decomposition circuit 33. The block decomposition circuit 33 is constituted by a 4-frame memory, and converts data of each pixel in the order of blocks into a signal in the scanning order of a television signal. Block decomposition circuit 33
Thereafter, pixel data 34 which is an 8-bit code signal corresponding to each pixel, an error flag 35 indicating whether or not each pixel has an error, and a motion detection signal 36 are generated. Motion detection signal
Reference numeral 36 denotes a signal indicating whether the block is a still block or a motion block, which is separated from the additional data 30. In the case of a stationary block, two areas A13 forming one block
And A12, in which the transmission of one of the frames is omitted. Output signals 34, 35, 36 of the block decomposition circuit 33 are supplied to a smoothing circuit 37. The smoothing circuit 37 performs a smoothing process on the still blocks that have been dropped and compressed so as to prevent unnatural connection between the blocks and the image when the still blocks continue. The output of the smoothing circuit 37 includes the pixel data 38 and the error flag 35.
Occur, and these output signals are supplied to the error correction circuit 39. In the error correction circuit 39, the error data is interpolated by other correct data having a temporal and spatial correlation. The output signal 41 of the error correction circuit 39 is supplied to the rate conversion circuit 42. The rate conversion circuit converts the (3: 1: 0) time-division multiplexed signal into a (4: 4: 4) component signal. Output signals (luminance signal Y, color difference signals U, V) of the rate conversion circuit 42 are supplied to a digital matrix circuit 43, where they are converted into three primary color signals (R, G, B). D / A conversion record 44
Thus, the three primary color signals are converted into analog three primary color signals, and are taken out to output terminals 45, 46, and 47. [Effects of the Invention] According to the present invention, the blocking circuit converts signals in the order of scanning lines into signals in the order of blocks,
Remove horizontal blanking period and vertical blanking,
Since the effective data is converted into a continuous signal, a data absence period can be formed in the data sequence. In the data absence period, the threshold required for the buffering process can be controlled, the delay time in the ADRC encoder can be suppressed to, for example, two frames, and the capacity of the delay memory can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a recording circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a reproducing circuit according to one embodiment of the present invention;
FIG. 3 is a schematic diagram used for explaining blocks, and FIG. 4 is a timing chart used for explaining one embodiment of the present invention. Description of main reference numerals in the drawings 8: block circuit, 10: ADRC encoder, 13: framing circuit.

Claims (1)

(57) [Claims] The digital television signal is divided into a plurality of blocks formed over a plurality of continuous frames, and a maximum value and a minimum value of each block, and a dynamic range which is a difference between the maximum value and the minimum value is detected. A high-efficiency encoding apparatus that performs encoding adapted to the dynamic range, wherein only effective data of the digital television signal is written into a memory of a block circuit, and the digital television signal is written from the memory in the order of the blocks; A digital signal having a data absence period other than the valid data in the signal is read out, and the digital signal is supplied to an encoding device corresponding to the dynamic range. The encoding device uses the read valid data. Then, the amount of information generated by the encoding is calculated, In data lack period, the high efficiency encoding device and performs control of the amount of information generated.