JPH01109978A - Highly efficient encoder - Google Patents

Abstract

PURPOSE:To save the capacity of a delay memory by eliminating the horizontal/ vertical blanking period of a digital TV signal, writing only an effective data to a block circuit so as to form a data missing period thereby controlling a threshold value required for buffering processing. CONSTITUTION:A luminance signal Y and color difference signals U, V are formed from the 3 primary color signals R, G, B given to terminals 1-3 by a matrix circuit 5. Then the signal is converted into a time division multiplex signal 7 by a rate conversion circuit 6. Then the TV scanning sequential signal is converted in the order of blocks by the blocking circuit 8. The blanking period in the input signal is eliminated in the circuit 8 and a data missing period is formed in the data series. Then a threshold value suitable for the dynamic range by an ADRC encoder 10 is set. The threshold value is controlled to process buffering in the data missing period thereby saving number of delay memories.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency encoding device that is applied to compress the data amount of a television signal and record the compressed digital signal with a VTR.

[Summary of the invention]

In this invention, one screen of a digital television signal is divided into a plurality of blocks, the maximum value, the minimum value, and the dynamic range which is the difference between the maximum value and the minimum value of each block are detected, and encoding adapted to the dynamic range is performed. In a high-efficiency encoding device that writes only valid data of a digital television signal to the memory of a blocking circuit, it writes only valid data of a digital television signal to the memory of a blocking circuit, and encodes digital television signals in block order from the memory and that has a data missing period other than valid data in the digital television signal. By reading the signal and supplying the digital signal to an encoding device according to the dynamic range, processing can be performed with a small memory capacity.

[Conventional technology]

The applicant of this application has determined a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and A high-efficiency encoding device that performs adaptive encoding is proposed. Furthermore, as described in Japanese Patent Application No. 60-232789, a high-efficiency encoding device performs encoding adapted to a dynamic range with respect to a three-dimensional block formed from pixels in areas included in each of a plurality of frames. is proposed. Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. is proposed.

High-efficiency code (AD) adapted to the above-mentioned dynamic range
RC) is suitable for application to digital VTRs because it can significantly compress the amount of data to be transmitted. In particular, variable length ADRC can increase the compression rate. However, in variable length ADRC, the amount of data to be transmitted varies depending on the content of the image, so when using a fixed rate transmission path such as a digital VTR that records a predetermined amount of data as one track, buffering processing is required. For example, the applicant of the present application who requires
As described in the specification of No. 586, the frequency distribution of the dynamic range is obtained, this frequency distribution is converted to a cumulative type distribution, and a coding threshold is applied to the cumulative type frequency distribution to obtain occurrence information. We have proposed a buffering device that calculates the amount of information and controls the amount of generated information so that it does not exceed the transmission rate.

[Problem that the invention seeks to solve]

In order to perform the buffering process described above, the variable length A
Time is required to calculate the amount of information generated when DRC encoding is performed. Therefore, during this time, the variable length ADR
It is necessary to delay the C encoded data. When this delay time increases, there is a problem in that the capacity of the delay memory increases.

Therefore, an object of the present invention is to provide a highly efficient encoding device that can reduce the capacity of a delay memory for buffering processing.

[Means for solving problems]

In this invention, one screen of a digital television signal is divided into a plurality of blocks, the maximum value, the minimum value, and the dynamic range which is the difference between the maximum value and the minimum value of each block are detected, and encoding adapted to the dynamic range is performed. In a high-efficiency encoding device, only valid data of the digital television signal is written to the memory of the blocking circuit, and the data is written in block order from the memory, and there is a data missing period other than the valid data in the digital television signal. The digital signal is read out, and the digital signal is supplied to an encoding device according to the dynamic range. [Operation] According to the present invention, only valid data excluding the blanking period is written into the memory of a blocking circuit that converts data in the order of scanning lines of a television signal into the order of blocks. Conversion to the block order is performed by controlling the write address or read address of the memory. The digital signal read from this blocking circuit contains continuous valid data from which the blanking period has been removed. Therefore, a data missing period in which no data exists occurs in a unit forming a block, for example, in a two-frame period. This data missing period can be used to calculate the amount of generated information and control the threshold value. Due to buffering, the data is delayed for example by 2 frames, reducing the memory capacity for delay. Can be made small.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the recording circuit of this embodiment. In FIG. 1, three primary color signals red (R), green (G), and blue (B ) signals are supplied. A D/A converter 4 converts the three primary color signals into digital signals. A digital matrix circuit shown in 5 generates a luminance signal (Y) and a color difference signal (
U, V) are formed. The luminance signal and color difference signal (Y:U:V) have a sampling frequency of (4:4:4).

Since the (4:4:4) digital component signal has a large amount of information, the rate conversion circuit 6 converts the (3:1:
0) and is converted into a time division multiplexed signal 7. That is, the sampling frequency of the luminance signal is (3
/4), and the sampling frequency of the color difference signal is (1/4).
4), and the color difference signals U and V are line sequential signals.

The output signal of the rate conversion circuit 6 is supplied to a blocking circuit 8, and the Il-order signal of the television screen scan is converted into a block order signal.

In this example, as shown in FIG. 3, the same position is occupied in two consecutive frames of the screen (4 lines x 4 pixels).
The two areas All and A12 constitute one block,
One block includes 32 pixels. Furthermore, in the blocking circuit 8, the blanking period in the input signal is removed, and valid data is made to be continuous.
Data missing periods are formed in the data series. One line contains 858 samples, of which 7 are valid data.
There are 20 samples, and the number of lines in one frame is 525 lines, of which the number of effective lines is 488. Therefore, the number of data and the number of effective data in two frame periods are as follows.

Number of valid data near 20 x 488 x 2 depth 702.72
Number of data in 02 frame period: 858 x 525 Valid data converted into block order is read from the frame memory. By setting the read address of the 2-frame memory in the block order, the scanning line order can be converted into the block order. Therefore, the output signal 9 of the blocking circuit 8 includes a data missing period of 2311 ((H: horizontal period) as shown in the following equation.

(900,900-702,720) +858-23
An output signal 9 of the 1H blocking circuit 8 is supplied to an ADRC encoder 10. The ADRC encoder 10 detects the dynamic range DR, which is the difference between the maximum value MAX and the minimum value MIN1 for each block, and performs variable length encoding in accordance with the dynamic range DR. For example, four threshold values TH1, TH2, TH3, TH4 (TH
4<T) (3<TH2<THI) is set. The dynamic range DR of the block is (0≦DR<Tf(4
), the number of allocated bits is O, and only the maximum value MAX and minimum value MIN of the block are transmitted. (
When TH4≦DR<TH3), the number of allocated bits is 1 bit. When CTH3≦DR<TH2), the number of allocated bits is 2 bits. (T)I2≦
When DR<THI), the number of allocated bits is 3 bits. When (TH1≦DR<255), the number of allocated bits is 4 bits.

In this way, when encoding variable-length ADRC of θ to 4 bits, buffering processing is performed so that the amount of information in a two-frame period does not exceed a predetermined value. Buffering is performed by determining the frequency of occurrence of the dynamic range DR in a two-frame period, determining the optimal threshold values TRI to TH4 from the distribution of the frequency of occurrence of the dynamic range DR, and further buffering the dynamic range in order to prepare for the next processing. It consists of a series of processes to clear the memory in which the range DR frequencies are stored. Variable length ADRC encoding is performed using the threshold determined by this buffering.

FIG. 4 shows a blocking circuit 8 and an ADRC encoder 1.
2 is a timing chart showing the process of 0 processing. FIG. 4A shows a frame pulse FRD synchronized with a data frame period, and FIG. 4B shows a pulse DBFR synchronized with a two-frame period of data. As shown in FIG. 4C, data F1. F2. When the output signal 7 from the rate conversion circuit 6 in which . It consists of two frames of valid data Fil, F12, etc., and has a data missing period of approximately 231H as described above. FIG. 4E shows the pulse signal DTEN which becomes "L" corresponding to a valid data period and becomes "O" corresponding to a data missing period.

In the ADRC encoder lO, the pulse signal DTEN is “
The frequency of the dynamic range DR is collected during the period ``1'', and during the period when the pulse signal DTEN is 0, the 0-order process is performed to create an integrated frequency distribution table, determine the threshold value, and clear the memory. Then, variable-length ADRC encoding is performed using a threshold value, and as shown in FIG. 4F, encoded outputs Fi11 corresponding to two frames of data Fil. Output data consisting of is obtained from the ADHC encoder 10.The delay time from when the 2-frame data Fil is supplied to the ADRC encoder 10 until the encoded output F111 is output from the ADRC encoder 10 can be set to 2 frames. ..

The output signal of the ADRC encoder 10 consists of a code signal (referred to as a bit plane) 11 and additional data 12 corresponding to each pixel. Additional data 12 includes the dynamic range DR9 minimum value MIN for each block, pit length data, thresholds for each of the luminance signal and color difference signal, and the block number.

It includes a 2-frame identification signal DBFR and the like.

Output signals 11 and 12 of the ADRC encoder 10 are supplied to a framing circuit 13 and converted into data having a frame structure. The output signal 14 of the framing circuit 13 is supplied to an error correction code parity generation circuit 15, and is encoded into an error correction code having a product code configuration, for example. The output signal 16 of the parity generation circuit 15 is supplied to the parallel-to-serial conversion circuit 17, and a serial data recording signal 18 is obtained at the output terminal 19.

FIG. 2 shows the configuration of the reproducing circuit, and in FIG.
A reproduction signal reproduced by a rotary head is supplied to an input terminal indicated by 1 via a reproduction amplifier or the like. The reproduced signal is converted into a parallel signal by a serial-to-parallel conversion circuit 22
C (time axis correction device) 23. The output signal 24 of the TBC 23 is supplied to an error correction circuit 25, and errors are corrected using an error correction code. The error correction circuit 25 generates corrected data 26 and an error flag 27 indicating the presence or absence of an error.

Output signals 26 and 27 of the error correction circuit 25 are supplied to a frame decomposition circuit 28. The frame decomposition circuit 28 separates the bit plane 29, additional data 30, and error flag 27, and the output signals 27, 29, and 30 of the frame decomposition circuit 28 are supplied to the ADRC decoder 31. The ADRC decoder 31 decodes the bit plane 29 using the additional data 30 to obtain 8-bit data corresponding to each pixel. ADRC decoder 3
1 output signals 27 and 32 are supplied to a block decomposition circuit 33.

The block decomposition circuit 33 is constituted by a 4-frame memory, and converts the data of each pixel in the block order into a signal in the scanning order of the television signal.

From the block decomposition circuit 33, pixel data 34 which is an 8-bit code signal corresponding to each pixel, an error flag 35 indicating the presence or absence of an error in each pixel, and a motion detection signal 36 are output.
occurs. The motion detection signal 36 is a signal indicating whether the block is a still block or a moving block, and is separated from the additional data 30. In the case of a still block, frame drop compression is performed in which transmission of one of the two areas All and A12 making up the l block is omitted.

The output signals 34, 35° 36 of the block decomposition circuit 33 are supplied to a smoothing circuit 37. Smoothing circuit 3
In No. 7, interpolation is performed on a still block subjected to frame drop compression, and one area is used as data for two areas. At the same time, smoothing processing can be performed to prevent unnatural connections in images between blocks when still blocks are consecutive. Pixel data 38 and an error flag 35 are generated at the output of the smoothing circuit 37, and these output signals are supplied to an error correction circuit 39. In the error correction circuit 39, the error data is interpolated with other correct data that is temporally and spatially correlated.

The output signal 41 of the error correction circuit 39 is transmitted to the rate conversion circuit 4.
2. By the rate conversion circuit 42, (3:1
:0) time division multiplexed signal is converted into a (4:4:4) component signal. The output signals of the rate conversion circuit 42 (luminance signal Y2 color difference signals U, V) are supplied to the digital matrix circuit 43 and converted into three primary color signals (R, G, B). The three primary color signals are converted into analog three primary color signals by the D/A conversion record 44, and output terminals 45° and 46
．． It was taken out at 47.

〔Effect of the invention〕

According to this invention, the blocking circuit converts the scanning line order signal into a block order signal, removes the horizontal blanking period and vertical blanking, and converts the valid data into a continuous signal. Therefore, data missing periods can be formed in the data series. During this data missing period, the threshold required for buffering processing can be controlled, the delay time in the ADRC encoder can be suppressed to, for example, two frames, and the capacity of the delay memory can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a recording circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram of a reproducing circuit according to an embodiment of the present invention.
FIG. 3 is a route map used to explain the blocks, and FIG. 4 is a timing chart used to explain one embodiment of the present invention. Explanation of main symbols in the drawings 8: Niblocking circuit, 10: ADRC encoder, 13
: Framing circuit. Procedural amendment, February 8, 1988 Director General of the Patent Office Kunio Ogawa 2 Name of the invention High-efficiency encoding device 3 Relationship with the person making the amendment Case Patent applicant address Tokyo Parts and Parts Ward Kita 6-7-35 Name (21
8) Sony Corporation Representative Director Norio Ohga 4, Agent 170

Claims (1)

[Claims] Divide one screen of a digital television signal into multiple blocks, detect the maximum value and minimum value of each block, and the dynamic range that is the difference between the maximum value and the minimum value,
In the high-efficiency encoding device that performs encoding adapted to the dynamic range, only valid data of the digital television signal is written into a memory of a blocking circuit, and the data is read from the memory in the order of the blocks and the digital television signal. A high-efficiency encoding device characterized in that a digital signal having a data missing period other than the valid data is read out, and the digital signal is supplied to an encoding device according to the dynamic range.