JPH042542Y2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a video signal processing device, and particularly to a video signal processing device that can obtain high quality frame-by-frame images without noise.

Conventional technology and its problems In helical scanning VTR,
During variable speed playback, in which recorded video signals are played back by running (or stopping) a recorded magnetic tape at a tape running speed different from that during recording, the relative speed between the tape and the head is different from that during recording, so the head scanning trajectory changes. It is well known that the marks are drawn at a different slope from the recorded tracks. For this reason, adjacent tracks are recorded by rotary heads having gaps with different azimuth angles, respectively.
During variable speed playback of a magnetic tape with a track pattern in which there is no guard band or only a very small guard band is formed between the tracks, the playback rotary head rotates with a gap of the same azimuth angle as itself per one track scanning period. The track recorded by the head and the track recorded by the rotary head (reverse track) having a gap of different azimuth angle are scanned alternately, and therefore, during reverse track scanning, the track is reproduced due to the azimuth loss effect. The signal level becomes extremely low and the S/N ratio deteriorates. Similarly, during variable speed playback of a magnetic tape with a track pattern in which a guard band of a sufficient constant width is formed between adjacent tracks, the guard band is crossed more than once per track scanning period, so when the guard band is scanned, The reproduced signal level becomes extremely low and the S/N ratio deteriorates.

Here, if the variable speed playback described above is frame-by-frame playback in which still images are sequentially obtained from arbitrary different recording tracks on the tape, in addition to the deterioration of the S/N ratio of the playback signal, noise In order to drive the noise outside the effective screen, a precise servo circuit for tape feeding, etc. is required, and furthermore, it is difficult to completely drive the noise out of the screen, and there is a problem in that the noise may also appear within the screen.

Therefore, the present invention writes the reproduced composite video signal to the field memory when the level of the FM wave is higher than a certain value during frame-by-frame playback, and
It is an object of the present invention to provide a video signal processing device that solves the above problems by reading out when the level of FM waves is lower than a certain value.

Means for Solving the Problems The present invention includes an AD converter that converts a composite video signal that is reproduced from a recording medium in a signal form having at least FM waves and then demodulated into a digital video signal; switch means for selectively outputting one of the output digital video signals of the AD converter and the field memory, and a pulse having a constant logical value near the middle of each field of the output digital video signal of the AD converter. The generated circuit means, the output signal of the switch means and the above-mentioned signal reproduced from the recording medium.
A detection signal indicating a reproduction period in which the level of the FM wave is lower than a certain value and the pulse are respectively supplied, and when the detection signal and the pulse of a certain logic value arrive at the same time, the next time when they arrive at the same time The field memory is used for one field period from the input of the vertical synchronizing pulse in the output signal of the first switch means to perform a write operation, and the switch means is used to selectively output the output signal of the AD converter, and otherwise control means for causing the field memory to perform a read operation and using a switch means to selectively output a digital video signal read out from the field memory; and an output means for obtaining a reproduced composite video signal output from the output signal of the switch means. An embodiment thereof will be described below with reference to the drawings.

Embodiment FIG. 1 shows a block system diagram of an embodiment of the device of the present invention. In the figure, a reproduced composite color video signal is input to an input terminal 1. This reproduced composite color video signal is produced by frequency modulating (FM) the luminance signal, frequency converting the carrier color signal to a low frequency band, frequency division multiplexing these two signals, and transmitting one field to one track using a rotating head. The magnetic tape recorded on successive tracks is played back at various speeds, the FM luminance signal in the playback signal is FM demodulated, the low frequency conversion carrier color signal is frequency converted to the original band, and these two signals are combined. This is a reproduced composite color video signal that is obtained by multiplexing and substantially conforms to the standard format. In addition, in the variable speed playback, the magnetic tape is run at a slower speed than during recording so that the shortest pulse interval of the detection signal shown as b in FIG. 3, which will be described later, appears at an interval larger than one field. The playback speed is selected.

As described above, the above-mentioned reproduced composite color video signal, which has been reproduced from the magnetic tape in the form of a signal having at least FM waves and then demodulated, is supplied to the AD converter 2 via the input terminal 1, where the analog-
After being digitally converted into a digital video signal, it is supplied to a field memory 3 and a bus line controller 4, respectively. When reading out the field memory 3, the bus line controller 4 selectively outputs the read digital video signal,
On the other hand, when writing to the field memory 3, the digital video signal of the field currently being reproduced by the AD converter 2 is selectively output. The output digital video signal of the bus line controller 4 is supplied to a first timing control circuit 5 and a DA converter 6, respectively.

As will be described later, the timing control circuit 5 receives a detection signal from an input terminal 6 as shown in FIG. The selected clock signal and the signal from the row address counter in the address signal generation circuit 10 are supplied together with the digital video signal to control the write and read operations of the field memory 3 and the switching operation of the bus line controller 4. A reference signal for this is outputted from its output terminal 7a to the second timing control circuit 9.

Here, the above-mentioned detection signal is, for example, at a high level during a period when the amplitude of the FM luminance signal reproduced from the rotating head while scanning the magnetic tape becomes smaller than a certain value due to reverse track scanning, and when the amplitude exceeds this certain value. The binary signal is generated to be at a low level during the period. However, for convenience of explanation, in this specification, it is assumed that the detection signal is received when the level of the reproduced FM wave is at a level indicating that it has become smaller than a certain value.

Further, the timing control circuit 5 outputs the horizontal synchronization pulse from which the equalization pulse and the vertical synchronization pulse have been removed from the output terminal 7b and supplies it to the timing control circuit 9, while the pulse obtained by shaping the vertical synchronization pulse is output from the output terminal 7b. 7c and supplies it to the address signal generation circuit 10. The timing control circuit 9 generates a signal controlled by the color subcarrier frequency based on the signal from the terminal 7a and supplies it to the bus line controller 4 for switching control, and also controls the field switching based on this signal. Generates the CAS (column address strobe) signal, RAS (row address strobe) signal, WE (read/write control) signal, etc. necessary for reading and writing to the memory 3 and supplies it to the field memory 3, and also generates an address signal. A signal is also output to the generating circuit 10. The field memory 3 is, for example, a random access memory (RAM), which has a storage capacity capable of storing one field's worth of digital video signals, and its read output signal (digital video signal) is supplied to the bus line controller 4. , and also writes the digital video signal taken out from the AD converter 2.

The address signal generation circuit 10 is a circuit for generating an address signal for specifying a write address or a read address for the field memory 3, and specifies the scanning line position in the screen where the digital video signal to be written or read is to be displayed. It has a row address counter that generates and outputs an address signal for specifying a pixel, and a column address counter that generates and outputs an address signal that specifies where among a large number of pixel positions on one scanning line the pixel is to be positioned. The row address counter is connected to the terminal 7c.
(3rd pulse described later)
The column address counter generates a pulse managed by the color subcarrier from the 1H cycle pulse from the terminal 7b, and is cleared thereby. In this embodiment, as will be described later, the output address signal of the row address counter is supplied to the timing control circuit 5 as well as the field memory 3.

Timing control circuit 9 is timing control circuit 5
Based on the output signal of the AD converter 2, when the detection signal enters the input terminal 6 near the middle of each field of the output digital video signal (becomes high level), the next first bus For only one field period from the input of the vertical synchronizing pulse in the output digital video signal of the line controller 4, the field memory 3 is caused to perform a write operation, and the bus line controller 4 is
The output digital video signal of the AD converter 2 is selectively outputted, and during other periods, the field memory 3 is caused to perform a read operation, and the bus line controller 4 is used to read out the digital video signal read from the field memory 3. Switching control is performed to select the output.

The digital video signal taken out from the bus line controller 4 is supplied to the DA converter 11, where it is digital-to-analog converted and returned to the original composite color video signal in the form of an analog signal, and then output to the output terminal 12. Ru. In this way, a high-quality frame-by-frame image without deterioration of the S/N ratio can be obtained at the output terminal 12.

Each of the field memory 3 and bus line controller 4 is controlled by a timing control circuit 9.
and the output signal of the address signal generation circuit 10, but the reference signal is the timing control circuit 5.
Next, the configuration and operation of the timing control circuit 5, which is a main part of the present invention, will be explained in more detail.

FIG. 2 shows a circuit diagram of one embodiment of the timing control circuit 5. As shown in FIG. In the figure, the same components as in FIG. 1 are designated by the same reference numerals. In FIG. 2, the bus line controller 4 that has entered the input terminal 15
These digital video signals are supplied to a horizontal sync pulse extraction circuit 16 and a vertical sync pulse extraction circuit 17, respectively. The vertical synchronizing pulse extracted by the vertical synchronizing pulse extraction circuit 17, as shown by h in FIG. is converted into an extremely small pulse of one field period and then output to the output terminal 7c.
-KF.F) 23, the clear terminal of the row address counter 20 in the address signal generating circuit 10, and the clock terminal of the J-KF.F 27, respectively.

The row address counter 20 is supplied with a 1H cycle pulse as a clock signal through the input terminal 19 and counts it. This count value signal of the counter 20 is supplied to the field memory 3 as described above, and is also supplied to the gate circuit 21 in the timing control circuit 5, where it is arithmetic-processed and output to each of the output digital video signals of the AD converter 2. The signal remains at a high level for a certain period of time (for example, 40 to 50 hours, although this can be set arbitrarily) only near the center of the field.
It is converted into a pulse as shown at c in FIG. This pulse c is supplied to the NAND circuit 22, where it is NANDed with the detection signal from the input terminal 6 as shown by b in FIG. As shown in FIG.
It is assumed that the signal enters (becomes at a high level) during each period leading up to the field. Further, it is assumed that the detection signals entering the first, third, and eighth fields exist near the middle of the fields. The numbers in brackets above the waveform of pulse a in FIG. 3 indicate the field order of the output digital video signal of the AD converter 2, that is, the field order of the composite video signal currently being reproduced from the recording medium.
Further, the numerical value in the waveform of the vertical synchronizing pulse h indicates the order contents of the reproduction field of the output digital video signal of the bus line controller 4, which is controlled as described later.

The output signal waveform of the NAND circuit 22 to which the above detection signal b and pulse c are respectively supplied is shown in FIG.
As shown, the signal is at a low level during the period when the detection signal b and the pulse c are received at the same time, and is at a high level at other times. This signal d is J-KF.
It is applied to the clock terminal of F23, and it is activated, for example, at its falling edge. J-KF.F23 has its J terminal connected to the positive DC voltage Vcc input terminal,
Its K terminal is connected to its output terminal.
Therefore, after the J-KF.F23 is cleared by the pulse a, the signal d is applied to its clock terminal.
The output signal of the Q output terminal is maintained at a low level (clear state) unless d is input, and the output is inverted at the falling edge of the first signal d that is input in the clear state. However, even if the second and subsequent falling edges of signal d come in, the output signal of that Q output terminal remains at a high level until the next pulse a comes in and the clear state is set. Hold.

Therefore, the Q output signal of J-KF.F23 rises at times t ₁ , t ₄ , and t ₇ when the detection signal b and pulse c start to arrive at the same time, respectively, as shown by e in FIG.
The pulses (square waves) fall at times t ₂ , t ₅ , and t ₈ when the detection pulse a of the first vertical synchronization pulse arrives after each time t 1 , t _{4 ,} and t ₇ . Here, as described above, the shortest pulse interval of the detection signal b is longer than one field, and the detection signal b does not come in for at least one field period from time t ₂ , t ₅ , t ₈ . This pulse e is supplied to the data terminal of the D-type flip-flop 24 and one input terminal of the two-input exclusive OR circuit 25, respectively. The flip-flop 24 has its clock terminal supplied with a clock signal having a high frequency such as the color subcarrier frequency sc or a natural number multiple or 1/2 times that of the color subcarrier frequency sc from the input terminal 8, and samples the pulse e using this clock signal. The signal is sent from its Q output terminal to the other input terminal of the circuit 25 and the two-input NAND circuit 26.
output to one input terminal of the .

The output signal of the circuit 25 is supplied to the other input terminal of the NAND circuit 26. This results in
From the NAND circuit 26, as shown by f in FIG.
A narrow pulse that goes low level in synchronization with the falling edge portion of pulse e is extracted. The pulse width of this pulse f is determined by the period of the clock signal input to the input terminal 8. This pulse f is J-
It is applied to the clear terminal of KF.F27, and for example, when the voltage falls, it becomes the clear state. J-KF.F2
Similar to J-KF.F23, J-KF.7 has a configuration in which a positive voltage Vcc is supplied to the J terminal and its output signal is supplied to the K terminal, so it is cleared by pulse f. Thereafter, the output is inverted by the pulse a that enters the clock terminal, and this state is maintained from then on until the next pulse f arrives. Therefore, the Q output terminal of J-KF.F27 becomes low level at the falling edge of the pulse f at times t ₂ , t ₅ , and t ₈ as shown by g in FIG.
The low level is maintained until time _t3 , _t6 when the waveform shaping pulse a of the first vertical synchronization pulse following time _t2 , _t5 , _t8 comes in, and it becomes high level again at time _t3 , _t6 . Become.

That is, the pulse g is low for one field period from the time points _t2 , _t5 , and _t8 when the pulse a arrives after the times _t1 , _t4 , and _t7 when the detection signal b and the pulse c arrive at the same time, respectively. level, and remains at a high level during other periods. This pulse g is output to the timing control circuit 9 via the output terminal 7a. The high level period of this pulse g approximately corresponds to the read period of the field memory 3, and the low level period approximately corresponds to the write period of the field memory 3.

On the other hand, the horizontal synchronizing pulse extracted by the horizontal synchronizing pulse extracting circuit 16 is converted by a waveform shaping circuit 28 into a pulse whose phase is synchronized with, for example, its rising edge portion, and then supplied to a sampling circuit 29. Here, in addition to the horizontal synchronization pulse, an equalization pulse and a vertical synchronization pulse are also extracted at the output terminal of the horizontal synchronization pulse extraction circuit 16 during the vertical blanking period. Therefore, the extraction circuit 29 removes the equalization pulse and the vertical synchronization pulse, extracts only the pulse that is phase-synchronized with the horizontal synchronization pulse at 1H intervals, and uses it as a timing signal from the output terminal 7b to the timing control circuit 9.
Output to. Note that the extraction circuit 29 becomes unnecessary if the horizontal synchronization pulse extraction circuit 16 is provided with that function.

The timing signal taken out from the output terminal 7b is supplied to the timing control circuit 9 shown in FIG. 1 together with the pulse g taken out from the output terminal 7a. Based on the clock pulse whose repetition frequency is equal to the color subcarrier frequency s and the timing signal from the terminal 7b, the timing control circuit 9 causes the clock pulse to rise in phase synchronization with, for example, the rising edge of the clock pulse as shown in FIG. A signal j with a waveform is generated. Here, the timing signal from terminal 7b comes in every 1H (=227.5/s), but the color subcarrier frequency s is equal to the horizontal scanning frequency _H.
Since the frequency is 227.5 times higher, the phase is reversed every 1H, but if you generate a signal j that rises only in phase synchronization with the rise of the clock pulse with the repetition frequency s as described above, the phase of the color subcarrier and The relationship is always the same with the phase of the rising edge of signal j. Thus, the time interval from any rising edge of signal j to the next rising edge is 227/
s or 228/s.

The timing control circuit 9 generates the above signal j and supplies it to the clock input terminal of the D-type flip-flop inside the circuit 9, and also supplies the pulse g from the terminal 7a shown in FIG. 4 to the data input of the D-type flip-flop. The flip-flop outputs a signal k as shown in FIG. 4. This signal k is generated and output as a control signal for the field memory 3 and bus line controller 4 shown in FIG. During the low level period of the signal k, the field memory 3 is written and the bus line controller 4 is
Switch to the output selection output state of converter 2. On the other hand,
During the high level period of the signal k, the field memory 3 is read out, and the bus line controller 4 is switched to the field memory 3 output selection output state.

The signal k has substantially the same signal waveform as the pulse g as described above, and has the same signal waveform if the phase of the color subcarrier is not considered. Therefore, for convenience of explanation, assuming that the high level period and the low level period of the pulse g correspond to the periods corresponding to reading and writing of the field memory 3, the field memory 3 has the low level period of the pulse g shown in FIG. The write operation is performed during the high level period, and the read operation is performed during the high level period. Therefore,
As shown by _W2 in g in FIG. 3, the field memory 3 writes the digital video signal of the second field without deterioration of the S/N ratio during one field period from time _{t2 to t3} , and from time _t3 to t. In the third field period following ₅ , the detection signal b comes in, so the digital video signal of the second field is read out as shown by _R2 in g of the figure. Furthermore, during the next fourth field reproduction period, the field memory 3 writes a digital video signal with no deterioration in the S/N ratio of the fourth field being reproduced, as shown by _W4 in FIG.
Since the detection signal b enters each field during the reproduction period of the 5th to 8th fields from t ₆ to t ₈ , the digital video signal of the 4th field written in one field period from time t ₅ to _{t 6} is Figure 3 g
It is read out repeatedly four times in total as shown by R ₄ . In this way, a reproduced composite video signal of a frame-by-frame image with no S/N deterioration is output to the output terminal 12.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can also be applied to frame-by-frame playback of a playback device such as a video disc.

Effects As described above, according to the present invention, the detection signal that comes in from time to time is detected at approximately the middle position of the field,
It is determined whether or not a detection signal is received in that field, and if it is determined that a detection signal is received, a digital video signal for the next one field period is written, and if a detection signal is received, When it is determined that there is no detection signal, the field memory is read and operated, so when it is determined that the detection signal is present, the next field period is FM.
Since the wave level is always above a certain value and there is no deterioration in the S/N ratio, it is possible to write only digital video signals without deterioration in the S/N ratio.
During other field periods in which a reproduced composite video signal with a degraded ratio can be reproduced, the readout output signal of the field memory is taken out any number of times.
It is possible to automatically obtain frame-by-frame images without deterioration of the S/N ratio, and it does not require a very precise servo circuit to perform frame-by-frame playback, and since only one field memory is required, the structure is inexpensive. It has features such as being able to

[Brief explanation of drawings]

Fig. 1 is a block system diagram showing one embodiment of the device of the present invention, Fig. 2 is a circuit system diagram showing an embodiment of the main part of the block system shown in Fig. 1, and Fig. 3 is the circuit shown in Fig. 2. FIG. 4 is a signal waveform diagram for explaining the operation of the system. FIG. 4 is a signal waveform diagram for explaining the operation of other main parts of the device of the present invention. 1...Reproduction composite color video signal input terminal, 2...
...AD converter, 3...Field memory, 4...
Bus line controller, 5, 9...timing control circuit, 6...detection signal input terminal, 7a to 7c
...Output terminal, 8, 19...Clock signal input terminal, 10...Address signal generation circuit, 11...
DA converter, 12... Reproduction composite color video signal output terminal, 15... Digital video signal input terminal, 16... Horizontal synchronization pulse extraction circuit, 17...
Vertical synchronization pulse extraction circuit, 20... Row address counter, 21... Gate circuit, 23, 27...
J-K flip-flop (J-KF.F), 24...
D-type flip-flop.

Claims (1)

[Scope of utility model registration request] an AD converter that converts a composite video signal reproduced from a recording medium in a signal form having at least FM waves and then demodulated into a digital video signal; a field memory to which the digital video signal is supplied; a switch means for selectively outputting one of the two output digital video signals of the field memory; a circuit means for generating a pulse having a constant logical value near the middle of each field of the output digital video signal of the AD converter; The output signal of the means and the said reproduced from the recording medium
A detection signal indicating a reproduction period in which the level of the FM wave is lower than a certain value and the pulse are respectively supplied, and when the detection signal and the pulse of the certain logical value arrive at the same time, the time when they arrive at the same time. The field memory is caused to perform a write operation for only one field period from the time when the first vertical synchronizing pulse in the output signal of the switch means is input, and the switch means causes the output signal of the AD converter to be changed. a control means for selectively outputting a digital video signal read out from the field memory; and a control means for causing the field memory to perform a read operation and causing the switch means to selectively output the read output digital video signal of the field memory; A video signal processing device comprising an output means for obtaining a reproduced composite video signal output.