JPS62230289A - Video signal processor - Google Patents

Abstract

PURPOSE:To drastically reduce the capacity of a storage device necessary for storing a picture by sequentially switching R-/G-/B-color signals at every horizontal scanning line, and time-shifting the R-/G-/B-signals, then recording/ reproducing. CONSTITUTION:Among the R-/G-/B-signals from an RGB demodulator 1, R-signal is directly inputted to a multiplexer 17, G-signal is subjected to a delaycirucit 20 of a delay time tau and supplied to the multiplexer 17, and B-signal is subjected to a delay circuit 21 of a delay time 2tau and supplied to the multiplexer 17. The three signals are sequentially switched at every horizontal scanning line. The output signals are digitized by an A/D converter 2, and written in a RAM 30. The signals read from the RAM 30 are D/A conerted by a D/A converter 5, switched at every h orizontal scanning line by a demultiplexer 18, and further provided with time-differences inverse to those at the time of recording by delay circuits 22 and 23, then inputted to a display 8. As a result, in the display 8, the R-/G-/B-signals are sequentially reproduced in a mosaic state at every scanning line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to information compression technology when recording and reproducing video signals in a storage device.

[Conventional technology]

2. Description of the Related Art Conventionally, there is a signal processing device shown in FIG. 7 for recording and reproducing video signals in a storage device (particularly a semiconductor memory).

In the figure, the video signal is transmitted to an RGB demodulator 1 (R: red,
G nigerien, B nibble) and are added to the synchronous separation circuit 9. The output of RGB demodulator 1 is A, D converter 2.3.4
and the output of AD converter 2.3.4 is RA
It is input to M (random access memory) 10, 11, and 12.

Furthermore, the data output of the RAM 10111.12 is connected to a DA converter 5.6.7, and these outputs are input to the display device 8. On the other hand, the vertical synchronization signal VSYNC and the horizontal synchronization signal H8YNC which are the output of the synchronization separation circuit 9
is added to the vertical address counter 14, and the horizontal synchronizing signal H8YNC is added to the horizontal address counter 15 together with the output of the clock generator 16. The outputs of the respective counters are input to the address inputs of the RAMs 10, 11, and 12. Furthermore, the control circuit 13 is RAM
Connected to IO, 11, 12.

The input video A signal, which is a component shift signal, is color-demodulated by an RGB demodulator as an R signal, a G signal, and a B signal. The color demodulated signal is converted from an analog signal to a digital signal by an AD converter 2.3.4.

Generally, flash converters are used because high speed is required. Each AD-converted RGB signal is stored in RAM10.
．． 11.12 is added to the data input and becomes write 1-data. -10,000 RAM 10,11.12
The read data is sent to the DA converter 5.6.
7 and is returned to an analog signal. The output of the DA converters 5, 6, 7 is visualized on the display device 8.

On the other hand, the horizontal synchronization signal 105YN separated by the synchronization separation circuit 9
C and vertical synchronization signal VSYNC are vertical address counter 1
4 and added to the horizontal at 1 counter 15 and the RAM 10
Generates a pulse specifying the address of 111.12.

FIG. 8 shows a block diagram of a concrete example of the vertical and horizontal address counters 14 and 15. Vertical and horizontal address counter 1
4.15 consists of a binary counter, and the horizontal synchronizing signal "■YNC is input to the clock terminal of the vertical address counter 14 and the reset terminal of the horizontal address counter 15. Also, the clock output of the clock generator 16 is input to the horizontal address counter 15. 15. Therefore, the terminal output of the horizontal address counter 15 is inputted to the clock terminal of 1-1.
If it is 4 bits 0-H3, the input/output waveforms of each terminal will be as shown in FIG. Further, the vertical synchronizing signal VSYNC is input to the reset terminal of the vertical address counter 14, and if the terminal output is 4 bits VO to V3, the input/output waveforms of each terminal will be as shown in FIG. Therefore, the outputs of these vertical and horizontal address counters 14.15 are stored in RAM 10.11.
．． It is connected to 12 address terminals and instructs write and read addresses. In addition, RAM10.1
The control circuit 13 controls writing and reading to and from 1.12.

FIG. 11 shows the state of recording and reproducing video data in the RAMs 10, 11, and 12 and the relationship with the display.

FIG. 11(a) shows the state when recording to RAM10, 11.12, and corresponds to the first scanning line of the display screen, the RA in the case of sample timing to -t9.
The data of M10.11.12 is BO-89, respectively.
Recorded as GO-G9 and RO-R9. Also the second
Sample timing 110 to t19 corresponds to the scanning line.
In the case of , the data of RAMl0111.12 is 8
10 to 19, recorded as G10/G19, R10/~R19. Next, the state when this recorded data is reproduced is shown in FIG. 11 (1)). In this case, the operation is opposite to that during recording, and data BO-89, Go-G9 of RAM 10, 11.12, RO to R9 are read out, and these data are displayed on the display 8 (RO, GO, B).
0), (R1, Gl, B1), each picture element is displayed once. However, although this example shows a small number of data, in reality, if the number of picture elements is at least 200 dots in the vertical direction and 400 dots in the horizontal direction, so, ooo pixels will be appropriate.

[Problem that the invention seeks to solve]

Since the conventional video signal processing device is configured as described above, the memory capacity required to store video data is quite large.

For example, 200 dots vertically, 400 dots horizontally, 8083
Color, resolution 8 pixels [-200X400X3X
A capacity of 8=1.920.000 bits is required. Furthermore, since one AD converter must be provided for each of RGB, there is a drawback that the cost is extremely high.

[Purpose of the invention]

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method.
The B color signal is switched sequentially, and the RGB color signals are time-shifted and AD converted and recorded. When one signal is generated, the data read from the recording means and DA converted is sequentially read out for each horizontal scanning line. The object of the present invention is to provide a video signal processing device that can significantly reduce memory capacity by performing playback with a time shift in the direction opposite to the recording property when switching.

〔Example〕

An embodiment of the present invention will be explained below based on the drawings. 1st
In the figure, if the ``embo shift video signal'' is an RGB demodulator 1.
and is input to the synchronization separation circuit 9.

The output of the RG B demodulator 1 is first input to the multiplexer 17 as the R signal output, and the G signal output is inputted as it is after the delay time τ.
The signal is inputted to the shift shaker 17 via the delay device 20 having the following. Then, the B signal output is input to the multiplexer 17 via a delay device 21 having a delay time of 2τ. ? The output of the multiplexer 17 controlled by the signal from the radiplex signal generator 19 is input to the AD converter 2, and its output is further connected to the data input terminal of the RAM 30. A multiplex signal is input to the multiplexer 17 from a multiplex signal generator 19 . This multiplex signal generator, the vertical address counter 14, and the horizontal address counter 15 have a synchronous separation circuit 9.
The horizontal synchronizing signal 5YNC is inputted to each of the first two, and the vertical synchronizing signal VSYNC is inputted to the first two. Furthermore, it is applied to the horizontal horn dress counter 15 [1 Tsuku Bongyuuki 1]
A clock signal is supplied from 6. Vertical)) The outputs of the address counter 14 and the horizontal address counter 15 are RA.
Connected to the address input of M30. On the other hand, RAM3
The read data read from 0 is input to the DA converter 5, and its output is input to the demerge blur 18. Multiplexer 1 to demultiplexer 18
Similarly to 7, a multiplex signal from a multiplex signal generator 19 is input as a control signal. A delay device 22 having a delay time 2τ is connected to the R output of the demultiplexer 18, and a delay device 23 having a delay time τ is connected to the G output. inputted to the display device 8 as a signal output,
The output of the delay device 23 is input to the display device 8 as a G output. A control circuit 13 is provided to control reading and writing of data in the RAM 10.

Next, the operation of this invention will be explained. RGB demodulator 1
Of the RGB signals color-demodulated by
The G signal is input to the multiplexer 17 via the delay device 20 with a delay time τ, and the B signal is input to the multiplexer 17 via the delay device 21 with a delay time 2τ. Multiplex signal Sφ from multiplex signal generator 19
, Sl, S2'C-tit+, and the RGB signals are sequentially switched for each horizontal scanning line. FIG. 2 illustrates an actual circuit diagram of the multiplex signal generator 19. Here, the vertical synchronization signal VSYNC is the flip-flop circuit 24.2.
5.26 The horizontal synchronizing signal H8YNC is input to the terminals 1 to 1 through terminal R, and the horizontal synchronizing signal H8YNC is input to the input terminal CK. Further, the two input terminals of the NOR circuit 23 are connected to the output terminals Q of the flip-flop circuits 24 and 25, respectively, and
The output terminal of the OR circuit 23 is connected to the input circuit of the logic circuit 24. ? Lutibrex signal generator 1
The outputs of 9 are the multiplex signals SΦ, SL,
Output as S2. FIG. 3 shows an input/output signal waveform diagram of the multiplex signal generator 19. The multiplex signals Sφ, Sl, $2 of the multiplex signal generator 19 are synchronized with the horizontal synchronizing signal H8Y and are switched sequentially. ,
The control circuit is reset by the vertical synchronization signal VSYNC.

FIG. 4 shows an example of the multiplexer 17.

In this example, the i~lance tour gates 27, 28, and 29 are used as switch elements, and the multiplex numbers SΦ, B1, and B2 are applied to the control terminals, respectively. The RGB color signals multiplexed for each horizontal scanning line in this manner are digitally converted by the AD converter 2 and written into the RAM 30.

On the other hand, in the case of reproduction, data read from the RAM 30 is converted into an analog signal by the DA converter 5 and switched by the demultiplexer 18 for each horizontal scanning line. As the demultiplexer 18, the circuit illustrated in FIG. 4 can be used as is by replacing the input and output. The operations of the vertical address counter 14 and the horizontal address counter 15 are the same as in the prior art, and they generate addresses corresponding to the horizontal and vertical positions of the screen and provide them to the RAM 30.

FIG. 5 illustrates the relationship between the recording and reproducing states and the display in the video signal processing apparatus according to the present invention.

When recording the signal shown in FIG. 5(a), the multiplexer 17 in FIG.
Since the signals are switched, the RCj number is RO to R9 on the first scan line on the display screen, the G signal is G10 to G18 on the second scan line, and the B signal is on the third scan line. are added to the AD converter 2 as 820 to B27. In that case, since the delay device 2o is inserted in the G signal line and the delay device 21 is inserted in the B signal line, the G signal and the B signal arrive at the AD converter 2 with a delay of time τ and 2τ. This delay time τ is set to approximately 1/3 of the sample timing Bo to t3). As a result, the signal of R3 at time t3 and the signal of G12 at time 13 are sampled and recorded in the storage device "i<A M 30" as shown in FIG. 5(b). When reproducing signals, the RA
The read data read from the M30 is subjected to DΔ conversion by the DA converter 5, and distributed into RG B signals for each horizontal scanning line by the demultiplexer 18. The R signal is then input to the display 8 via the delay device 22 and the G signal via the delay device 23. Therefore, the data read at read timing t3 becomes R3 of the first scanning line on the screen of display 8 with a delay of 2τ.

Also, the data at read timing 113 is G of the second scanning line.
Becomes 12. From then on, the video signal is reproduced on the display screen in the same manner.

As described above, in the present invention, on the display screen, the first scanning line is RO, R3, R6, the second scanning line is G12.15, and the third scanning line is B21, B24, B27, which are reproduced in a mosaic pattern. Ru. This display screen provides a natural color image when viewed from a short distance, and the horizontal resolution in particular has the same effect as a shorter sampling period. This is because the R, G, and B signals have information representing brightness, and information in the horizontal direction can be represented by the first, second, and third scanning lines. Although the resolution of color information decreases, this does not pose a practical problem because the band of color information is relatively narrow. In this example, the number of picture elements is reduced, but in reality, the number of picture elements is large.

In the above embodiment, when writing data, as shown in FIG.
As shown in FIG. 6, the main parts of the circuit are configured in the following order: AD converters 2, 3, .
4, and delay devices 20 and 21, and multiplexer 17
Similar effects can be obtained by configuring in this order. In this case, the order may also be changed during reproduction as shown in FIG. 6. Further, in the above embodiment, a delay device is used as a means for creating a time difference between the RGB signals, but this may be done using other methods. For example, note 1! The same effect can be obtained by setting a time τ between RGB in writing and reading timing to the device. Further, the delay time τ of the delay device is set to 1/3 of the cycle of the write/read clock, but even if this is slightly different, the effects of the present invention will not be lost.

Further, in the present invention, an AD converter is used to convert the RGB signal into a digital signal, but if quantization requires only one bit, a simple comparator may be used.

Further, although RAM (Random Access Memory) is used as a storage element, other storage media may be used.

〔Effect of the invention〕

As described above, in the present invention, since the RGB color signals are sequentially switched for each horizontal scanning line and the RGB signals are time-shifted for recording and reproduction, the capacity of the storage device required for recording images can be significantly reduced. . Even if information is compressed in this way, the display screen must be viewed from a distance, or if the display screen is small (LCD Pocket T
(for V) the image is reproduced normally. In particular, it is a compact power set for audio by AD converting the J revision signal.
- In applications such as recording on media, significant information compression is essential, and the present invention is an effective means.

Furthermore, since the sampling frequency can be set low, interference such as electromagnetic induction imparted to the harmonic (high frequency) signal of the signal processing system or the TV signal is reduced.

Also, if configured as shown in Figure 1, A
It is sufficient to use only one each of l) and DA converter, and there is a great cost advantage.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the video signal processing device of the present invention, FIG. 2 is an example of a multiplex signal generator that is a part of this block diagram, and FIG. 3 is the output waveform thereof. In addition, FIG. 4 shows a specific example of the block diagram, which is a part of the block diagram, and FIG. 5 shows the relationship between the recording/playback state and the display in the video signal processing device of the present invention. FIG. 6 shows an embodiment of the present invention. FIG. 7 shows a conventional video signal processing device, FIG. 8 shows a configuration diagram of the address counter used in FIG. 7, and FIGS. 9 and 10 show the output waveform of the 77 address counter shown in FIG. FIG. 11 is a diagram showing the relationship between the recording/reproducing state of video data and the display in a conventional example. 1・・・・・・・・・・・・・・・・・・・・・・・・
...... RGB demodulator 2.3.4, 20...
......AD converter 5.6.7.21...
・・・・・・・・・DA converter 10.11.12.3
0...RAM 17...................................................................................
・・・・・・Multiplexer 18・・・・・・・・・
・・・・・・・・・・・・・・・・・・ Demultiplexer Special Applicant Bi-Nia Co., Ltd. = 16-

Claims (1)

[Claims] Video signal processing comprising means for AD converting the color signal of the video signal, storage means for recording the AD converted color signal, and means for reproducing the color signal by means of DA conversion for data read from the storage means. The apparatus includes a delay means for sequentially switching each RGB color signal for each at least one horizontal scanning line during color signal recording, and for shifting each of the RGB color signals by a predetermined time, before or after the AD conversion means. When the color signal is reproduced, the DA-converted data read from the storage means is sequentially switched for each at least one horizontal scanning line, and the predetermined RGB color signal is converted into the RGB color signal in the opposite direction to that during recording. A video signal processing device characterized in that it is provided with a time-shifting delay means for reproduction.