JPS61114682A - Image processing circuit - Google Patents

Abstract

PURPOSE:To realize a multi-image regenerating system at low cost in an optional composition of camera work by establishing the 1st and 3rd frame memory system to memorize the 1st and 2nd digital image information in the scanning period (2n-1) and the 2nd and 4th frame memory system to memorize the 1st and 2nd digital image information in the 2n scanning period. CONSTITUTION:Each image A, B line scanning signal is varied into a digital signal individually by A/D convertor 12. The image information A2 an odd- number signal is memorized in the line memory 5 in each pixel during the period of opening of the 1st scanning up to the end. In synchronization with the image information A2 the image information B2 of the 1st scanning 1' is memorized by line memory 7, likewise. Next, in the 2nd scanning period, the 2nd scanning line signal 2' of the image A and the scanning signal of the image B2' turn into the image information A2, B2 to be memorized every picture element as image information A4, B4 in the line memory 6, 8 through switch circuit 3, 4. On one hand, the digital image information A2 & B2 are read in succession in the 2nd scanning period to be memorized in each line memory 6, 8 and the image information A3, B3s are outputted through the adding machine 9, 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image processing circuit that simultaneously reproduces images obtained by a plurality of television cameras on a single cathode ray tube.

Conventional technology Recently, reconstructed images using television cameras are used as crime prevention and disaster prevention systems.
It has been adopted in many systems such as measurement control systems and traffic monitoring. There is a desire for a reproduction method that can simultaneously monitor images using a multi-reproduction method in which images obtained by multiple cameras can be reproduced simultaneously on a single cathode ray tube.

For example, a conventional camera based on the Nippon Shibo system has a horizontal scanning period of 63.5 μs and approximately 525 lines/2 scans. In order to perform multiple reproduction of two screens on one reproduction display device, it is sufficient to double the beam deflection speed of the camera's image pickup tube.

Moreover, as a method without improving the camera, each image may be once stored in a frame memory, and then read out and reproduced in accordance with the two-screen configuration.

Problems to be Solved by the Invention However, in the former case described above, in order to double the speed of the camera's image pickup tube beam deflection, it is necessary to significantly change the camera's image pickup tube beam deflection circuit. Furthermore, since the camera is a special camera, not only is there a loss of freedom in system configuration, but there are also disadvantages in terms of camera compatibility.

On the other hand, the latter case is disadvantageous because it increases the cost of frame memory and the like.

In view of the above-mentioned drawbacks, the present invention has been developed to convert a conventional 3:4 view angle image into a 3:8 view angle display device without improving a standard camera, and without using a frame memory or the like, and with an arbitrary camera configuration. The present invention provides an image processing circuit that can realize a multi-image reproduction system at low cost.

Means for Solving the Problems The present invention provides a first frame memory for storing first digital image information in (2n-1) scanning periods; a first frame memory storing said first digital image information in 2n scanning periods; a third frame memory that stores the second digital image information during the (2n-1,) scanning period; and a fourth frame memory that stores the second digital image information during the 2n scanning period. By providing this, the above object is achieved.

action
According to the above configuration, the present invention reads out the image information stored in the first frame memory during the 2n scanning period, then reads out the image information stored in the third frame memory, and reproduces the image. (2n-1) of the device
scanning line information, while (2n-1-1) scanning period lζ After reading out the image information stored in the second frame memory, reading out the image information stored in the fourth frame memory, Since the image reproducing apparatus uses 2n scanning line information, the image reproducing apparatus can obtain scanning line information alternately, so that multi-image reproduction is possible.

Embodiment Hereinafter, an embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 shows a block configuration of an image processing circuit in an embodiment of the present invention.

In FIG. 1, 1 is a first television camera (not shown)
An analog/digital converter (hereinafter abbreviated as M/D converter 1) converts the analog image information 1 sent from the 8-bit digital image information A2, 2 is a second
This is an analog/digital converter (hereinafter abbreviated as A/D converter 2) that converts analog image information B1 sent from a television camera (not shown) into 8-bit digital image information B2. Reference numeral 3 denotes a switch circuit that inputs the digital information image information person 2 sent from the MU/D converter 1, and the internal OR circuit is alternately turned on and off by the control signals T□ and T2 of the timing control circuit 12. . 4 is a switch circuit which inputs the digital image B2 sent from the MU/D converter 2, and an internal OR circuit is alternately turned on and off by the control signals T3 r T4 of the timing control circuit 12. 6 and 6 are digital information image information signals 3.6 and 6 sent from the A/D converter 1 via the switch circuit 3;
A, and control signals T5.A and T5.A, which are respectively sent by the timing control circuit 12. It is controlled by T6 and outputs at twice the writing speed. 7 and 8
is the digital image information B3. that is sent from the human/D converter 2 via the switch circuit 4. B4 is a line memory that stores control signals T7 . T, and outputs at twice the writing speed. 9 is an adder that outputs digital image information B3 sent out by the line memory 5 after the digital image information sent out by the line memory 5; and 10 is a digital image information sent out by the line memory 6. an adder that outputs digital image information B4 sent out by the line memory 8 after
11 is an adder that outputs the output of adder 10 next to the output of adder 9;

The operation of the above configuration will be explained below with reference to FIG. 2.

FIG. 2 is an explanatory diagram when two 3:4 view angle images are displayed simultaneously in the horizontal direction on a 3:8 view angle image reproducing display device using the signal processing according to the present embodiment.

In the same figure, it is assumed that the images B and B which are converted into person/D by the M/D converter 1.2 are all composed of scanning line image signals generated by a Japanese standard television camera.

The image shown in FIG. 2L starts from the first scanning line 1' and scans sequentially in even or odd fields, starting from the first scanning line 1', 2', 3', .

Similarly, image B in the figure (bl) starts from the first scanning line 1'' and is sequentially scanned as 71, 3LL, . . . .

In this case, images A and B are sequentially scanned using the same synchronizing signal pulse, and both screens are assumed to maintain synchronization.

First, line scanning signals of each image A and B from a television camera are individually converted into digital signals by A/D converters 1 and 2.

The first scanning line 1' of the image frame is converted into an 8-bit digital image information frame 2 by the MU/D converter 1, and then passed through the switch circuit 3 to the odd-numbered scan line 8, which is the image information input line 1;
is the period from the beginning to the end of the first scan and the line memory 6
is stored for each pixel.

In synchronization with the digital image information A3, the digital image information of the first scanning line 1' is also stored in the line memory 7 via the switch circuit 4 until the first scanning ends.

Next, a second scanning period begins. At this time, the second scanning line signal 2' of the image person and the 2'' scanning line signal of the image B are sent to the A/D converters 1 and 2.
According to 8-bit digital image 1 image information ~, B2'! The digital image information B2 is transferred to the line memory 6 as the digital image information 4 via the switch circuit 3, and the digital image information B2 is transferred to the line memory 8V via the switch circuit 4.
c It is stored for each pixel as digital image information B4.

On the other hand, digital image information M2 and B2 are stored in each line memory 6.
8 and are sequentially read out during the second scanning period. That is, the line-scanning digital image information 3 corresponding to the image B is read out from the first line memory 5 in the first half of the second scanning period, and the line-scanning digital image information 3 from the line memory 7 for the image B is read out in the second half. is read out.

Above two digital image information systems 3. B3 is adder 9.1
1 and then output. This output signal is subjected to one time/mu conversion and then becomes the scanning line image signal signal of the 3:8 image reproduction display device shown in FIG. 2(C). This is the first scanning line 1#
corresponds to

Note that scanning line 1 scans at a cycle of 15.75 KHz, and the read clock frequency from line memories 5 to 8 is twice the clock frequency during storage, but data is read out from line memories 5 to 8 intermittently. The images may be reproduced so that two screens are lined up in one scanning period.

Next, the third running signal of the image person and B from the television camera is subjected to person/D conversion by the person/D converter 1.2, and becomes digital image information M2 and B2, and the line memory 5.7
is memorized.

At the same time, the data of the line memory 6 in the first half of the -scanning period and the data of the line memory 8 in the second half of the -scanning period are sequentially read out from the line memory 6.8, and are outputted via the adder 10.11.

Similar to the output of the adder 9 mentioned above, this output signal is
After image conversion, the second scanning line 2'' of the image reproduction display device in FIG.
A two-screen image signal corresponding to ' is obtained.

Thereafter, scanning for one screen continues in the same manner, and the image is reproduced.

In this way, when playing the two screens of image person and B at the same time horizontally,
In particular, multiple images can be realized using only four sets of line memories 5 to 8 without using field memory circuits for two screens.

Effects of the Invention As described above, the present invention provides 2n frame memories for n images, and stores digital information for two scans per image in the first... The image information of the first frame corresponding to each image is sequentially read out, and then the image information of the second frame corresponding to each image is sequentially read out. By configuring this, it is possible to configure a composite image with a simple configuration, and the effect is great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image processing circuit according to an embodiment of the present invention, and FIG. 2 is a conceptual diagram of scanning lines for explaining the operation of the circuit. 1.2... Mu/D converter, 3.4... Switch Qo path, ts, 6. -r, a...Frame memory, 9°10.11...Adder.

Claims (1)

[Claims] Analog/digital conversion means for converting first and second analog image information into first and second digital image information, respectively, and an output destination of the first digital image information (2n-
1) A first switch means for switching between a scanning period and a 2n scanning period (where n is an integer of 1 or more), and a first switch means for switching the output destination of the second digital image information between a (2n-1) scanning period and a 2n scanning period. and a second switch means for switching between the first and second switches during (2n-1) scanning periods via the first switch means.
a first frame memory for storing digital image information of , a second frame memory for storing the first digital image information in a 2n scanning period via the first switch means, and the second switch means a third frame memory for storing the second digital image information during (2n-1) scanning periods via the second switch means;
a fourth frame memory that stores the second digital image information during n scanning periods; and after reading the digital image information from the first frame memory during 2n scanning periods, digital image information from the third frame memory; The first to read out
a second adding means for reading out the digital image information in the fourth frame memory after reading out the digital image information in the second frame memory during the (2n+1) scanning period;
an image processing circuit comprising: an adding means; and a third adding means that outputs the output of the second adding means after the output of the first adding means.