JPH0370288A - Scan converter - Google Patents

Abstract

PURPOSE:To prevent missing of a picture signal by converting a video signal of n-line while keeping a period interval or continuity of a brightness level when the video signal of n-line obtained by a 1st synchronizing signal is represented by a 2nd synchronizing signal of n'-line. CONSTITUTION:The address of readout control from video memories 16a, 16b is designated by a control circuit 13 so as to read the data sequentially in the Y axis and n-set of data in the Y axis direction is given sequentially by m-string to a D/A converter 18. When number of scanning lines of the video signal synchronously with the 2nd synchronizing signal is n', the sampling pulse is set so as to divide one line data into n' and m-string of n' data are written in the X axis to any of video memories 23a, 23b from the output of the A/D converter and when one frame write is finished, the signal is outputted to a 2nd D/A converter 27 via a changeover circuit 25. Thus, missing of the picture signal is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a scan converter, and more specifically, it converts a video signal controlled by a certain synchronization signal into a video signal controlled by UJ using a different synchronization signal. This article relates to a scan converter used in this case.

(Prior Art) In order to display a video signal controlled by a certain first synchronization signal on a CRT display or the like controlled by a different second synchronization signal, the synchronization signal of the video signal is changed to the second synchronization signal. have to be converted.

Conventional video signal conversion methods generally involve thinning out image signals, generating interpolation signals between scanning lines, or thinning out image signals on a frame-by-frame basis.

FIG. 6 is a diagram that does not show the configuration of a scan converter according to the conventional image signal thinning method disclosed in Japanese Patent Application Laid-open No. 63-142783.
6.016kHz, vertical synchronization frequency 54.65Hz,
The computer 1 output outputs a video signal controlled by a text control signal with a pixel signal of 21.645 MHz, a horizontal synchronization frequency of 15.7 Hz, a vertical synchronization frequency of 30 Hz, Pixel frequency is 6M
In order to display the output of the image pickup device 2 controlled by the Hz control signal on one CRT monitor 3 controlled by the text control signal, the output of the image pickup device 2 is processed into a plurality of bit numbers in the image processing device 4. , the image signal PIG is converted into an image signal PIG indicating a grayscale image, and an image synchronization signal (horizontal synchronization signal, vertical synchronization signal, and pixel signal) is extracted.
On the other hand, the extracted image synchronization signal is input to the timing control circuit 7.

The timing control circuit 7 operates the switching circuit 5 based on the input image synchronization signal, and performs writing control on which memory the image signal PIG is stored in, and also operates the switching circuit 8 based on the text synchronization signal input from the computer 1. is driven to perform read control so that the data written in the memories 6a and 6b is output to the adder circuit 9 at the next stage.

The operation of the switching circuit 5.8 is as shown in the same figure.
The contents of the memory 6b are outputted to the adder circuit 9.
When data is written to the memory 6a, the data in the memory 6a is outputted to the adder circuit 9 in a correlated manner, so that the memories 6a and 6b are sequentially written and read.

That is, in this method, image signals based on the first synchronization signal are once stored alternately in two memories every few screens,
By sequentially reading the image signals in the memory based on the text synchronization signal to be synchronized, an image signal synchronously converted into the text synchronization signal is output to the addition circuit 9, and further, the output of the addition circuit 9 is are displayed on the CRT monitor 3 as gray scale analog signals in the digital-to-analog converter 10 at the next stage.

When the output of the computer 1 and the output of the imaging device 812 are combined, the imaging signal synchronously converted to the text synchronization signal and the text video signal controlled by the text synchronization signal are combined in the adder circuit 9, and the combined signal is is displayed on the CRT monitor 3 via the digital-to-analog converter 10.

However, as shown in FIG. 6, the output of the scan converter controlled in this manner inevitably includes the image signal PIG from the image pickup device every few screens, and in this example, every other screen is read out to the adder circuit 9. Therefore, the video signal of the thinned out portion is erased according to the relationship between the repetition periods of both synchronization signals, and therefore, if it includes an image of a fast-moving object, the video signal can be accurately reproduced. The above conventional example shows a case where an image signal with a high synchronization signal is converted into one with a low synchronization signal, but conversely, when synchronizing a long-period synchronization signal with a short-period one, Adjacent 2 as shown in 1986-114674 etc.
An interpolated signal is generated by signal processing using two scanning line signals, and interpolation is performed between '4' of the scanning line.As is well known, the signals of scanning lines have a strong correlation not only in the horizontal direction but also in the vertical direction, so interpolation There is a problem in that the subsequent video signal loses continuity in time intervals and luminance signal levels, resulting in redundant or unnatural video.

<Object of the Invention> The present invention has been made in order to solve the problems of the conventional scan converter as described above. It is an object of the present invention to provide a scan converter that can obtain high-quality images without impairing the continuity of vertical time intervals or brightness levels of scanning lines.

(Summary of the Invention) In order to achieve this object distantly, the scan converter according to the present invention has a first switching system which inputs a digital signal of one frame of m dots on the X axis and n lines on the Y axis obtained by the first synchronization signal. means, a first memory consisting of two sets of video memories provided at the output end of the first switching means, and a video memory of the first memory selected by the first switching circuit; writing means; second switching means for selecting a video memory of the first memory not selected by the first switching circuit; and converting the video memory selected by the second switching circuit into a digital signal. reading means for sequentially reading out the converted video signals in the Y-axis direction; a first D/A converter for converting the read digital signals into analog video signals;
A second memory consisting of two sets of video memories and an analog video signal, which is the output of the first D/A converter, are used to store digital video signals of lines in Y@n' lines and m dots on the X axis. A first A/D converter for converting into a digital video signal; and a third A/D converter for switching into which memory of the 2Mi video memory of the second memory the video signal converted into a digital amount is written. a switching circuit; means for sequentially writing the video signals converted into digital quantities in the Y-axis direction into the second memory selected by the third switching circuit; a fourth switching circuit for selecting the video memory of the second memory; and n' from the video memory of the second memory selected by the fourth switching circuit in the means for sequentially reading out the four-shot image signals; a second D/A converter for converting the read digital video signal into an analog video signal; and reading of the first and second memories. It is equipped with a timing generator for generating timing signals necessary for reading/writing and clock signals necessary for the A/D converter and D/A converter, and generates the n-line video signal obtained by the first synchronization signal. It is characterized in that it is displayed in n° lines by the second synchronization signal.

(Example) Hereinafter, the present invention will be described in detail based on the example shown in the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 11 is an image processing device which inputs an image signal synchronized with the first synchronization signal and extracts the image synchronization signal, and the image signal output terminal of the image processing device Tl1l output is converted into a digital signal. It is connected to a first analog-to-digital converter (hereinafter referred to as A/D converter) 12, and its image synchronization signal output end is connected to a control circuit 13.

The output terminal of the A/D converter 12 is connected to a first switching circuit 15.
The output terminals a and b of the switching circuit 15 are connected to video memories 16a and 16b, respectively.

The output ends of the video memories 16a and 16b are connected to a second switching circuit 17, and the output ends of the switching circuit 17 are connected to a first digital-to-analog converter (hereinafter referred to as a D/A converter) 18 and a second A/A converter. A D converter 19 is connected in series, and the output end of the A/D converter 19 is connected to a third switching circuit 21.
is connected to.

Furthermore, the output terminal of the switching circuit 21 is connected to a video memory 23a,
23b, and the video memories 23a, 23b
The output end is connected to the fourth switching circuit 25, and the switching circuit 25
The output terminal of is connected to the second D/A converter 27.

Further, the control circuit 13 is connected to the first to fourth switching circuits 15, 17, 21 and 25, and periodically switches the switching circuits by sending out a control signal. , video memories 16 and 23
, the D/A converters 18 and 27 are connected to a timing generator 29;
9 supplies a clock signal and a memory address signal.

In the scan converter configured in this way, for example, a video signal of n lines in the Y-axis direction and m dots in the X-axis direction as shown in FIG. 2(a) is transferred in the Y-axis direction as shown in FIG. The case of converting into a video signal of n' line and m dots in the X-axis direction will be explained.

A video signal controlled by a certain synchronization signal is sent to the image processing device 11.
The image information and synchronization signal are separated from the video signal, and the image information is input to the A/D converter 12 at the next stage, and the synchronization signal is provided to the control circuit 13.

The A/D converter 12 is a timing generator 2
The desired value applied from 9 (8 for normal TV image information)
The input image information is converted into digital quantities of m pieces in the X-axis direction and n lines in the Y-axis direction by a sampling pulse SP of about MHz), and is written into one of the video memories 16ab via the switching circuit 15.

Further, the switching circuit 15 is controlled by a control signal synchronized with a frame synchronization signal output from the control circuit 13, so that the switching circuit 15 switches the video memory 16 for each frame.
Data is written alternately to a and 16b.

The switching circuit 17 provided at the next stage is also switched i9Jm by the frame synchronization signal output from the control circuit 13, and as shown in the figure, when the switching circuit 15 is connected to the video memory 16b and writing is performed, is switching circuit 1
7 is connected to the video memory 16a, and the switching circuit 1 is configured to read the contents written in the video memory.
It operates relative to 5.

Reading from the video memories 16a, 16bfull
l is a control circuit 1 that reads data sequentially in the Y-axis direction.
As a result, the D/A converter 18 manually outputs n pieces of data in the Y-axis direction in m columns in order, as shown in FIG. 3(a).

The D/A converter 18 converts the input digital signal into an analog signal again based on the tarok signal supplied from the timing generator 29, and
The signal is output to the next-stage A/D converter 19, where it is converted into a digital signal using sampling pulses supplied from two timing generators.

The sampling pulse is the second pulse as shown in FIG. 2(b).
If the number of scanning lines of the video signal synchronized with the synchronization signal is n', it is set to divide one line of data into n',
The A/D converter output is transferred to either of the video memories 23a, 23b in the Y-axis direction via the switching circuit 21.
' pieces of data are written in m columns in the X-axis direction, and when writing of one frame is completed, the second D
/A converter 27.

The switching circuits 21 and 27 are also the switching circuit l5.1 described above.
Similarly to 7, the switching is performed in a correlated manner based on the frame signal output from the control circuit 13, and when data is being written to one video memory, it operates to read data from the other video memory.

That is, the frame synchronization signal frequency of the data output from the video memories 23a and 23b is the same as the frame synchronization signal frequency of the input video signal, but the horizontal synchronization signal frequency is changed by changing the number of scanning lines. Become.

FIG. 4 is a diagram for explaining the signal state of the scan converter according to the present invention. For example, as shown in FIG. 60 Hz, (pulse interval 16.7
m5) If the horizontal synchronization signal frequency is 15.75kHz (pulse interval 63.5μs), the number of scanning lines in one frame is 262, and image information is superimposed between the horizontal synchronization signals, and the image processing circuit In step 11, the image information and the synchronization signal are separated and extracted. The extracted synchronization signal is input to the X1IJ control circuit 13, and the vertical synchronization signal, that is, 1
Switching circuits 15 and 1 based on the 6.7ms frequency signal
Activate 7.

On the other hand, the image information signal is sampled in the next stage A/D converter 12 and converted into a digital signal as shown in FIG. 4(b).

The sampling frequency is 8MH for normal video signals.
It is sufficient if the image information is about z, and the image information is approximately 5 per raster.
It is converted into a digital signal as a pixel signal of 00 dots,
In the video memory 16, 500 digital signals in the X-axis direction and 262 lines in the Y-axis direction are sequentially written.

Reading from the video memory 16 is performed by the memory address signal output from the timing generator as described above, and the memory address signal controls the video memory to sequentially read data in the Y-axis direction.

Therefore, as shown in FIG. 4(c), 262 digital signals are output from the video memory 16 to the D/A converter 18, where they are converted into analog signals, as shown in FIG. Obtain an analog signal as shown in d).

The second A/D converter 19 samples the desired frequency signal and converts it into a digital signal. For example, the frame synchronization signal frequency is 60H2 and the number of scanning lines is 41.
When displaying on three CRTs, sampling may be performed using a 25 kHz sampling pulse and digital conversion may be performed. As a result, a converted signal as shown in FIG. 4(e) is obtained. The converted signal is sequentially written into the video memory 23 in the Y-axis direction via the switching circuit 21, and after one frame has been written, the data in the video memory 23 is sequentially read out in the X-axis direction and sent via the second D/A converter. It is possible to obtain a video signal output that is converted into an analog signal and synchronized with the second synchronization signal.

That is, it is possible to convert signals of a desired number of scanning lines without impairing the mutual relationship of adjacent scanning lines in the Y-axis direction.

In the embodiment of the present invention, in order to convert moving image signals obtained by a video camera or the like in real time, the first and second memories are each divided into two sets, and writing/reading is performed alternately. If the video signal displays a still image or an image with little change, it is possible to configure the first and second memories as one each, and if the input video signal is already digitized. Needless to say, the first A/D converter can be omitted if the first A/D converter is provided.

Furthermore, in the embodiments of the present invention, a method of converting a non-interlaced video signal has been described, but the present invention is not limited to this, and the method is not limited to this, but the present invention is not limited to this method. It is clear that it can also be used in any case.

(Effects of the Invention) Since the present invention is configured and functions as described above, the video signal of n lines obtained by the first synchronization signal is
Since it is possible to perform conversion while maintaining the continuity of time intervals or brightness levels when displaying with the second synchronization signal of the line, it exhibits a remarkable effect in obtaining high-quality images without loss of image signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a scan converter according to the present invention, FIGS. 2(a) and (b) are diagrams schematically showing scanning lines, and FIGS. 3(a), (b), ( C) is a diagram showing reading/writing of memory in the scan converter according to the present invention, and FIGS. 4(a) to (e) are diagrams explaining signal states of the scan converter according to the present invention. 11... Image processing device, 12.19... A/D converter, 18.27... D/A converter, 16a,
16b, 23a, 23b---memory, 13...control circuit, 29...timing generator, 15.17
．． 21 and 25・Switching circuit hLWL

Claims (1)

[Claims] In a scan converter for displaying n lines of video signals obtained by a first synchronization signal on n' lines by a second synchronization signal, a first switching means for inputting a digital signal of m dots on the X axis and n lines on the Y axis; and a first memory consisting of two sets of video memories provided at the output end of the first switching means; means for writing the digital signal into the video memory of the first memory selected by the first switching circuit; and a second means for selecting the video memory of the first memory not selected by the first switching circuit. switching means; reading means for sequentially reading out video signals converted into digital signals from the video memory selected by the second switching circuit in the Y-axis direction; and converting the read digital signals into analog video signals. a first D/A converter, m dots, n'
A second memory consisting of two video memories for storing line digital video signals and an analog video signal which is the output of the first D/A converter are stored in n' lines on the Y axis and m dots on the X axis. A first A/D converter for converting the video signal into a digital video signal; and a second A/D converter for switching which memory to write the video signal converted into a digital amount into one of two sets of video memories. 3 switching circuit; means for sequentially writing the video signal converted into digital quantity into the second memory selected by the third switching circuit in the Y-axis direction; a fourth switching circuit for selecting a video memory of the second memory that is not selected by the fourth switching circuit; means for sequentially reading video signals converted into digital quantities for n lines; a second D/A converter for converting the read digital video signals into analog video signals; and the first D/A converter. , a timing generator for generating a timing signal necessary for reading/writing a second memory, a clock signal necessary for an A/D converter, a D/A converter, etc.