JPH0515349B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television receiver in which another video image can be inserted into a part of the image on the screen.

BACKGROUND ART A conceptual diagram of a two-screen television is shown in FIG. This is an example in which a child screen 502 is combined with a main screen 501. The two main basic functions of a dual-screen TV are:

(a) The synchronization of the composite video and the composite video is unrelated to each other; in other words, the phase and frequency are different, so the synchronization of the composite video is the same as the synchronization of the composite video (in the case of CRT,
A function to align the time axis to match the deflection synchronization signal).

(b) A function to reduce the composite screen from its original size when compositing screens.

There is a conventional example in which such a function is implemented using a buffer memory and a one-field memory.
(For example, see Japanese Patent Publication No. 55-39472.) To explain this example, first, the relationship between the two-screen television circuit section and the peripheral circuits will be explained with reference to FIG. The input video switching circuit section 401 selects and switches between the parent (to be synthesized) video and the child (composed) video.
It is. The input is, for example, a plurality of tuner/ViF circuits 402, 403 or other video equipment 4.
04 (for example, VGR, disk, camera, etc.), one of which is supplied to the parent video processing circuit 405 and the parent synchronization separation circuit 406, and the other one is supplied to the child video processing circuit 405 and the parent synchronization separation circuit 406. The signal is supplied to the processing circuit section 407 and the child synchronization separation circuit section 408 . In the dual-screen television circuit section 1, the video signal from the child video processing circuit 407 (input from terminal 2) is basically converted into the synchronization signal from the child sync separation circuit section 408 (input from terminal 3). ), the video signal for synthesis is output from the terminal 5 by writing it once into the memory and reading it from the memory using the synchronization signal from the parent synchronization separation circuit section 406 (input from the terminal 4). This video signal is transferred to the output signal switching unit 40
At step 9, it is combined with the parent image from the parent image processing circuit section 405 and output to the CRT 410 which is deflected by the synchronization signal from the parent synchronization separation circuit section 406. FIG. 6 is a block diagram of a conventional example of the dual-screen television circuit section 1, focusing on the signal flow. 2 and 5 correspond to Figure 4,
They are respectively a child video signal input terminal and a video signal output terminal for synthesis. Reference numeral 601 is a buffer memory for horizontal scanning, and reference numeral 602 is a 1-field memory that can be read and written in every horizontal period (hereinafter abbreviated as H). As mentioned above, the two main basic functions of a dual-screen TV are as follows. In terms of circuit design, when aligning the time axes of the parent and child, writing and reading from memory cannot be done at exactly the same time, so how can this be done? The key point is how to organize time relationships. A case in which the size of the child screen 502 is 1/3 vertically by 1/3 horizontally will be described with reference to the timing diagram of FIG. 7 with respect to the main screen 501. First, as shown in FIG. 7a, data is written into the buffer memory 601 in accordance with the child H. However, since the vertical direction is 1/3, you only need to write 1H in 3H. Since the buffer memory 601 only has a capacity of 1H,
Before the next write, data must be sent to the field memory 602, which is the main memory (that is, read from the buffer memory 601 and written to the field memory 602). The timing is such that the buffer memory 601 is not performing a write operation and the field memory 60
2 is a period in which no read operation is performed. As shown in FIG. 7c, the field memory 602 is read out every H in accordance with the parent H during the period when the child screen 502 is output on the screen. However, horizontal direction 1/
3, the data is read out at approximately three times the speed of writing to the field memory 602. During the period when the child screen 502 is output, the field memory 602 has little free time, but if the writing period of the buffer memory 601 in FIG. memory 60
As mentioned above, the read period of 2 is about 1/3,
By 1/4×H, there is a time interval of approximately 3/4H between readings from the field memory 602.
In other words, use this time to buffer memory 6.
01 data can be sent to the field memory 602.

The problem that the invention seeks to solve The above conventional example has the following three problems.

(1) There is a problem that information around the screen cannot be displayed on the child screen 502. Ideally, the information display area of the main screen 501 and the child screen 502 should be equal. Consider the sample period within H for the small screen information required at that time. Of the horizontal period, the period during which information is actually carried is about 0.835H. If 90% of that is displayed on the screen due to the characteristics of the TV receiver, then 0.835H x 0.9 = 0.75H. Even in the conventional method, if the absolute values of the H periods of the parent and child are the same, there is no problem because 3/4 data of the child's H can be handled. However, in reality, depending on the operation of the video equipment 404 that is the video signal source for the sub-screen, the normal H, that is, approximately
Since there are deviations from 63.5 μsec, in order to maintain the read/write relationship of the field memory 602 explained in FIG. 7c in a sufficiently safe manner even when the child's H is longer than the parent's H, The sample period within H for child screen information must be designed to be much shorter than 0.75H. For this reason, information on the left and right sides of the screen is cut off, which is particularly inconvenient when there is text information in the cut-off area.

(2) Field memory 602 which is main memory
As such, a fast readout speed is required.
This is because compression in the H direction is performed at the stage of reading from the main memory, as shown in FIG. 7c. High-speed main memory is expensive, so in order to reduce capacity, instead of storing one frame of data, one field memory is used, which is half that amount. However, this results in significant image quality deterioration when the child screen 502 is a still image. That is, when shooting a moving image, there is no problem because the contents of the main memory are always updated, but when shooting a still image, in other words, data writing to the main memory is stopped and the data is repeatedly stored in the field memory 602.
When reading the contents of , the contents of even and odd fields are equal, so the vertical resolution is halved. If you try to write down certain text information as a still image, you will be told that it cannot be read.

(3) Double scan cannot be supported.

The period of the parent horizontal period signal is half of 63.5μsec,
That is, if this is called a double scan, in the conventional method c in FIG. 7 is doubled, so the child screen is not like 502 in FIG. 5 but 802 in FIG.
This results in two vertically elongated sub-screens with the same content as in 803, which is inconvenient.

Means for Solving the Problems The dual-screen television receiver of the present invention first reads out the video signal input for synthesis pixel by pixel, stores it in a writable one-frame memory, and then converts it into a signal synchronized with the horizontal period. Through two sets of readable and writable shift registers for one horizontal period, while writing to one shift register, reading is performed from the other shift register, and this is performed alternately to convert the video signal to be synthesized. It is output as a video signal to be synthesized.

Effect This will be explained in terms of the three problems mentioned above.

For problem (1), two sets of shift registers are read and written alternately, and in principle all the data in H of the sub-screen can be taken in, and the peripheral information of the screen will not be cut off.

Regarding problem (2), in the 1-frame memory that is the main memory, data compression in the H direction is not performed, but is performed in the shift register afterward, so it is necessary to reduce the operating speed of the main memory. I can do it. That is, an inexpensive main memory can be used. Shift registers are simple in operation and have a small capacity, so they account for a small portion of the cost. In the end, even if the main memory capacity is increased to one frame, which is twice the capacity of one field, the cost of the entire system can be realized at a lower cost than in the conventional method. Furthermore, since the main memory has one frame's worth, there is no deterioration in image quality when a still image is taken.

For problem (3), while reading one of the two shift registers, the output of this shift register is used as a video signal for synthesis and is returned to the input of this shift register, and the other shift register is kept in memory for this period. Since this is repeated alternately, no data errors will occur in the composite video signal output even if the horizontal frequency is doubled.

Embodiment Hereinafter, a two-screen television receiver according to an embodiment of the present invention will be described with reference to FIG. This figure corresponds to the two-screen television circuit section 1 shown in FIG. The child video signal is input from terminal 2 in FIG. This terminal 2 is shown in more detail at X in Figure 1.
These are video signal input terminals 101, 102, and 103 to which Y and Z signals are input. here,
The X, Y, and Z video signals may be primary color signals of R, G, and B, or color difference signals of R-Y, B-Y, and Y. In general, it would be more advantageous to use color difference signals in terms of reducing memory capacity. The video signal input here is sent to an analog-to-digital conversion circuit 104,
The signal is input to 105 and 106 and converted into a 6-bit digital signal. These digital signals are input to the multiplexer 107 and are chronologically
Each Y and Z digital signal is processed and latched one after another in a data latch 108, and is input to a frame memory 109 that can be written to and read out pixel by pixel. The output of the frame memory 109 is received by a data latch 110, and a switching circuit 112 and a switching circuit 113 select between a shift register 114 and a shift register 116 that can be read and written every horizontal period.
Or it is transmitted via the switching circuit 115. The outputs of the shift registers 114 and 116 are connected to the switching circuit 117.
is input to the demultiplexer 119 via the data latch 118, and the time series signal is
The signals are converted into Y and Z digital signals, converted back to analog signals by digital-to-analog converters 120, 121, and 122, and outputted from terminals 124, 126, and 126 to X and Z signals.
Obtain Y and Z video signals for synthesis. That is, this corresponds to the output video signal appearing at terminal 5 in FIG.

Further, the output from the switching circuit 117 is sent to the shift register 11 via the switching circuit 113 and the switching circuit 115.
4 or 116 again. FIG. 2 shows the block 111 in FIG. 1 in more detail. 210 corresponds to the switching circuit 112 in FIG. 1, 213 corresponds to the switching circuit 113, and 21 corresponds to circuit 115
4. The shift register 217 corresponds to the shift register 114, the shift register 218 corresponds to the shift register 116, the shift register 227 corresponds to the switching circuit 117, and the data latch 229 corresponds to the data latch 118. be.

In FIG. 1, a clock for writing to the frame memory 109 is generated by a clock generation circuit section 127, and a clock for reading data from the frame memory 109 is generated by a clock generation circuit section 128. Further, the output of the clock generation circuit section 128 is used as a write clock for the shift register 114 and shift register 116, and the read clock for the shift register 114 and shift register 116 is obtained from the clock generation circuit section 129. In FIG. 2, WCK is the output clock of the clock generation circuit section 128 of FIG.
In the figure, RCK is the output clock of the clock generation circuit section 129 of FIG.

First, in FIG. 4, the parent synchronization separation circuit section 40
The case where the horizontal synchronization signal of No. 6 is 15.7KHz will be explained. FIG. 3 shows an operation timing diagram of FIG. 2. Here, Hp is the normal horizontal sync signal (15.75K
Hz), Hpw is twice that horizontal synchronization signal (30.5KHz)
, ARp is the readout gate signal of shift register 217, AWp is shift register 2
17 is the write gate signal, BRp is the read gate signal of the shift register 218,
BWp is a write gate signal for the shift register 218, and ABSW is a control signal for the switching circuit 210, switching circuit 213, switching circuit 214, and switching circuit 227.

First, when the horizontal synchronization signal is 15.75 KHz, a timing waveform as shown in 1 (during normal scan) in FIG. 3, which is called normal scan, is input to each terminal in FIG. 2. Here, if the switching circuits 210 to 227 are on the a side, the signal 206 from the data latch 110 is on the a side of the switching circuit 210.
side, i.e., via the data bus 212, the switching circuit 2
14c, that is, input to the shift register 218 via the bus 216. At this time, the write pulse BWp of the shift register 218 becomes "H" and the write clock WCK is input to the line 232 via the AND gate 222 and the OR gate 224. After that, the read pulse ARp of the shift register 217 becomes "H", and the AND gate 219 and OR gate 223
The read clock RCK is connected to line 231 via
The contents of the shift register 217 are output to the bus 228 via the bus 225 and the switching circuit 227.
The data is then output to the data latch 229. next,
Switching circuit 210 to switching circuit 227 with ABSW
to the side. As before, this time writing to shift register 217 and reading from shift register 218. In this way, shift registers 217
It can be seen that since writing and reading are performed in and 218, no data is lost.

Next, the horizontal synchronization signal is twice 15.75Hz, that is, 30.5KHz
The case will be explained below. This case will be called a double scan. As shown in the timing chart 2 [double scan] in FIG. 3, writing to each shift register 217, 218,
Performs read control. The amount of information in the horizontal direction is
Since it is the same as the case of 15.5KHz, the writing time is
The same time is required as in the case of 15.75KHz. Switching signals of switching circuit 210 to switching circuit 227
ABSW is switched once to 2H of Hpw with the same correlation as Hp of normal scan.

First, as before, switching circuit 210 to switching circuit 2
The case where 27 is on the a side will be explained.
While writing to the shift register 218 with Bwp, the shift register 217 is read twice with ARp when Hpw is "H". Here, since the readout output is transmitted from the bus 228 via the switching circuit 213 and is input to the shift register 217, the same data can be read out. Here, it is assumed that both shift registers 217 and 218 have a capacity of 1H. Next, the switching circuits 210 to 227 are switched to the b side by ABSW, and while writing to the shift register 217, the shift register 218 is read twice in succession when Hpw is "H". By repeating this process alternately, a normal composite video signal can be obtained without missing data even during double scan. Also, even during double scan,
The same frame memory as used for normal scan may be used, and it is possible to configure the frame memory using an inexpensive memory.

Effects of the Invention The two-screen TV receiver of the present invention uses a frame memory that can read and write for each pixel, so when viewed in units of H, writing can be matched to the child H, and reading can be matched to the parent H. I can do it. The post buffer memory performs synchronization at the pixel level and compresses the data output period in the H direction. The effects will be described in relation to the three problems mentioned in the section of problems to be solved by the invention.

(1) Regarding the peripheral cut-off of sub-screen information.

In the circuit of the present invention, the write period of the small screen signal is limited when the read periods of adjacent H's of the frame memory overlap. If H of the child and H of the parent are equal, it is possible to write all data during the H period. As the cycle of the parent H becomes smaller relative to the child H, the writeable period becomes shorter, but if the write period is set to 0.75H according to the above calculation, the relative rate of 25% per H becomes shorter. There is sufficient margin of error. Therefore, peripheral cutoff of child screen information does not occur. Note that, according to the circuit of the present invention, the reading period of the child surface information can be varied up to a ratio of 1:1 with the writing period. Therefore, the size of the child screen can be arbitrarily set up to the maximum size of the parent screen, and is not limited to 1/3 height x 1/3 width as used in the explanation.

(2) Regarding the issue of main memory read/write speed.

A comparison will be made between the conventional example and the present invention. It is assumed that the output period in the H direction of the child screen is T _h , the number of pixels (number of samples) per H is n, and the cycle of reading and writing to the memory is equal to T _c . In the conventional example, T _h
The highest speed is when n pieces of data are read during this time, and T _c = T _h ÷ n. In the present invention, the speed is highest when the read and write periods of the frame memory overlap, and n pieces of data are read and n pieces of data are written in a period of 3×T _h . , T _c =3×T _h ÷n ÷2=1.5×T _h ÷n.

In other words, the main memory of the present invention can be 1.5 times slower than the conventional example. here,
Try substituting specific values. T _h is 1/3 of the writing period of sub-screen data, assuming it is 0.75H.
It is. Although n is a pixel, it is not considered as an actual pixel on the screen, but as a unit of data input/output to the memory. When storing color video signals in memory, it is common to separate them into luminance and color difference signals to reduce memory capacity, and the sampling rate of each is set to 4:1 for such applications. is normal. Therefore, in order to match the speed of luminance and color difference data, data is synthesized before being stored in memory. The number of unit data per H at this point is considered to be n. It is a good idea to select 2 to the nth power in terms of memory configuration, and in consideration of image quality, n=64. In this case, T _c of the conventional example = 248 nsec T _c of the present invention = 372 nsec The reason why this difference greatly affects the cost is as follows. There are two general types of digital RAM: static RAM and dynamic RAM. The former is fast and the latter is slow, and with current technology, the boundary between them is
It is about 250nsec. Considering the design margin, the operating speed required for conventional main memory is:
I have no choice but to use static RAM. On the other hand, in the present invention, the dynamic RAM can be sufficiently used as the main memory since it may be 1.5 times slower than the conventional example. Comparing the memory cost per unit capacity, dynamic RAM is
Due to the simplicity of its storage method, the circuit size within the memory is significantly smaller, about 1/4 of that of static RAM. In other words, even if the main memory is doubled in capacity to one frame and the quality of still images is improved, the price of the entire system can be kept lower than in the conventional case.
This is extremely advantageous in practical terms.

(3) Compatibility with double scan In the circuit of the present invention, as explained above, by changing the read and write timings during double scan, it is possible to display a sub-screen normally even during double scan.

Also, shift registers A and B shown here are not limited to shift registers.
It goes without saying that you can use memory such as RAM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a two-screen television receiver according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of block 111 in FIG. 1, and FIG. 3 is a diagram for explaining the operation of FIG. 2. Timing diagram, Fig. 4 is a block diagram of the entire two-screen TV receiver, Fig. 5 is a conceptual diagram of a two-screen TV, Fig. 6 is a main block diagram of a conventional two-screen TV, and Fig. 7 is a conventional two-screen TV receiver. FIG. 8 is a conceptual diagram of a conventional two-screen television during double scanning. DESCRIPTION OF SYMBOLS 1...Two-screen television circuit section, 2...Composition side video signal input terminal, 3...Horizontal synchronization signal input terminal for composition side video, 4...Horizontal synchronization signal input terminal for composite side video, 5...Composition video signal output terminal, 104
~106...Analog-digital converter, 10
7...Multiplexer, 108,110,1
18, 229...Data latch, 109...Frame memory, 112, 113, 115, 117
...Switching circuit, 210, 213, 214, 227
...Switching circuit, 114, 116...Shift register (1H memory), 217,218...Shift register (1H memory), 119...Demultiplexer, 120-122...Digital-to-analog converter, 219-222 ...and gate, 2
23,224...Or Gate, 402,403
...Tuner, ViF circuit section, 404...Video equipment, 401...Input video switching circuit section, 405...
...Parent video processing circuit section, 406...Parent synchronization separation circuit section, 407...Child video processing circuit section, 408
... Child synchronization separation circuit section, 409 ... Output signal switching section, 410 ... CRT, 501, 801 ... Main screen, 502, 802, 803 ... Child screen.

Claims (1)

[Claims] A first clock synchronized with the horizontal synchronization signal of the composite side video, which has a one-frame memory that can be read and written for each pixel, and two sets of buffer memories for a horizontal period that can be read and written for each horizontal period; It has a circuit that generates a second clock whose phase is 180 degrees different from the first clock, and a third clock that is synchronized with the horizontal synchronization signal of the image to be synthesized, and the writing to the frame memory is performed by: Reading of the frame memory is performed using the first clock in accordance with the horizontal synchronization of the video to be synthesized, and the readout of the frame memory is performed at the second clock in accordance with the horizontal synchronization of the video to be combined.
The reading and writing of the two sets of buffer memories are alternately switched in accordance with the horizontal synchronization of the video to be synthesized, and the writing is performed using the second clock, and the reading is performed using the third clock. , a two-screen television receiver comprising a switching circuit for reading out the buffer memory once or twice during the horizontal synchronization period of images to be synthesized.