KR920002048B1 - Television system - Google Patents

Abstract

a microprocessor (20) for controlling the system; an A/D converter (30) for converting picture- in-picture (PIP) data signals to digital signals; an analogue switch (SW1) for supplying the PIP data to the A/D converter (30); a first data converting section (40) for converting the output of the A/D converter to another type of data; a dual port memory (50) for receiving the data from the first data converting section (40) and for outputting the data to a second port (P2); a second data converting section (41) for further converting the output of the second port (P2); a control decoding section (60) for designating the starting point; a clock generating section (80) for generating read clocks; and second and third converters (91,92) for further converting the output of the second data converting section.

Description

Magnification and reduction circuit of subscreen of TV or video tape recorder

1 is a circuit diagram of the present invention.

2 is a change state diagram of a car screen according to the present invention.

* Explanation of symbols for main parts of the drawings

10: keyboard 20: micom

30: A-D converter 40,41: First and second data converter

50: dual port memory 60: control decoder

70: horizontal window signal generator 70: vertical window signal generator

80: clock generator 90-92: first-3D-A converter

The present invention relates to a television (TV) or a video tape recorder (VTR) having a picture in picture (PIP) function in an image processing system. In particular, the present invention relates to a circuit and a method capable of enlarging or reducing the size of a magnetic screen.

In general, in an image processing apparatus such as a television or a VTR, the PIP function refers to the display of the child screen together in a portion of the mother screen displayed by using the entire screen.

In the conventional TV or VTR mother screen having the PIP function, the size of the child screen allocated and displayed in a certain section of the mother screen is fixed at a constant level, and the child screen is fixed to the upper, lower, left, right and right sides of the mother screen according to the viewer's selection. Was supposed to be moved to. Therefore, although the contents of a specific part of the parent screen can be enlarged or reduced and displayed on the child screen, the size of the child screen itself cannot be enlarged or reduced.

Accordingly, an object of the present invention is to provide a magnetic screen enlargement and reduction circuit and method that can display a magnified or reduced size of a magnetic screen to a movable range of the magnetic screen in a TV or VTR having a PIP function.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

라함)와 로우(Row) 및 칼럼(Column)어드레스와 전송제어신호 및 리드클럭 등을 발생하는 클럭발생부(80)와, 상기 제2데이터변환부(41)의 제1출력포트(P4)의 디지털 Y신호 출력을 아날로그 Y신호로 변환하여 칼러 합성부로 출력하는 제1디지탈－아날로그(Digital－Analog; 이하 D－A라함) 변환기(90)와, 상기 제2데이타 변환부(41)의 제2출력포트(P5)의 디지털 R－Y신호출력을 아날로그 R－Y신호로 변환하여 상기 칼러 합성부로 출력하는 제2D－A변환기(91)와, 상기 제2디지탈변환부(41)의 제3출력포트(P6)의 디지털 B－Y신호출력을 아날로그 B－Y신호로 변환하여 상기 칼러합성부로 출력하는 제3D－A변환기(92)로 구성하며, 제2a-d도는 본 발명에 의해 스크린상에 디스플레이되는 자화면의 확대 및 축소상태도로서, 제2a도는 예를 들어 모화면의 우측 하단에 위치한 기본 크기의 자화면 상태를 나타낸 것이고, 제2b도는 제2a도에 도시한 자화면을 수평방향으로 확대한 상태를 나타낸 것이며, 다)는 가)에 도시한 자화면을 수직방향으로 확대한 상태를 나타낸 것이고, 제2d도는 제2a도에 도시한 자화면을 수평 및 수직 방향으로 확대한 상태를 나타낸 것이다.1 is a circuit diagram of the present invention, a keyboard 10 for inputting enlarged and reduced information of a child screen and other function selection signals, and a microcomputer 20 for controlling the entire system according to an input from the keyboard 10. And an analog-digital digital signal for sequentially converting an analog color difference signal for a sub picture applied from a color difference separator into a digital signal of a first predetermined bit n under a predetermined control. ) A switching operation is performed by the converter 30 and the switching control signal applied from the switching control signal generator, and the Y, R-Y, and B-Y signals, which are the color difference signals for the magnetic screen supplied from the color difference separator, are sequentially An analog switch SW1 for transmitting to the D-D converter 30 and a first for converting the output of the A-D converter 30 into digital data of a second predetermined bit R and outputting the digital data in a fourth predetermined period. A data converter 40 and the first Dual port memory for inputting and storing the output of the converter conversion unit 40 to the first port P1 and reading the stored data under a predetermined control and outputting the stored data through the second port P2 in units of second predetermined bits. And the output of the second port P2 of the dual port memory 50 to be converted into digital data of the first predetermined bit n, and then the first to third output ports P4 at a fifth predetermined period. A horizontal window for generating a horizontal window signal occupying any section of the horizontal scanning period by inputting the second data conversion section 41 sequentially outputting through -P6 and the horizontal synchronizing signal 105 from the synchronization separating section; A vertical window signal generator T1 for inputting a vertical synchronization signal 104 from the signal generator 70 and the sync separator to generate a vertical window signal occupying an arbitrary period of the vertical scan period, and the microcomputer By thawing the screen size control signal applied from the 20 The control decoder 60 for controlling the horizontal and vertical window generators 70 and 71 to designate the start positions of the horizontal and vertical window signals, and the horizontal and vertical sync signals 105 and 104 applied from the synchronous synchronization separator. Accordingly, the first clock 108 of the eighth predetermined frequency and the second clock 109 of the ninth predetermined scan frequency applied from the division circuit unit are divided so that the output periods of the first and second data converters 40 and 41 are divided. First and second latch signals 110 and 111 for controlling the control signal, and the dual port memory 50 sequentially stores the sub picture data and is applied from the horizontal and vertical window signal generators 70 and 71. Read / write bar (Read / write bar: or less) to read and output the sub-screen data for a period corresponding to the horizontal and vertical window signal

And the clock generator 80 generating the row and column addresses, the transmission control signal and the read clock, and the first output port P4 of the second data converter 41. A first digital-analog (D-A) converter 90 for converting the digital Y signal output into an analog Y signal and outputting the analog Y signal to a color combining unit; and a second of the second data converting unit 41. A third output of the second digital conversion section 41 and the second D-A converter 91 for converting the digital R-Y signal output of the output port P5 into an analog R-Y signal and outputting the analog R-Y signal. A third D-A converter 92 converts the digital B-Y signal output of the port P6 into an analog B-Y signal and outputs it to the color synthesizing unit. Figure 2a shows a magnified and reduced state of the displayed child screen. The state of the screen is shown, and FIG. 2b is a state in which the child screen shown in FIG. 2a is enlarged in the horizontal direction, and c) is a state in which the child screen shown in a) is enlarged in the vertical direction. FIG. 2D shows an enlarged state of the magnetic screen shown in FIG. 2A in the horizontal and vertical directions.

Based on the above configuration, the present invention will be described in detail with reference to FIGS.

First, the A-D converter 30 and the 1 -3D-A converter 90-92 in the first diagram are conventional circuits, and the dual port memory 50 is also a commercially available memory device, and the control decoder 60 and the keyboard. (10) and the microcomputer 20 are known facts, and the first and second data converters 40 and 41 and the horizontal and vertical window signal generators 70 and 71 can also be implemented by those skilled in the art. It is obvious. Next, an operation of changing the size of the child screen by adjusting the start position of the child screen while the data in the memory is constant using these components will be described.

When the viewer manipulates the keyboard 10 to implement a mosaic screen on the screen by increasing or decreasing the size of the child screen, the keyboard 10 generates a corresponding function selection signal to convert the size of the child screen to the microcomputer 20. Will print

Then, the microcomputer 20 synchronizes a plurality of screen control signals with its own generated pulse signal to the control decoder 60 through a line 101 composed of a control line, a pulse line, and a recognition line together with a data recognition signal. Output

At this time, the control decoder 60 reads the size change of the sub picture by recognizing and decoding the screen control signal input in synchronization with the pulse signal from the microcomputer 20 by the data recognition signal, and according to the read result. A horizontal width deformation signal and a vertical width change signal in digital form corresponding to the change amount input by the viewer are generated and output to the horizontal and vertical window signal generators 70 and 71 through the two control bus lines 102 and 103.

The horizontal width change signal is inputted from the control decoder 60 through the control bus line 102, and during the horizontal scan period between the horizontal synchronization signals applied through the line 105, Alternatively, a horizontal window signal having a low logic state is generated and output to the clock generator 80 through the line 107.

Meanwhile, the vertical window signal generator 71 also inputs a vertical width change signal from the control decoder 60 through the control bus line 103 and between the vertical synchronization signals applied from the frequency divider circuit through the line 104. During the vertical scanning period, a vertical window signal having a high or low logic state is generated during the vertical width change and is output to the clock generator 80 through the line 106.

신호, 전송제어신호를 발생하며, 또한 두 라인(106,107)을 통해 수평 및 수직윈도우신호발생부(70,71)로부터 인가되는 수평 및 수직윈도우신호의 윈도우기간동안에 주파수가 다른 동일수의 리드클럭을 발생하여 제1래치신호는 라인(110)으로, 제2래치신호는 라인(111)으로, 전송제어신호는 라인(112)으로,

신호는 라인(113)으로, 리드클럭은 라인(114)으로, 어드레스 버스라인(115)을 통해 각각 출력한다.Then, the clock generator 80 transfers the first clock of the eighth predetermined frequency and the second clock of the ninth predetermined frequency applied from the frequency divider circuit through the two lines 108 and 109 to the two lines 104 and 105. An address of the third predetermined number of bits 1 composed of the first and second latch signals, the row address and the column address, by dividing and counting with a plurality of preset division ratios using the applied vertical and horizontal synchronization signals;

Signal and transmission control signal, and through the two lines 106 and 107, the same number of lead clocks having different frequencies during the window period of the horizontal and vertical window signals applied from the horizontal and vertical window signal generators 70 and 71 The first latch signal to line 110, the second latch signal to line 111, the transmission control signal to line 112,

The signal is output to the line 113, the read clock to the line 114, and through the address bus line 115, respectively.

Then, the operation process of writing the sub picture data in the dual port memory 50 is as follows. An analog type luminance signal (hereinafter referred to as Y) and a blue signal which are output from the chrominance separating unit via the line 116 from the analog switch SW1 which switches by the switching control signal applied from the switching control signal generator. (Blue; hereinafter referred to as B) -Y and red signal (hereinafter referred to as R) -Y in order of R-Y, Y, Y, the A-D converter 30 sequentially inputs the input signal. A predetermined number of bits (assuming n = 6) and a digital signal are converted and output to the first data converter 40 through the bus line 117.

The first data converter 40 converts the digital data of the first predetermined number of bits (n = 6) of the A-D converter 30 input through the bus line 117 to a second predetermined number of bits (here Converts to digital data of R < 4 > and latches by the first latch signal applied from the clock generation unit 80 through the line 110, thereby providing a dual port at a fourth predetermined period through the bus line 118. The first latch signal is a clock signal having a period 1.5 times faster than the output period of the A-D converter 30. The first latch signal is output to the first port P1 of the memory 50. The fourth predetermined period of 40 is 1.5 times faster than the output period of the A-D converter 30, which is determined by the ratio between the number of conversion bits of the A-D converter 30 and the number of input terminals of the dual port memory 50. Is determined.

신호의 라이트싸이클 동안에 상기

신호와 함께 인가되는 어드레스에 따라 상기 제2소정비트수(R＝4)의 디지털데이터를 로우어드레스에 해당하는 번지수와 칼럼어드레스에 해당하는 번지수에 저장한다.As described above, the dual port memory 50 for inputting the second predetermined number of bits (R = 4) of digital data from the first data converter 40 through the bus line 118 to the first port P1 is described above. Applied via line 113

Reminders during the light cycle of the signal

The second predetermined number of bits (R = 4) of the digital data is stored in the address corresponding to the low address and the address corresponding to the column address according to the address applied with the signal.

Next, an operation process of reading the sub picture data stored in the dual port memory 50 in synchronization with the read clock according to the vertical and horizontal width change amounts will be described.

리드싸이클에 의해 독출되어진 로우어드레스에 해당하는 번지내의 데이터량(스크린의 1수평 주사기간에 해당하는 각 돗트데이터들)을 R1/

라이트싸이클 동안중 상기 수평윈도우신호기간에 상기 클럭발생부(80)로부터 라인(114)을 통해 제어포트로 인가되는 리드클럭에 의해 제2소정비트수(R＝4)단위로 제2포트(P2)와 버스라인(119)을 통해 제2데이터변환부(41)로 출력한다. 이때 상기 출력되는 데이터들로 구성되는 화면은 수평 및 수직 윈도우 신호의 상하 및 좌우폭에 의해 제2a-d도에 도시한 자화면 형태와 같다.The dual port memory 50 is applied through a bus line 113 and a transmission control signal applied from the clock generator 80 to the control port through the line 112.

The amount of data in the address corresponding to the low address read out by the lead cycle (each dot data corresponding to one horizontal syringe on the screen) is R1 /

The second port P2 in units of a second predetermined number of bits (R = 4) by a read clock applied from the clock generator 80 to the control port through the line 114 during the horizontal window signal period during the write cycle. ) And to the second data conversion unit 41 through the bus line 119. At this time, the screen composed of the output data has the same shape as the sub picture shown in FIGS. 2a-d by the horizontal and vertical window signals.

Here, as shown in FIG. 2C, if the number of times is increased (or reduced) n times in the vertical direction, data is read from the memory without changing the horizontal clock, but the number of the horizontal lines is counted to obtain the same address. By reading t more times (t> 0), the resolution can be compensated vertically using the data in the limited memory.

Meanwhile, the second data converter 41 for inputting a second latch signal from the clock generator 80 through the line 111 is connected to the second port of the dual port memory 50 through the bus line 119. The digital data of the second predetermined number of bits sequentially applied from (P2) is converted into Y, B-Y, R-Y digital data of the first predetermined number of bits (n = 6), and the Y digital data is output to the first output. The B-Y digital data is transferred to the first D-A converter 90 through the port Pr and the bus line 120, and the second D-A converter 91 is connected to the second output port P5 and the bus line 121. The R-Y digital data is output to the 3D-A converter 92 through the third output port P6 and the bus line 122. The clock period of the second latch signal is the period of the read clock. It has a clock number corresponding to 1.5 times.

At this time, the first to third D-A converters 90 to 92 respectively convert Y, B-Y, and R-Y digital data input through the bus lines 120-122 to analog Y, B-Y, and R-Y. Is converted into the color combining unit and outputted through each line 123-125.

Then, the color synthesizing unit switches the color difference signal constituting the mother screen and the color difference signal of the first to third 3D-A converters 90 to 92 to form a PIP screen, and then synthesizes the configured color difference signals as shown in 2a-d. Will print on the screen.

As described above, the present invention has an advantage of preventing eye discomfort because the screen can be enlarged and reduced by adjusting the frequency of the lead clock so that the viewer can appropriately adjust the size of the screen to a desired size.

Claims (2)

An image processing system comprising a color difference separator, a frequency divider circuit, a synchronization separator, a switching control signal generator, and a color synthesizer, comprising: a keyboard 10 for inputting magnification and reduction information of a child screen and other function selection signals; The microcomputer 20 for controlling the entire system according to the input from the keyboard 10 and the analog color difference signal for the sub picture applied from the chrominance separating unit are sequentially input under a predetermined control to receive the first predetermined bit n. A, D-converter 30 for converting to a digital signal of the digital signal, and Y, R-, which are color difference signals for sub-screens supplied from the color difference separator, by switching operation by the switching control signal applied from the switching control signal generator. Analog switches SW1 for sequentially transmitting Y, B-Y signals to the A-D converter 30 and converting outputs of the A-D converter 30 to digital data of a second predetermined bit R. Fourth predetermined cycle The first data converter 40 and the output of the first data converter 40 are output to the first port P1, and the second data bit is read and stored under a predetermined control. The dual port memory 50 outputs through the second port P2 in units of (R) and the output of the second port P2 of the dual port memory 50 to receive the first predetermined bit n. A second data converter 41 for converting digital data and sequentially outputting through the first to third output ports P4 to P6 at a fifth predetermined period; and a horizontal synchronization signal 105 from the synchronization separator. A horizontal window signal generator 70 for generating a horizontal window signal occupying an arbitrary period of the horizontal scanning period, and a vertical synchronization signal 104 is inputted from the synchronization separating part to occupy any period of the vertical scanning period. A vertical window signal generator 71 for generating a vertical window signal, and the microcomputer 20 A control decoder unit 60 which decodes the screen size control signal applied from the control unit and controls the horizontal and vertical window generators 70 and 71 to designate horizontal and vertical window signal start positions, and is applied from the synchronization separator. The first clock 108 of the eighth predetermined frequency and the second clock 109 of the ninth predetermined frequency are divided by the horizontal and vertical synchronization signals 105 and 104 to convert the first and second data. The first and second latch signals 110 and 111 are generated to control the output periods of the units 40 and 41, and the dual port memory 50 sequentially stores the sub picture data, and simultaneously the horizontal and vertical window signals. The read / light bar 113 row and column address 115 and the transmission control signal (120) to read and output the sub-screen data for a period corresponding to the horizontal and vertical window signals applied from the generators 70 and 71. 112) and The clock generator 80 generating the clock clock 114 and the digital Y signal output of the first output port P4 of the second data converter 41 are converted into analog Y signals to the color combining unit. Outputs the first D-A converter 90 and the digital R-Y signal output of the second output port P5 of the second data conversion section 41 into analog R-Y signals and outputs the analog R-Y signals to the color combining section. Converts the digital B-Y signal output of the second D-A converter 91 and the third output port P6 of the second digital conversion section 41 into an analog B-Y signal and outputs the analog B-Y signal to the color combining section. A 3D-A converter (92), which comprises a magnetic screen enlargement and reduction circuit. In the image processing system, a sub picture size adjustment information decoding process of inputting sub picture enlargement or reduction information to decode whether the picture is enlarged or reduced horizontally, vertically, horizontally or vertically, and corresponding to the result of decoding the sub picture resize information The subscreen display position information generation process specifying the start position of the horizontal and vertical window signals occupying an arbitrary section between the horizontal and vertical scans to the mother screen, and 1 to be compressed in the subscreen at the start of the horizontal and vertical window signals. A read clock changing process of changing a read clock according to horizontal, vertical, horizontal, vertical and enlargement and reduction in order to read data for a field from a sub picture data storage memory, and a person who reads from the memory by the changed read clock. It is characterized by the screen composition process that colorizes screen data and synthesizes color with mother screen. Now the screen to zoom in and out method.

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