KR890017954A - Subscreen Enlargement and Reduction Circuitry and Method for Television or Video Tape Recorders - Google Patents

Abstract

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Description

Subscreen Enlargement and Reduction Circuitry and Method for Television or Video Tape Recorders

Since this is an open matter, no full text was included.

1 is a circuit diagram of the present invention.

Claims (2)

An image processing system including a color difference separator, a frequency divider circuit, a synchronization separator, and a color synthesizer, comprising: a key report 10 for generating a function selection signal for a function selected by a viewer; The switching operation is performed by the microcomputer 20 for controlling the entire system by inputting the function selection signal and the switching control signal applied from the switching control signal generator to sequentially output the Y, RY and BY signals, which are color difference signals of the color difference separation circuit. The analog switch SW1 transmitted to the AD converter 30, the analog luminance signal and the color difference signal applied from the color difference separator are input through the analog switch SW1, and then the digital signal of the first predetermined bis n is input. An AD converter 30 for converting the data into the second data; a first data converter 40 for converting the output of the AD converter 30 into digital data of a second predetermined bit R and outputting the fourth predetermined period; The dual port inputs and stores the output of the first data converter 40 as the first port, reads the data amount of the seventh predetermined unit, and outputs the read data in the second predetermined bit unit through the second port. The memory 50 and the output of the second port of the dual port memory 50 are inputted to be converted into digital data of the first predetermined bit n, and then output in the fifth predetermined period or in the first to third predetermined cycles. The second data converter 41 sequentially outputs to the output port, and the horizontal window signal generator 70 which inputs a horizontal synchronization signal from the synchronization separator to generate a horizontal window signal occupying an arbitrary section between the horizontal syringes. And a vertical window signal generator 71 for inputting a vertical synchronous signal from the synchronization separator to generate a vertical window signal occupying an arbitrary section between the vertical syringes, and the microcomb 20 A control decoder 60 for controlling the horizontal and vertical window generators 70 and 71 by decoding the plane size control signal, and a clock decoder being applied from the clock divider according to the horizontal and vertical synchronization signals applied from the synchronization separator. A first clock and a second clock for controlling an output period of the first and second digital converters 40 and 41 by dividing the first clock of the eighth predetermined frequency afsc and the second clock of the ninth predetermined frequency hfsc. 7th predetermined data during a period corresponding to the horizontal and vertical window signals applied from the horizontal and vertical synchronous signal generators 70 and 71 while the latch signal and the dual port memory 50 sequentially store data. To read and output And a clock generator 80 generating row and column addressed addresses, a transmission control signal, a read clock, and the like, and a digital Y signal of the first output port of the second data converter 41. The DA converter 90 converts the output into an analog Y signal and outputs it to the color synthesizer, and converts the digital RY signal output of the second output port of the second digital converter 41 into an analog RY signal and outputs the analog RY signal to the color synthesizer. A second D-A converter 91 and a third D-A converter 92 for converting the digital BY signal output of the third output port of the second digital converter 41 into an analog BY signal and outputting the analog BY signal to the color synthesizer; A child screen enlargement and reduction circuit, characterized in that consisting of. In the image processing system, a Y, RY, BY signal, which is an analog color difference signal, is converted into a digital signal of the first predetermined bit n in the order of RY, BY, Y, and then the second predetermined bit L is converted into memory. And a data reading process of sequentially reading a seventh predetermined unit digital signal corresponding to one horizontal syringe among any number in units of one horizontal scanning period during execution of the data storing process. Converting the digital signal read out during the data reading process during the data storage process into a Y, RY, BY signal, which is a digital color difference signal of a first predetermined number of bits, for an arbitrary period corresponding to a part of the horizontal scanning period, and then analog A method of enlarging and reducing a child screen, characterized by comprising a data output process of converting and outputting a color difference signal. ※ Note: The disclosure is based on the initial application.