JP2000125284A - Monitor camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To employ a simple circuit configuration for multi-screen display of video signals from a plurality of cameras on a monitor at a low cost in the monitor camera system. SOLUTION: A selector 12 selects video signals from 4 cameras A, B, C, D based on a vertical synchronizing signal, a decoder 18 converts the video signal into a digital luminance signal and digital color difference signals, a control section 15 writes the color difference signals alternately to two FIFO (first-in first-out) memories 1, 2 connected in parallel in interlocking with the changeover of the cameras and the signals are read from the memories 1, 2 synchronously with a horizontal synchronizing signal/vertical synchronizing signal for screen display. The read data are converted into a screen display signal by an encoder 16 and the signals are displayed on multi-screen of one monitor 10. Thus, one decoder and two memories are employed for 4 sets of the cameras to attain 4-multi-screen display.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a surveillance camera system which processes video signals input from a plurality of video cameras and divides and displays them on one monitor.

[0002]

2. Description of the Related Art In a conventional surveillance camera system of this type, a video signal input from a plurality of (four) surveillance cameras is divided into four on one monitor and simultaneously displayed on each monitor. Equipped with four video signal processing units for processing video signals. Each video signal processing unit separates the video signal of each camera into a luminance signal and a color difference signal by a luminance / color difference separator, and records the output signals in a ram sequentially. In addition, there is an apparatus which reads and outputs again during a plurality of divided area scanning periods (for example, see Japanese Patent Application Laid-Open No. 4-137886). Further, the video signals of a plurality of video cameras are selectively switched, and the switched output video signals are designated and stored in a divided memory area of an image memory, and the plurality of images stored in the image memory are stored in a single memory. There is a device that outputs a frame image (for example, see Japanese Patent Application Laid-Open No. 61-179693).

[0003]

However, in the apparatus disclosed in Japanese Patent Laid-Open No. Hei 4-137886, a video signal processing unit having a luminance / color difference separator (decoder) and a ram (memory) is provided for each camera. SRAM that requires and requires high cost and requires address setting in the memory
Since the / DRAM / dual-port RAM and the like were used, the circuit was complicated. Also in the apparatus disclosed in Japanese Patent Application Laid-Open No. 61-179693, the image signal is stored in a predetermined area of the memory, and the circuit becomes complicated as described above. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and is a surveillance camera that can reduce the cost by using a simple circuit configuration to divide and display video signals from a plurality of cameras on one monitor. The purpose is to provide a system.

[0004]

In order to achieve the above object, a first aspect of the present invention is a surveillance camera system which divides a video signal input from a plurality of surveillance cameras into a plurality of screens on one monitor and displays the screen. , A selector for switching a signal from at least four cameras operating in synchronization with a synchronization signal output from the synchronization signal generator for each vertical synchronization signal, and a signal from the camera passing through the selector. And a decoder that converts a digital signal into a digital luminance signal and a color difference signal; and at least two first and second memories arranged in parallel, which alternately write the luminance signal and the color difference signal in conjunction with the switching of the camera. Writing to memory,
A memory control unit that controls reading of the written data in synchronization with a horizontal / vertical synchronization signal for screen display; and an encoder that converts data read from the memory into a monitor screen display signal. A plurality of screens are divided and displayed on one monitor screen by output.

In the above configuration, video signals input from at least four cameras are switched by a selector for each vertical synchronization signal, and signals from these cameras are converted into digital luminance signals and color difference signals by a decoder. The converted luminance signal and color difference signal are alternately written to at least two memories arranged in parallel in synchronization with the switching of the camera by the memory control unit, and the written data is stored in the horizontal / It is read out in synchronization with the vertical synchronization signal. The read data is converted into a monitor screen display signal by the encoder, and is displayed on one monitor by being divided into a plurality of screens. Thus, for four cameras, one decoder and two memories are used without requiring a decoder and a memory for each camera.
Screen division display is enabled.

The first and second memories have a FI
It is desirable that the memory be an FO (first-in first-out) memory. This eliminates the need for address specification for writing data to the memory, and simplifies the circuit configuration.

When the camera is composed of the first to fourth cameras, the luminance signal and the chrominance signal data are thinned out in each of the horizontal and vertical directions by ４ in order to form a 4-split screen. , Data is written in the first memory in the order of the first camera and the third camera, and the second memory is written in the second memory.
When data is written and read out in the order of the camera and the fourth camera, a signal for one line of the first camera is read from the first memory, and then the second signal is read from the second memory.
The signal for one line of the camera is read out, and thereafter, the signals for all lines are alternately read out from the first memory and the second memory in the same manner. The signals of all the lines of the camera are read out, and one monitor screen is divided into two in the horizontal direction and the vertical direction, and the first to fourth signals are divided.
May be displayed. With such control, signals from a plurality of cameras can be displayed on a single screen by a simple circuit.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a surveillance camera system according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block configuration of the monitoring camera system. In this surveillance camera system, video signals input from a plurality of surveillance cameras A, B, C, and D are displayed on a monitor 10 such as a CRT by dividing the screen into a plurality of screens. , B, C, and D operate in synchronization with the synchronization signal output from the synchronization signal generator 11. The 4-1 selector 12 switches signals from the cameras A, B, C, and D for each vertical synchronization signal. The digital decoder 13 converts a signal from each camera passed through the selector 12 into a digital luminance signal and a color difference signal. Two FIFO (first-in first-out) memories 1 and 2 (first and second memories) are arranged in parallel with the data, in which a luminance signal and a chrominance signal are used for camera switching. It is written alternately in conjunction with it. The control unit 15 controls the operation of the 4-1 selector 12 in synchronization with the synchronization signal from the synchronization signal generator 11, and receives a signal from the digital decoder 13 to transfer data to the FIFO memories 1 and 2. writing,
Also, after receiving a signal from the digital encoder 16 described later,
The written data is read out in synchronization with a horizontal (H) / vertical (V) synchronization signal for screen display. The digital encoder 16 converts data read from the FIFO memories 1 and 2 into a monitor screen display signal.

The digital decoder 13 includes a control unit 1
Under the control of 5, the luminance signal and the chrominance signal data are thinned out to 水平 each in the horizontal and vertical directions in order to form a four-divided screen. Further, the control unit 15 controls the data read from the FIFO memories 1 and 2 so that the screen of one monitor 10 is divided into two in the horizontal direction and the vertical direction and displayed in four parts.

Next, the operation of the surveillance camera system configured as described above will be described. 4 cameras A, B, C, D
Are appropriately installed for monitoring, and in both cases, the horizontal and vertical operations are synchronized by the synchronization signal from the synchronization signal generation unit 11. Due to the synchronous operation, when signals from different cameras are input, the digital decoder 13
The response is faster. The signals from the four cameras A, B, C, and D are switched for each vertical synchronization signal by the 4-1 selector 12, and are converted by the digital decoder 13 into digital luminance signals and color difference signals. Here, the luminance signal and the color difference signal data are thinned out in both the horizontal and vertical directions by １ ／ in order to reduce the area of the screen to ４.

The luminance signal and the color difference signal are written to two FIFO memories 1 and 2. The timing is as shown in FIG. First, the signal from camera A is FIFO
The data is written to the memory 1. Next, a signal from the camera B is written into the FIFO memory 2. Next, a signal from the camera C is written into the FIFO memory 1. Next, a signal from the camera D is written into the FIFO memory 2.

The timing for reading data from the two FIFO memories 1 and 2 is as shown in FIG. A signal for one line of the camera A is read from the FIFO memory 1 in synchronization with a horizontal / vertical synchronization signal for screen display. Subsequently, a signal for one line of the camera B is read from the FIFO memory 2. In this way, the FIFO memory 1 and the FIFO
By reading the signals from the memory 2 alternately one line at a time, all the respective lines are read. As a result, as shown in FIG. 4, one screen of each of the cameras A and B is displayed by being divided into left and right in the upper half of one screen. Subsequently, by reading in the same manner, as shown in FIG.
Camera C and Camera D are divided into two in the lower half of the screen
Is displayed for one screen.

By controlling the writing / reading of signals from a plurality of cameras to the FIFO memory 1 and the FIFO memory 2 as described above, a decoder and a memory are not required for each camera as in the related art, and the cost is reduced. In addition, a memory having a simple circuit configuration without setting an address can be used. A relatively inexpensive CRT can be used for the monitor 10.

The present invention is not limited to the configuration of the above embodiment, and various modifications are possible. For example, in the above embodiment, the case of the four-split screen display using four cameras has been described, but the same applies to the six-split screen display using six cameras or the nine-split screen display using nine cameras. Can be implemented. In the case of the nine-split screen display, only three FIFO memories are required, and only one third of the memory is required as compared with a case where a memory is provided for each camera. In the case of black and white instead of color, the digital decoder 13 and the digital encoder 16 may be A / D and D / A converters, respectively. The camera may be external, and if a digital camera is used, the decoder does not need an A / D function.

[0015]

As described above, according to the present invention, a FIFO memory is used for signal processing for displaying video signals from a plurality of cameras on a single monitor on a plurality of divided screens. In addition, there is no need for a decoder and a memory for each camera, so that the camera is inexpensive, and there is no need to set an address in the memory, so that the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a surveillance camera system according to an embodiment of the present invention.

FIG. 2 is a diagram showing the timing of writing data to FIFO memories 1 and 2;

FIG. 3 is a diagram showing timings for reading data from FIFO memories 1 and 2;

FIG. 4 is a diagram showing a display of a monitor screen in the surveillance camera system.

[Explanation of symbols]

 A, B, C, D Monitoring camera 10 Monitor 12 4-1 Selector 13 Digital decoder 15 Control unit (memory control unit) 16 Digital encoder

Claims (3)

[Claims] 1. A surveillance camera system that divides a video signal input from a plurality of surveillance cameras into a plurality of screens on one monitor and displays the screen, wherein a synchronization signal generator and a synchronization output from the synchronization signal generator are provided. A selector for switching a signal from at least four cameras operating in synchronization with a signal for each vertical synchronization signal, a decoder for converting a signal from the camera passed through the selector into a digital luminance signal and a color difference signal, At least two first and second memories arranged in parallel for alternately writing a signal and a color difference signal in conjunction with the switching of the camera; and writing the data to the memory and displaying the written data on a screen. A memory control unit that controls reading in synchronization with a horizontal / vertical synchronization signal of the memory, and converts data read from the memory into a monitor screen display signal. A surveillance camera system comprising: an encoder for converting; and a plurality of screens divided and displayed on one monitor screen by an output of the encoder. 2. The memory according to claim 1, wherein said first and second memories are FIFO.
The surveillance camera system according to claim 1, wherein the surveillance camera system is a (first-in first-out) memory. 3. When the camera comprises a first to a fourth camera, the luminance signal and the color difference signal data are thinned out in each of the horizontal and vertical directions by １ ／ in order to form a 4-split screen. The unit writes data to the first memory in the order of the first camera and the third camera, writes data to the second memory in the order of the second camera and the fourth camera, Reading a signal for one line of the first camera from the first memory, and subsequently reading a signal for one line of the second camera from the second memory;
Hereinafter, similarly, signals of all lines are alternately read from the first memory and the second memory, and then the third memory is similarly read out.
Reading out signals for all lines of the first camera and the fourth camera, and dividing one monitor screen into two in a horizontal direction and a vertical direction to display images of the first to fourth cameras. The surveillance camera system according to claim 1 or 2.