JP2001204009A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device writing two or more asynchronous image data in a common memory shared among channels, which reduces a loss time at channel changeover so as to enhance the average frame rate. SOLUTION: In the case of selecting a next channel, a channel counter 14 controls selectors 13, 16oq, 16pr so that a video decoder 3pr (3oq) other than the video decoder 3oq (3pr) selected by the selector 13 at present can be selected. Furthermore, an access control circuit 12 continuous writing pixel data of a current channel in the common memory 11 while the video decoder 3pr (3oq) selected next to take synchronization according to the instruction of a timing control section 15 and selects the channel even on the way of a frame for the image data at the current channel to start writing for a new channel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device capable of displaying video signals of a plurality of channels on one screen, and more particularly to a display device capable of reducing a loss time when switching channels.

[0002]

2. Description of the Related Art For example, when displaying a plurality of places for monitoring control, a video camera is arranged at each place, and a video signal from each video camera is switched at a predetermined time interval. A display device for displaying on a monitor screen has been widely used. In such a display device, the image output simultaneously on one screen is a signal from one video camera, and when an abnormality occurs in a certain place, even if the operator keeps watching the screen, the operator can keep watching the screen. Until switching to a different video camera, no abnormality can be found. In addition, since each video camera is switched at predetermined time intervals, the operator needs to look at the screen at least once within the time interval in order to confirm the presence or absence of an abnormality. Becomes large.

Therefore, conventionally, as shown in FIG. 13, a dedicated analog signal synthesizing device 101 is used to synthesize analog video signals from a plurality of video cameras 102. A display system 100 that simultaneously displays an image from each video camera 102 as a window on one screen of a display device 104 based on a signal is also widely used.

[0004]

However, the above-described conventional analog signal synthesizing apparatus 101 is not
Since the signals from the two are synthesized and an analog video signal is output, the number of windows and the positions of the windows that can be displayed on one screen may be limited. Further, the display device 10
Since the synthesized analog signal is input to 3, the image processing such as contour extraction and motion detection, for example, becomes difficult to perform with high accuracy for each window.

On the other hand, if a video camera outputs a digital signal using, for example, a video decoder, image processing becomes easy. However, the digital signal processing requires a video decoder for outputting a digital signal, a memory for storing the digital signal, and a circuit for controlling the input and output of the memory, and these members are provided for each channel. Therefore, a large number of chips are required, and particularly when the number of channels is large, the manufacturing cost of the entire display system rises.

Here, if a selector 201 is provided after the video camera 102 as in the display system shown in FIG. 14, the number of video decoders 202 and the number of memories and memory control circuits in the display device 203 can be reduced. It is possible to reduce the production cost.

However, in general, each video camera 102
Are asynchronous with each other, so the video decoder 202
When the video camera 102 is switched, it is necessary to synchronize a newly input analog signal, and a normal video signal cannot be output during the synchronization acquisition period. Therefore, it is necessary to prohibit writing to the memory in the display device 203 during this period. Thus, in the display system 200, every time the channel is switched, a loss time that cannot be written to the memory occurs, and the average frame rate when writing to the memory is reduced.

In order to solve the above problem, the present applicant has disclosed in Japanese Patent Application Laid-Open No. H11-32326, a plurality of video decoders 202a and 202b and one of them as in a display system 200a shown in FIG. And a selector 204 for selecting one of the video decoders 202a.
While (202b) is writing one frame of image data to the display device 203, the other video decoder 2
02b (202a) proposed a configuration for synchronizing the next selected channel. However, even with this configuration, the loss time due to channel switching is
Still exists.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a display device for writing two or more asynchronous image data into a shared memory shared by each channel. An object of the present invention is to improve the average frame rate by reducing the switching loss time.

[0010]

According to a first aspect of the present invention, there is provided a display apparatus for displaying a plurality of video signals on a plurality of channels as windows on a single screen. In the display device capable of instructing the display device, the following means are taken.

That is, each of the video signals is transmitted together with a respective synchronizing signal indicating a frame segment of the video, and is provided in common for each of the channels. A shared memory for storing, a main selector for sequentially selecting the video signal of each channel, a first detecting means for detecting a frame break of the current channel based on a synchronization signal of a currently selected channel, A second detecting means for detecting a frame break of the next channel based on a valid synchronization signal of the selected channel; and one of the current channel and the next channel in the middle of the frame based on an instruction from the two detecting means. Even if there is an instruction to switch the main selector, the image data of the selected channel is updated in accordance with the frame. And a control means for writing into the shared memory.

In the above configuration, while a certain channel is selected by the main selector, the control means writes the data of the channel to the shared memory corresponding to the frame based on the instruction of the first detection means. Also,
The second detecting means detects a frame break of the next channel based on a valid synchronization signal of the next selected channel. On the other hand, the control means controls the correspondence between the image data and the frame of the current channel and the switching timing of the main selector based on the outputs of the two detection means.

According to this configuration, the control means refers to the outputs of the two detection means, so that the main selector can be switched in the middle of the frame without impairing the correspondence between the selected channel and the frame. . As a result, even when the frames of the video signal of each channel are not synchronized with each other, they can be written to the shared memory almost continuously, and the loss time at the time of channel switching can be reduced. As a result, even though the shared memory is shared between the channels, the average frame rate is improved compared to a configuration in which writing to the shared memory is stopped after the end of the frame of the current channel until the start of the frame of the next channel. it can.

If the main selector can be switched in the middle of the frame of the current or next channel, the switching timing of the main selector may be determined based on the next channel, for example, at the start of the frame of the next channel. And the end of the current channel frame,
The determination may be made based on the current channel. However, if the determination is made based on the current channel, the frame position of the data of the next channel changes at the time of switching according to the difference in the phase of the synchronization signal between the video signals. A circuit for monitoring and identifying the position in the frame at which the data at the time of switching indicates (identification circuit for the next channel)
Is required separately from the identification circuit for the current channel.

On the other hand, a display device according to a second aspect of the present invention is the display device according to the first aspect of the present invention.
The detecting means detects the start of the frame of the next channel, and the control means instructs switching of the main selector when the second detecting means detects the start of the frame, so that the common mode is switched from the beginning of the frame. It is characterized by writing data to a memory.

According to this configuration, since the main selector is switched at the time of starting the frame of the next channel, the data at the time of switching is the first of the frame. Therefore, the identification circuit for the next channel becomes unnecessary, and the circuit configuration can be simplified.

Further, the display device according to the invention of claim 3 is:
In the configuration of the invention according to claim 1 or 2,
Converting an analog input signal representing an image, generating the video signal, and selecting one of a plurality of video decoders for outputting to the main selector and one of the analog input signals corresponding to the plurality of channels; A sub selector for inputting to the video decoder, wherein the control means outputs the next selected channel from a video decoder different from the video decoder for outputting the video signal of the current channel, and terminates the selection. The analog input signal to the video decoder that output the video signal of the
The main decoder and the sub selector are instructed to be switched so that the video decoder can be switched to the analog input signal of the channel to be output next.
The detection means determines that the synchronization signal output by the video decoder is invalid until the video decoder corresponding to the next channel acquires the synchronization of the analog input signal.

According to this configuration, since the sub selector is provided at the preceding stage of the video decoder, the number of video decoders of the entire display device is reduced as compared with the case where a video decoder is provided for each channel (analog input signal). it can.
Further, since the main and sub selectors are switched as described above, even while one video decoder is acquiring synchronization of the analog input signal, the video signal of the current channel can be output by another video decoder, Loss time at the time of channel switching due to synchronization acquisition can be reduced. As a result, even when the number of channels is large, the average frame rate can be improved without increasing the manufacturing cost.

If all the channels can be selected by switching the main and sub selectors, each of the sub selectors may select, for example, from all the analog input signals, or select all the analog input signals in advance. It may be divided into a plurality of groups and selected from the groups. However, when the sub-selector is divided into a plurality of groups, each sub-selector only needs to receive the analog input signal of the group corresponding to itself, so that the transmission path of the analog input signal can be shortened.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
This will be described below with reference to FIG.
That is, the display system 1 according to the present embodiment is suitably used, for example, as a monitoring control device. As shown in FIG. 1, the details of connection with a plurality of video cameras 2 will be described later. As described above, one of the plurality of video cameras 2 is selected, and a video decoder 3 that captures the camera output, and a display device 4 that displays an image captured by each video camera 2 as a separate window on a screen. And the video signal VID from each video decoder 3
Display device 5 for controlling display device 4 based on EO
And In the following, a flow of a series of data generated from each video camera 2 is referred to as a channel. When members corresponding to each channel are distinguished, for example, a lowercase letter indicating a channel is used as in the video camera 2o. It is referred to. In particular, when no distinction is made or when they are collectively referred to, they are referred to without a lowercase letter like the video camera 2.

The combination of the video camera 2 and the video decoder 3 is, as described later,
Any combination may be used as long as a data sequence indicating an image captured by the video camera 2 can be output together with a synchronization signal. In the present embodiment, as an example, the video camera 2 outputs an NTSC signal and the video decoder 3 ,
The NTSC signal is decoded and one frame is
A case will be described in which an image of 0 lines × 640 dots in the horizontal direction is transmitted by dividing each frame into two fields by interlaced scanning.

More specifically, the video signal VIDEO includes:
An image signal DAT composed of pixel data D of each pixel arranged side by side and a control signal CTL for transmitting the image signal DAT correctly, such as a signal for synchronization, are included. As shown in FIG. 2, each of the pixel data D
Is that data for one line is transmitted in a predetermined order in synchronization with the clock signal DOTCLK, and for each line,
The horizontal synchronization signal HSYNC * is output as a pulse. Here, the clock signal DOTCLK is a clock signal having a predetermined period, and is provided between the horizontal synchronization signals HSYNC *.
Since there is a period during which the pixel data D is transmitted and a period during which the pixel data D is not transmitted, the control signal CTL is a signal VARID that goes high only during a period in which valid data exists.
Is transmitted.

As shown in FIG. 3, assuming that the first line is one line, the odd lines are transmitted as one field in a predetermined order, and the even lines are transmitted as the next field. Transmitted. further,
As the control signal CTL, a vertical synchronizing signal VSYNC *, which is output as a pulse for each field, and a signal ODDFRM which is set to a high level during transmission of an odd line are transmitted.
In this specification, for convenience of explanation, a signal name is added to the end of the signal name.
An asterisk (*) is used to distinguish negative logic signals.

On the other hand, the display device 5 according to this embodiment includes:
As shown in FIG. 1, a shared memory 11 is provided in common for each channel.
And a selector (main selector) 13 for selecting one of the video signals VIDEO of each channel and outputting it to the access control circuit 12
A channel counter 14 for designating a channel to be selected by the selector 13; and a timing control unit 15 for controlling switching timing of each channel. Each of the members 12, 14, and 15 corresponds to the control means described in the claims.

In this configuration, even though the shared memory 11 and the access control circuit 12 are shared by each channel, when the selector 13 sequentially selects a channel in accordance with the instructions of the timing control unit 15 and the channel counter 14, the access The control circuit 12 stores data indicating the image of the selected channel in the shared memory 11.
The access control circuit 12 reads out image data of each channel from the shared memory 11 and outputs the image data to the display device 4 so that the display device 4 can display an image of each channel in a window. Thereby, the shared memory 11
In spite of the simple configuration of one access control circuit 12, the image of a plurality of channels can be displayed in a window on one screen of the display device 4.

In the present embodiment, for example, the data bus width of the shared memory 11 is set to 16 bits, like the bit width of the pixel data D.
For example, it is set as shown in FIG. That is,
The least significant bits A0 to A9 of the address correspond to the horizontal position (X coordinate) in one frame of the image, and bit A1
0 to A18 correspond to the vertical position (Y coordinate) of the image. Further, bits A19 and A20 correspond to each channel, channel o corresponds to "00",
Channels p, q, and r are "01", "10", "1".
1 ". Needless to say, the data bus width and the address map of the shared memory 11 are not limited to this, and the same effect can be obtained if image data of each channel can be stored.

Further, the channel counter 14 according to this embodiment counts a switching signal SW described later.
Is a binary counter for each channel,
The count values “00” to “11” corresponding to r can be output as channel numbers. The selector 13 is a multiplexer, and outputs the video signal VIDE of each channel.
Out of O, the video signal VIDEO of the channel indicated by the channel number can be output.

On the other hand, as shown in FIG. 5, the access control circuit 12 includes a write address generation unit 21 for generating an address for writing the pixel data D into the shared memory 11,
A read address generation unit 22 that generates an address for reading pixel data D from the shared memory 11 for screen display, and a multiplexer 2 that switches between the two addresses according to an instruction from the arbitration circuit 23 and provides the address to the shared memory 11
4 and a buffer unit 25 for temporarily storing pixel data D during writing.

The write address generator 21 has a 10-bit binary counter 21a for outputting the bits A0 to A9 of the address, and a signal O as a bit A10.
An inverter 21b that outputs an inverted signal of DDFRM;
8-bit binary signal that outputs bits A11 to A18
A counter 21c is provided. The binary counter 21a is reset by the pulse input of the horizontal synchronization signal HSYNC, and the buffer unit 25
Is counted each time data is written to The binary counter 21c is reset by the vertical synchronization signal VSYNC and counts the horizontal synchronization signal HSYNC. The channel numbers output by the channel counter 14 shown in FIG. 1 are used as the bits A19 and A20.

The read address generator 22 outputs the output signal VSYNC of the display controller 22a.
Based on ** HSYNC ** DOTCLK * VARID, bits A0-A9 and bits A10-A10 of the address
Binary counter 22b that outputs A18
22c, and a number output circuit 22d for outputting a channel number corresponding to a window to be displayed.
Each of the above signals VSYNC *, HSYNC *, DOTCLK
VARID is the control signal CTL of the video signal VIDEO
However, the cycle of the clock signal DOTCLK is set to a shorter cycle in accordance with the display device 4 that performs sequential scanning (non-interlace), and the vertical synchronization signal VSYNC * is provided between each frame. Is output.
The binary counter 22b is reset by the horizontal synchronizing signal HSYNC *, and the clock signal DOTCL is reset.
Count K. Also, the binary counter 22c
Are reset by a vertical synchronization signal VSYNC *, and an inverted signal of the signal VARID is input as a clock signal.

On the other hand, the arbitration circuit 23 includes a binary counter 23a for counting a clock signal DISP_CLK of a predetermined cycle, and a NAND circuit 23b to which both output bits Q1 and Q2 of the binary counter 23a are input. , The arbitration signal S having a ratio of the low level period to the high level period of 1: 3 can be output. The multiplexer 24 outputs the address signal from the write address generator 21 to the shared memory 11 while the arbitration signal S is low, and outputs the address signal from the read address generator 22 during the high level. This allows
For display (data reading) that is sequentially scanned, more bandwidth can be secured among the bandwidths for accessing the shared memory 11.

The buffer unit 25 has a FIFO (Fi
(rst in first out) memory 25a is provided. The output of the FIFO memory 25a is connected to the data bus of the shared memory 11 via a three-state buffer 25b that keeps the output at high impedance when the arbitration signal S is high. Also, as the read signal RD,
The write signal WE * of the shared memory 11 is
It is input after being inverted by c. The write signal WE * of the shared memory 11 is a negative logic input / output AND circuit 25d.
Accordingly, only when the FIFO memory 25a is not empty and the arbitration signal S permits writing,
Becomes active (low level). Note that the write signal W
E * is also input to the binary counter 21a of the write address generation unit 21 as a clock signal.

Further, the output of a three-input AND circuit 25e is applied to the FIFO memory 25a as a write signal WR. The three-input AND circuit 25e outputs the clock signal DOTCLK during a period in which the signal VARID and an effective signal ENB described later are both at a high level (true). The output to the FIFO memory 25a is stopped while keeping the output at the low level. Further, the switching signal SW is input to the FIFO memory 25a as the reset signal MR,
The buffer is cleared when switching channels.

Thus, the access control circuit 12 allows the video signal VIDEO of the channel selected by the selector 13 shown in FIG.
In the memory area of the shared memory 11 corresponding to the channel.

Here, the display system 1 according to the present embodiment
In order to reduce the number of video decoders 3 and the number of signal lines from each video decoder 3 to the display device 5, a video decoder 3 is provided for each of the plurality of video cameras 2. Also, a selector (sub selector) 16 is provided. FIG. 1 shows, as an example, a case where two video cameras 2 are provided in two video decoders 3, respectively, and video cameras 2o and 2
q is connected to the video decoder 3oq via the selector 16oq. Similarly, the video cameras 2p and 2r
It is connected to the video decoder 3pr via the selector 16pr. Each of the selectors 16 oq and 16 pr and the selector 13 determine
Select one of the inputs (analog input signal). As a result, the display device 5 has two video decoders 3oq and 3p.
With r, images from the four-channel video cameras 2o to 2r can be displayed in a window.

Here, the video cameras 2o to 2r do not have a configuration for synchronizing their output signals, and their output signals are asynchronous. Therefore, each video decoder 3oq (3pr) selects the selector 16oq (16p
When the input is switched according to r), it takes a certain amount of time to start capturing in synchronization with a new input signal. For example, as shown in this embodiment,
When capturing an NTSC signal, the time required for synchronous capture reaches several hundred [ms].

Therefore, in this embodiment, the switching order of the channels o to r is set such that the next channel is captured by a video decoder 3 different from the video decoder 3 of the current channel. Also,
The switching order is set so as to instruct selection of a different channel of the same video decoder 3 after selecting all the other video decoders 3.

Specifically, for example, as shown in FIG.
The channel counter 14 includes a 2-bit binary counter 14a that counts the pulses of the channel switching signal SW, and a 2-bit D flip that delays the output of the binary counter 14a until receiving the next pulse of the switching signal SW. -It has a flop 14b. The output of the D flip-flop 14b indicates the currently selected channel number C, and the lower bit C0 is applied to the selector 13 implemented as a two-input multiplexer. On the other hand, the binary counter 14
The output value of a indicates the channel number N to be selected next.

Further, based on the current and next channel numbers, the control signals Xoq for the selectors 16oq and 16pr are controlled.
Multiplexer 14oq to generate Xpr
14pr is provided. The multiplexer 14o
q indicates that the lower bit C0 of the current channel number C is "
In the case of "1", the upper bit N1 of the next channel number N is output, and in the case of "0", the upper bit C1 of the current channel number C is output.
Indicates that the lower bit C0 of the current channel number C is "1"
In the case of, the upper bit C1 of the channel number C is output, and in the case of "0", the upper bit N1 of the next channel number N is output.

Thus, the selector 16oq (16p
r), the output of the corresponding video decoder 3op (3pr) is selected by the selector 13 based on the control signals Xoq and Xpr.
Is switched when it is no longer selected. As a result, as compared with the case where switching is performed in another order, the period α from the end of channel selection to the next selection of another channel of the same video decoder can be secured longer. 3op · 3qr can be synchronously captured with a relatively long time margin.

By the way, during the period β during which synchronization is acquired,
The video decoder 3oq · 3pr outputs the normal video signal VI
Since the DEO cannot be output, the display device 5 needs to control so that the video signal VIDEO during this time is not written to the shared memory 11.

In the following, before describing the configuration of the present embodiment, as a comparative example, a configuration in which writing to the shared memory 11 is prohibited after the writing of the previous channel is completed until the next channel can be written. I do. That is, in the display system 51 according to the comparative example,
A timing control unit 55 shown in FIG. 7 is used as the timing control unit 15 shown in FIG. As an example, the timing control unit 55 shows a configuration in which each channel is switched for each frame, a frame start detection circuit 61 and a frame end detection circuit 62 for detecting the start and end of a frame, and each video decoder 3oq.
A selector 63 that outputs the next selected one of the 3pr control signals CTLoq and CTLpr to the frame start detection circuit 61, and a control signal CT of the currently selected one
L for outputting L to the frame end detection circuit 62
And an effective signal ENB to generate an image signal DAT currently input to the access control circuit 12 shown in FIG.
And a JK flip-flop 65 for instructing the validity / invalidity of the data. Each of the selectors 63 and 64 only needs to be able to output, of the control signal CTL, only a signal required by the subsequent circuits 61 and 62.

The output BGFRM of the frame start detection circuit 61 is input to the J input of the JK flip-flop 65 via a two-input AND circuit 66, and the output of the frame end detection circuit 62 is input as the K input. ENDFR
M has been entered. The J input is a switching signal S
W is output to the channel counter 14 and the like.

On the other hand, in order to generate the other input (NXTASC) of the AND circuit 66 in accordance with the synchronization acquisition time β, the control signals C of the video decoders 3oq and 3pr are generated.
A selector 71 that outputs the next selected one of TLoq · CTLpr; a channel stable circuit 72 that outputs a signal STB indicating that a synchronization acquisition period is in progress based on a control signal CTL output by the selector 71; Signal ST
B which receives B as a J input and outputs the signal NXTASC
A K flip-flop 73, a D flip-flop 74 for delaying the output of the JK flip-flop 73,
An AND circuit 75 for calculating the logical product of the output signal NXTASC of the JK flip-flop 73 and the inverted output Q of the D flip-flop 74 is provided.

The flip-flops 73 and 74 are supplied with a system clock as a clock signal, and the output of the AND circuit 75 is applied to the RS input of the channel stable circuit 72. Further, as the K input of the JK flip-flop 73, the signal ENDDFRM is applied from the frame end detection circuit 62 described above.

In this configuration, as shown in FIG.
When S is input, the channel stable circuit 72
Until the next video decoder 3 acquires synchronization (t1
During the period from t4 to t4), the signal STB is kept at the low level.

The channel stable circuit 72 is
For example, as shown in FIG. 9, a 2-bit binary counter 81 that counts the vertical synchronization signal VSYNC and an upper bit output Q1 of the binary counter 81 are input as a clock signal, and the D input is maintained at a high level. A flip-flop 82, a pulse output circuit 83 that is realized by, for example, a delay timer or a one-shot, outputs a negative logic pulse signal for a predetermined period after the signal RS rises, and an output RSS of the pulse output circuit 81 *
And a NOR circuit 84 which outputs a NOT of a logical sum of the signal RS and the signal RS to the binary counter 81 and the D flip-flop 82 as a negative logic reset signal.

As a result, as shown in FIG.
At 1, the signal RSS * goes low for a predetermined period (period from t1 to t3) after the signal RS rises, and is selected next time, for example, immediately after the selectors 16oq and 16pr shown in FIG. 1 are switched. During a period in which the video decoder 3 cannot stably output even the vertical synchronization signal VSYNC (a period until t2), the binary counter 81
And the D flip flop 82 can continue to be reset. When the period ends, the reset is released, and the binary counter 81 outputs the vertical synchronization signal VSYN.
Start counting C. After the time point t3, the vertical synchronization signal V
When SYNC is applied a predetermined number of times (two times in the configuration of FIG. 9) and it is determined that the video decoder 3 selected next has acquired synchronization, the upper bit output Q1 of the binary counter 81 is set to "1". And the signal STB goes high (at time t4).

Further, when the signal STB goes high, as shown in FIG. 8, the output signal NXTASC of the JK flip-flop 7 shown in FIG. 7 rises in synchronization with the system clock (at time t5). As a result, the output BGFRM of the frame start detection circuit 61 is applied to the JK flip-flop 65, and changes the valid signal ENB to a high level. The output BGFRM is applied to the channel counter 14 shown in FIG. 6 as a channel switching signal SW, and when the count value C becomes a value indicating the next channel, the selector 13 causes the selector 13 to output the video signal VIDEO ( DAT11 VSY
NC11). Further, the JK flip-flop 65 keeps the valid signal ENB at the high level until the frame writing in the newly selected channel is completed and the signal ENDDFRM is applied (until time t6). As a result, the pixel data D of the newly selected channel is sequentially written into the shared memory 11 shown in FIG. The selector 63 shown in FIG.
64, 71 etc. can also be switched.

At time t6, when the writing period (for one frame) of the newly selected channel ends and the signal ENDDFRM is applied, the JK flip-flop 73 is reset and the frame start detection circuit 61 output signal BGFRM is JK flip-flop 6
5 is no longer applied. As a result, the valid signal ENB becomes
Until the next channel is synchronized, the low level is maintained, and the display system 51 according to this comparative example can prevent incorrect writing of pixel data D into the shared memory 11.

At the time point t5, the signal NXTAS is output.
When C rises, the output signal RS of the AND circuit 75 goes high. As a result, the signal STB changes to low level again for the next channel switching,
The operation after time point t1 described above is repeated.

However, as in the above comparative example, the writing to the shared memory 11 is prohibited from the completion of the writing of the pixel data D of a certain channel to the synchronization of the next selected video decoder 3. If the writing of incorrect pixel data D is prevented, the time during which data can be written to the shared memory 11 is shortened by the prohibited period (loss time), and frames are easily dropped.

When the number of video decoders 3 is large, the loss time can be reduced to some frames, for example, to several frames by the above-described switching order. However, when the number of video decoders 3 decreases, for example, In the case where the number of video decoders 3 is two, the number of video decoders reaches about 15 frames, and a moving image cannot be displayed.

In addition, since the video signal VIDEO output from each video decoder 3 is usually asynchronous, the start and end points of the frame are different from each other. Therefore, even when the number of video decoders 3 is set to be sufficiently large, the configuration of the comparative example eliminates the loss time from the end of the frame of the previous channel to the start of the frame of the next channel. Can not do it.

On the other hand, in the display system 1 according to this embodiment, until the next channel is synchronized,
After the previous channel is written to the shared memory 11 and synchronization is established, the loss time is reduced by switching the channel even in the middle of the frame.

More specifically, as shown in FIG. 11, the timing control unit 15 according to the present embodiment includes the same members 31 to 35 as the members 61 to 65 and 71 to 75 of the timing control unit 55 shown in FIG.・ Equipped with 41 to 45. However, in the timing control unit 15 according to the present embodiment, the selector 3
3, the signal C0 indicating the current channel number is applied, the AND circuit 66 shown in FIG. 7 is omitted, and the output signal BGFRM of the frame start detection circuit 31 is omitted.
Is directly applied as the J input of the JK flip-flop 35. Further, a signal RS is used as the switching signal SW, and the JK flip-flop 35 is used.
, The signal RS is input via the inverter 36 as a negative logic reset signal. Note that the frame start detection circuit 31 is, for example, the channel counter 14
A pulse of the signal BGFRM is output at the start of a frame immediately after the rising of the signal STB by setting the delay time of the selector 63 or the like to a predetermined value or less, or by referring to the signal STB. . Further, the channel stable circuit 42 corresponds to the first detecting means described in the claims, and both the detecting circuits 31 and 32 correspond to the second detecting means.

According to this configuration, as shown in FIG.
When the signal RS is output along with the switching of the channel, the channel stable circuit 42 outputs the signal until the newly selected video decoder 3 can stably output the video signal VIDEO as in FIG. The STB is maintained at a low level (a period from t1 to t4).

At time t4, when the signal STB changes to the high level, the JK flip-flop 43 changes the output signal NXTASC to the high level in synchronization with the system clock. As a result, the signal RS as the switching signal SW changes to the high level, and notifies the channel counter 14 and the channel stable circuit 42 of the switching of the channel.

However, in this embodiment, the JK flip
The signal B for the channel currently selected by the flop 35
It is set to be set by GFRM and reset by signal ENDRM. Further, both signals BGFR
It is reset by the switching signal SW (signal RS) regardless of M.ENDDFRM.

Therefore, unlike FIG. 8, even if a new channel is selected and writing of one frame of the channel is completed at time t11, writing of the next frame of the channel is completed at time t12. When started, the valid signal ENB becomes active again. As a result, the pixel data D of the channel is repeatedly written in the shared memory 11.

The writing of the current channel is continued until the video decoder 3 selected next takes synchronization.
At time 5, when the signal RS is output, even if the current channel is in the middle of the frame, the signal RS is output.
Is immediately transmitted to the access control circuit 12 and the channel counter 14 as the switching signal SW. Further, when a new channel is selected and the signal BGFRM indicating the start of the frame is output from the frame start detection circuit 31 at the time t14, the JK flip-flop 35 in FIG. 1 is set, and the valid signal ENB is activated ( (High level).

As described above, the access control circuit 12 according to the present embodiment, based on the instruction of the timing control unit 15,
The writing of the current channel is continued until the video decoder 3 selected next takes synchronization. As a result,
Since no loss time occurs due to the synchronization acquisition period β, frame drop can be prevented.

Since the video signals VIDEO are asynchronous with each other, the frame of the next channel generally starts writing the frame in the current channel, but the access control circuit 12 according to the present embodiment is Based on an instruction from the control unit 15, writing is performed up to the middle of the frame of the current channel, and the channel is switched at the start of the frame of the next channel. As a result, the loss time at the time of channel switching can be reduced and the average frame rate can be improved as compared with the configuration in which writing is prohibited until the frame of the current channel ends and the frame of the next channel starts.

The access control circuit 12, for example,
A period during which the image signal DAT does not indicate an image, such as a period between frames of the video signal VIDEO of the current channel (a period from t11 to t12), and a period from the output of the switching signal SW to the start of the frame ( t13
During a period necessary for channel switching, such as a period from t14 to t14), writing to the shared memory 11 is prohibited. As a result, even when switching is performed in the middle of a frame, the shared memory 11 can be protected from writing indefinite data.

In the present embodiment, the case of switching at the start of the frame of the next channel has been described as an example of a switching method in the middle of a frame, but the switching method is not limited to this. For example, a new channel may be written from the middle of a frame by continuing writing the current channel even after synchronization of the next channel is established and switching to the next channel at the end of the frame of the current channel.

In this case, since less than one frame becomes the next channel, that frame is immediately overwritten by a complete frame that is subsequently captured, and the display period of the incomplete frame can be shortened. However, in this configuration, a new channel is written in the middle of the frame. For example, the next channel is monitored by, for example, providing the binary counters 21a and 21c for the next channel as shown in FIG. A circuit for determining the write start position of the frame in the next channel is required. Therefore, when a reduction in circuit size is required, it is desirable to switch at the start of the frame of the next channel as in the present embodiment.

In the present embodiment, the video camera 2 outputs a composite signal or an analog signal such as an S terminal signal as in a home video tape recorder, and the video decoder 3 converts the analog signal. Although the case of converting into a digital signal has been described, the present invention is not limited to this. The video decoder 3 outputs the horizontal synchronization signal HS
It suffices if a series of digital data indicating each pixel, such as R, G, B signals, Y, U, V signals, can be output in synchronization with synchronization signals such as YNC and vertical synchronization signal VSYNC. In any case, if a plurality of video decoders 3 that output mutually asynchronous video signals VIDEO are provided, the same effects as those of the present embodiment can be obtained.

[0068]

As described above, the display device according to the first aspect of the present invention is provided with a shared memory provided common to the channels and storing data indicating the video signal of each channel, and the video of each channel. A main selector for sequentially selecting a signal, first and second detecting means for detecting a frame break of the current and next channels, and one of the current channel and the next channel being in the middle of a frame based on an instruction from the two detecting means. Even in this case, control means for instructing switching of the main selector and writing image data of the selected channel to the shared memory in correspondence with a frame is provided.

According to this configuration, the control means can switch the main selector in the middle of the frame without losing the correspondence between the selected channel and the frame by referring to the outputs of the two detection means. . As a result, even when the frames of the video signal of each channel are not synchronized with each other, they can be written to the shared memory almost continuously, and the loss time at the time of channel switching can be reduced. As a result, even though the shared memory is shared between the channels, the average frame rate is improved compared to a configuration in which writing to the shared memory is stopped after the end of the frame of the current channel until the start of the frame of the next channel. It has the effect of being able to.

As described above, the display device according to the second aspect of the present invention has the configuration of the first aspect of the present invention,
The detecting means detects the start of the frame of the next channel, and the control means instructs switching of the main selector when the second detecting means detects the start of the frame, so that the common mode is switched from the beginning of the frame. This is a configuration for writing data to a memory.

According to this configuration, the main selector is switched at the time of starting the frame of the next channel, so that the data at the time of switching is the beginning of the frame. Therefore, unlike a configuration in which the main selector is switched based on the frame of the current channel, a circuit for monitoring the next channel and associating the frame with the data becomes unnecessary, and the circuit configuration can be simplified.

According to the third aspect of the present invention, as described above, the display device according to the first or second aspect has the following configuration.
Further, a plurality of video decoders for converting an analog input signal and outputting a video signal to the main selector, and one of the analog input signals corresponding to the plurality of channels.
And a sub selector for inputting the selected signal to the video decoder, wherein the control means outputs the next selected channel from a video decoder different from the video decoder for outputting the video signal of the current channel. ,And,
The switching between the main selector and the sub selector is performed so that the analog input signal to the video decoder that has output the video signal of the channel whose selection has been completed is switched to the analog input signal of the channel that the video decoder outputs next. In addition to the instruction, the second detecting means determines that the synchronization signal output by the video decoder is invalid until the video decoder corresponding to the next channel acquires the synchronization of the analog input signal.

According to this configuration, since the sub-selector is provided before the video decoder, the number of video decoders in the entire display device can be reduced. Further, since the main and sub selectors are switched as described above, even while one video decoder is acquiring synchronization of the analog input signal, the video signal of the current channel can be output by another video decoder, Loss time at the time of channel switching due to synchronization acquisition can be reduced. As a result, even if the number of channels is large, there is an effect that the average frame rate can be improved without increasing the manufacturing cost.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a main configuration of a display system.

FIG. 2 is a timing chart showing a video signal output by a video decoder of the display system and showing a video signal for one line.

FIG. 3 is a timing chart showing the video signal and showing a video signal for a half frame.

FIG. 4 is an explanatory diagram showing an address map of a shared memory of each channel in the display system.

FIG. 5 is a circuit diagram showing a main configuration of an access control circuit of the shared memory in the display system.

FIG. 6 is a circuit diagram showing a configuration example of a channel counter for switching each channel in the display system.

FIG. 7 illustrates a comparative example of the present embodiment, and is a circuit diagram illustrating a main configuration of a timing control unit that controls switching timing of each channel in a display system.

FIG. 8 is a timing chart showing an operation of the display system according to the comparative example.

FIG. 9 is a circuit diagram showing a configuration example of a channel stable circuit provided in the timing control unit.

FIG. 10 is a timing chart showing the operation of the channel stable circuit.

FIG. 11 is a circuit diagram illustrating a main configuration of a timing control unit according to the embodiment.

FIG. 12 is a timing chart showing the operation of the display system according to the embodiment.

FIG. 13 is a block diagram showing a conventional technique and showing a main configuration of a display system having an analog signal synthesizing device.

FIG. 14 is a block diagram showing another related art and showing a main configuration of a display system having a single video decoder.

FIG. 15 is a block diagram showing still another conventional technique, showing a main configuration of a display system having a selector before and after a video decoder.

[Explanation of symbols]

 3oq · 3pr Video decoder 4 Display device 5 Display device 11 Shared memory 12 Access control circuit (control means) 13 Selector (main selector) 14 Channel counter (control means) 15 Timing control section (control means) 31 Frame start detection circuit (first 1 detecting means) 32 end-of-frame detecting circuit (first detecting means) 42 channel stable circuit (second detecting means) 16oq / 16pr selector (sub selector) VIDEOoq / VIDEOpr video signal

Claims (3)

[Claims] 1. A display device capable of instructing a display device to display a plurality of video signals on a single screen as a plurality of video signals corresponding to respective windows as windows, wherein each of the video signals is a frame segment of the video. And a shared memory that is provided in common with each of the channels and stores data indicating the video signal of each channel, and a main memory that sequentially selects the video signal of each channel. A selector, first detection means for detecting a frame break of the current channel based on a synchronization signal of a currently selected channel, and
Second detecting means for detecting a frame break of the next channel; and instructing switching of the main selector based on the instructions of the two detecting means even if one of the current channel and the next channel is in the middle of a frame. And a control unit for writing data of the selected channel to the shared memory in correspondence with a frame. 2. The second detecting means detects a frame start of a next channel, and the control means instructs switching of the main selector when the second detecting means detects a frame start. 2. The display device according to claim 1, wherein data is written to the shared memory from the beginning of the frame. 3. A plurality of video decoders for converting an analog input signal representing an image to generate the video signal and outputting the video signal to the main selector, and among the analog input signals corresponding to the plurality of channels, And a sub selector for selecting one of the video signals and inputting the video signal to the video decoder. The control means outputs the video signal of the current channel from a video decoder different from the video decoder that outputs the video signal of the current channel. The main selector and the sub selector are set so that the analog input signal to the video decoder that has output the video signal of the channel whose selection has been completed and has been output is switched to the analog input signal of the channel that the video decoder outputs next. In addition to instructing the switching of the selector, the second detecting means outputs the video deco Da is time to capture synchronization of the analog input signal, the display device according to claim 1 or 2, wherein the determining and disable synchronization signal to which the video decoder outputs.