JPH0990920A - Video signal conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of line memories required for conversion and to reduce a circuit scale of a video signal conversion device. SOLUTION: A write enable pulse LWE and a write address reset pulse LWRST being timing pulses starting a write means of a line memory 5 are delayed by a delay time d2 by a delay element 24, and phase differences are caused between the LWE and LWRST and a read enable pulse LRE and a read address reset pulse LRRST being the timing pulse starting the read means. The phase differences are the sizes so that a horizontal blanking period of an input video signal 2 contains the horizontal blanking period of an output video signal 25. Thus, even when one of the line memory 5 performs conversion, the matter that read operation outstrips write operation within a horizontal scan period displayed on an image is eliminated, and the problem of the deterioration in the image according to reduction in the line memories is dissolved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal conversion device for converting a video signal of a personal computer or the like and a television video signal of different systems, and more particularly to a clock of a predetermined frequency using a line memory. The present invention relates to conversion of a video signal synchronized with a clock signal into a video signal synchronized with a clock having a frequency twice that of the clock.

[0002]

2. Description of the Related Art In the recent multimedia era, a display device for displaying an NTSC signal (2: 1 interlaced scan) which is a normal television video signal is used for a video signal from a personal computer or the like having a different video system. It has become required to display. Also,
The demand for higher image quality has also increased for televisions, and television receivers that display images by the progressive scanning method have been realized.

Therefore, conventionally, a line memory has been used, and an NTSC signal or the like (hereinafter referred to as a single-density video signal) which is a 2: 1 interlaced scan is written in the line memory, which is read twice at a double speed and a progressive scan video signal. (Hereinafter, referred to as a double-density video signal), and conversely, a double-density video signal is converted into a single-density video signal.

FIG. 7 is a block diagram of a conventional single-density / double-density video signal conversion processing circuit. Video signal converter 1
The input video signal 122 to 21 is either a single density video signal (here, NTSC system video signal) or a double density video signal (here, VGA standard video signal). The input selector switch 123 switches the route according to the type of the input video signal 122. When the input video signal 122 is a single density video signal, the video signal conversion device 1 is provided on one path.
21 is supplied to the external monitor output single-density video signal processing circuit 124, and is converted into a double-density video signal by using the line memories 125 and 126 in the other path, and is displayed on the display. Processing circuit 12
7 is supplied. On the other hand, when the input video signal 122 is a double-density video signal, it is passed through the video signal conversion device 121 through one path and supplied to the display double-density video signal processing circuit 127, and through the other path. ,
A single-density video signal is converted by using the line memory 128, and the single-density video signal processing circuit 124 for external monitor output is used.
Is supplied to.

A conversion process from a single density to a double density video signal using the line memories 125 and 126 will be described. FIG. 8 shows line memories 125 and 126 (memory A and memory A, respectively).
Let B. 3) is a timing chart showing the write and read operations for (1). In the figure, the vertical axis and the horizontal axis respectively indicate the memory address and time, the solid line indicates the read operation, and the alternate long and short dash line indicates the write operation. For example,
Write data 140 is a single density image signal of the n horizontal scan line period, the frequency 4F _SC write clock (WC
K) shows that data is sequentially written from the head address of the memory B. The write data 140 is read twice from the already-written head address portion at the read clock (RCK) of the frequency 8F _SC (read data 141, 142). The writing operation of the video signal in the (n + 1) th horizontal scanning line period must be performed subsequent to the end of the nth horizontal scanning line period. But memory B
Writing to the memory is unsatisfactory because the memory contents are overwritten during the read operation of the write data 140. Therefore, the video signal in the (n + 1) th horizontal scanning line period is written in the memory A (write data 143). In this manner, the write operation and the read operation are alternately performed for each horizontal scanning line period (1H) of the single density video signal by using the two line memories.

FIG. 9 is a timing chart showing a defect when the above operation is performed using one line memory. It is desired to read the single-density video signal (write data 160) in the nth horizontal scanning line period twice as read data 161, 162. However, when the write operation of the video signal (write data 163) in the (n + 1) th horizontal scanning line period is performed, this write operation is overtaken by the read operation of the read data 162 on the memory address. The line representing the data 163 intersects on the way. This means that the read data 162 before and after the intersection are the write data 163 and the write data 160, respectively. That is, on the image, two temporally different images are switched and displayed in the middle of every other horizontal scanning line, which causes a problem that the image quality is significantly impaired.

Next, the conversion processing from the double density to the single density video signal using the line memory 128 will be described. FIG.
Reference numeral 0 is a timing chart showing a write / read operation with respect to the line memory 128 (referred to as a memory C). The input video signal 122 synchronizes with the write data 18 in synchronization with the write clock (LWCLK) having a frequency of 8 F _SC.
It is written as 0, 181. These are the nth
It is a video signal in the horizontal scanning line period and the (n + 2) th horizontal scanning line period. The double-density video signal which is the input video signal 122 is thinned out every other horizontal scanning line by controlling the write enable signal to the line memory C, and the write data 180 and 181 are synchronized with the read clock (LRCLK) of the frequency 4F _SC. Then, conversion into a single density video signal (readout data 182) is executed.

[0008]

As described above, in the conventional conversion processing from a single-density to a double-density video signal, a temporally different video is displayed in the horizontal scanning line, and the image quality is remarkably increased. In order to avoid the problem of being damaged, a video signal conversion device having two line memories has been used. However, in this video signal converter for converting a single-density video signal to a double-density video signal, two line memories are required, and a means for alternately allocating reading and writing to both line memories is required, resulting in a large circuit scale. There was a problem of becoming. Further, in the video signal conversion device for mutually converting the single density video signal and the double density video signal, another line memory is required, so that there is a problem that the circuit scale further increases.

It is an object of the present invention to provide a video signal conversion device in which the number of line memories required for conversion is reduced and the scale is reduced.

[0010]

According to a first aspect of the present invention, a video signal converting apparatus for converting a single density video signal into a double density video signal is activated every one horizontal scanning line period of an input video signal. Writing means for writing an input video signal of one horizontal scanning line into the line memory in synchronization with one clock, and line memory synchronized with a double speed clock, activated every half horizontal scanning line period of the input video signal. Read-out means for performing an operation of reading out the output video signal of one horizontal scanning line from the line, and timing pulse for starting the writing means so that the horizontal retrace line period of the input video signal includes the horizontal retrace line period of the output video signal. And a start pulse supplying means for supplying both timing pulses with a phase difference from the timing pulse for activating the means.

With the above features, the present invention can convert a single-density video signal in consecutive horizontal scanning line periods into a double-density video signal by using one line memory. At this time, the read operation does not overtake the memory address of the write operation within the horizontal effective scanning period, so that image quality deterioration due to temporally different images being switched and displayed in the middle of the horizontal effective scanning line does not occur.

According to a second aspect of the present invention, a video signal conversion device for mutually converting a single density video signal and a double density video signal switches the frequency of a write clock and a read clock according to an input video signal. A clock switching means, and a writing means that is activated every one horizontal scanning line period of the input video signal and performs an operation of writing the input video signal of one horizontal scanning line to the line memory in synchronization with the write clock.
A reading means that is activated every horizontal scanning line period of the output video signal and performs an operation of reading the output video signal of one horizontal scanning line from the line memory in synchronization with the read clock, and a horizontal blanking period of the double-density video signal. Supplying both of these timing pulses with a phase difference between the timing pulse for activating the writing means and the timing pulse for activating the reading means so that the horizontal blanking period of the density video signal is included. And means.

As in claim 1, the present invention can convert a single-density video signal in consecutive horizontal scanning line periods into a double-density video signal by using one line memory. In addition to the above, according to the above feature, the present invention is used for conversion from a single density to a double density video signal by switching an input video signal to a double density video signal and mutually switching a write clock and a read clock. One line memory is also used as one line memory used for conversion from a double density to a single density video signal.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram of a single density / double density video signal conversion processing circuit according to a first embodiment of the present invention. The input video signal 2 to the video signal conversion device 1 is either a single density video signal (here, NTSC video signal) or a double density video signal (here, VGA standard video signal). The input selector switch 3 switches the path according to the type of the input video signal 2. When the input video signal 2 is a single-density video signal, it is directly supplied to the external monitor output single-density video signal processing circuit 4, and the double-density conversion unit 20 which performs the double-density conversion using the line memory 5 is used. Is supplied to the display display double-density video signal processing circuit 7. On the other hand, when the input video signal 2 is a double-density video signal, it is directly supplied to the display-display double-density video signal processing circuit 7 and also converted to a single density by using the line memory 8 to be output to an external monitor output unit. It is supplied to the density video signal processing circuit 4. The timing generator 9 generates a pulse that drives the line memories 5 and 8. The feature of the video signal conversion apparatus 1 used in this video signal conversion processing circuit according to the present invention is that the double density conversion is performed by one line memory 5.

FIG. 2 is a detailed block diagram of a portion related to the double density conversion. In this configuration example, the double density conversion unit 2
A single density video signal which is the input video signal 2 to 0 is obtained from the field memory 21. Although not shown, the input changeover switch 3 exists after the field memory 21 and is switched so as to lead the input video signal 2 to the line memory 5. The timing generator 9 generates a pulse for driving the line memory 5, and is also used for driving the field memory 21 in order to synchronize the input video signal 2 with the operation of the line memory 5. The timing generator 9 may generate a signal for accessing the line memory 5 from the sync signal of the input video signal 2.

The pulses FRE, LWE and LRE are read enable pulses for the field memory 21, respectively.
These are a write enable pulse and a read enable pulse for the line memory. FRE and LWE have a pulse width of one horizontal effective scanning period obtained by removing the horizontal blanking period from the period of 1H (one horizontal scanning line period) of the single density video signal. L
RE has a cycle of 1 / 2H of a single-density video signal and a pulse width of one horizontal effective scanning period of a double-density video signal. Pulse F
RCLK, LWCLK and LRCLK are a read clock of the field memory 21, a write clock and a read clock of the line memory 5, respectively. FRC
LK and LWCLK are 4F _SC and LRCLK, respectively.
Has a frequency of 8F _SC , and these clocks are supplied from the timing generator 9.

Pulses FRRST, LWRST and LRR
ST is a reset pulse for the read address counter in the field memory 21, the write address counter and the read address counter in the line memory 5, respectively. These are generated in response to the rising edge of each enable pulse and reset each address counter to 0. Each address counter is incremented by the corresponding clock while the corresponding enable pulse is at the high level.

The field memory 21 is composed of FRE and FRC.
In response to the supply of LK, the memory data forming the effective image area of one horizontal scanning line is output as the input video signal 2 in the 1H cycle. Each enable pulse and each reset pulse generated by the timing generator 9 are synchronized.
However, the input video signal 2 has a delay 2 due to processing in the path from the field memory 21 to the line memory 5.
2 (delay time d1) is received. The delay element 23 (delay time d1) is provided for the enable pulse and the reset pulse to the line memory 5 in order to compensate for this delay 22. The delay element 24 (delay time d2) is a timing pulse LWE and LWRST that activates writing in the line memory 5 so that the horizontal blanking period of the input video signal 2 includes the horizontal blanking period of the output video signal 25.
And LRE and LRRST, which are timing pulses for activating reading, are provided to have a phase difference. This will be described in detail later. The delay element 26 (delay time d2) provided in the path of the input video signal 2 has timing pulses LWE and LWRS generated by the delay element 24.
It is inserted to delay the input video signal 2 in accordance with the delay of T.

FIG. 3 is a timing chart showing write and read operations for the line memory 5 (referred to as memory A). In the figure, the vertical axis Y and the horizontal axis T indicate the memory address and time, respectively. The time at which the memory data of the first horizontal scanning line is output from the field memory is T = 0. In addition to H (horizontal scanning line period) as a unit of video signal time, a clock cycle t of frequency 4F _SC is used. Further, here, the delay time d1 of the delay element 23 = 13t,
The delay time of the delay element 24 is d2 = 3t. The line memory 5 stores 768 pixels corresponding to a video signal in the horizontal effective scanning period. 1H = 910t. Input video signal,
When each horizontal effective scanning period of the output video signal ends, the corresponding enable pulses LWE and LRE become Low level, and the address counter stops incrementing the address. Therefore, the value of the address counter is Y = 1 corresponding to the real address. Within the range of to 768. That is, actually, there is no value in the range of Y = 769 to 910. For convenience of explanation, in the drawing, each data line is drawn to extend to a virtual address range Y = 769 to 910, which corresponds to the horizontal blanking period. Many actual display devices do not display the start and end portions of one horizontal scanning period. The horizontal blanking period in the present application includes a period in which no display is performed in the above case.

The data lines 40 and 41 represent write data of the nth and (n + 1) th horizontal scanning lines, respectively, and the data lines 42, 43, 44 and 45 represent read data. m
Is an integer, the write operation is performed by the delay element 23.
It starts at mH + (d1 + d2) and has a period of 1H.
The read operation starts at mH / 2 + d1 and has a cycle of 1 /
Has 2H. The read operation of the read data 43 is
The address of the write operation of the write data 40 is overtaken by the virtual address Y = 904 corresponding to the horizontal blanking period. That is, in the video signal converting apparatus 1 embodying the present invention, address overtaking does not occur within the horizontal effective scanning period displayed on the screen as described above. for that reason,
The read data 42 is only for the (n-1) th horizontal scanning line (not shown), and the read data 43 and 44 are the write data 40.
The read data 45 includes only the (n + 1) th horizontal scanning line which is the write data 41. Therefore, the image deterioration due to the read data becoming the video signal of the adjacent horizontal scanning line before and after the address overtaking, which is a problem in the conventional technique, does not occur. Since the address overtaking described here occurs at a virtual address corresponding to the horizontal blanking period, each horizontal blanking period of the single-density video signal that is the write data (input video signal) means that the read data (output It is equivalent to including one horizontal blanking period of a double-density video signal which is a video signal).

The relative positional relationship between the two horizontal blanking periods is determined by the phase difference between the timing pulses for activating writing and reading in the line memory 5, which is determined by the delay time d2 of the delay element 24. . The delay time d2 can be set to 1 to 71t. Since the write operation and the read operation are cyclically repeated, the pulse LR on the read operation side is used instead of the delay elements 24 and 26.
Even if a delay of 384t to 454t is inserted in E and LRRST, the same phase shift occurs between the both operations. But,
In the present video signal conversion device, the case where the writing operation side is delayed, which is preferable in that the delay time of the delay element is short, has been described.

Conventionally, two line memories were required for double density conversion. On the other hand, the video signal conversion device 1 performs the conversion as described above with reference to FIGS. 2 and 3.
One line memory 5 can be used.

Single density conversion using the line memory 8 is
Since there is no difference from the conventional method, the description is omitted.

[Second Embodiment] FIG. 4 is a block diagram of a single density / double density video signal conversion processing circuit according to a second embodiment of the present invention. Since the circuit has a configuration similar to that of the circuit of FIG. 1, a code obtained by adding 60 to the code of the corresponding element in FIG. 1 is attached to FIG. 4, and the difference between both circuits will be mainly described below. The video signal converter 61 uses the line memory 65 to perform both double density conversion and single density conversion. In the second embodiment, the line density 65 including the double density conversion unit 20 is shown. Timing generator 6
9 differs from the first embodiment in that a pulse for driving the line memory 65 is generated by switching between double-density conversion and single-density conversion as described later. The feature of the video signal conversion device 61 used in this video signal conversion processing circuit according to the present invention is that the double density conversion is performed by one line memory 65 as in the first embodiment, and the drive pulse is simply switched. The point is that the line memory 65 also performs single density conversion.

The block configuration of FIG. 2 is the same for the line memory 65 of this embodiment. However, the only difference is that the timing generator has a mechanism for switching the pulse between the double density conversion and the single density conversion. Therefore,
For the sake of distinction, the timing generator of this embodiment will be referred to as a timing generator 69 (not shown), and the drive pulse supplied to the line memory 65 will be described with reference to FIG.

In the double density conversion, the pulse output from the timing generator 69 to each clock line is the first pulse.
Is the same as that described in the above embodiment. That is, LWC
A clock having a frequency of 4F _SC is output to LK and a clock having a frequency of 8F _SC is output to LRCLK. For LWE, a pulse width of 1H in one horizontal effective scanning period of a single-density video signal, and for LRE, a pulse width of 1 / 2H in one horizontal effective scanning period of a double-density video signal. Is output. A pulse is output to LWRST and LRRST in synchronization with the rising edge of the corresponding enable pulse.

The drive pulse in the single density conversion is switched as follows. That is, the frequency is 8F _SC for LWCLK and the frequency is 4F _SC for LRCLK.
The clock of is output. For LWE, the pulse width of one horizontal effective scanning period of the double-density video signal is output in a cycle of 1H, and for LRE, the pulse of the pulse width of one horizontal effective scanning period of a single-density video signal is output in a cycle of 1H. To be done. LW
A pulse is output to RST and LRRST in response to the rising edge of the corresponding enable pulse.

FIG. 5 is a block diagram of a clock switching device which is a clock switching means for switching the writing / reading clock according to the input / output video signal. This clock switch is provided in the timing generator 69. The frequency of the reference clock 80 is 8F _SC , and this is divided by the frequency divider 81 into the frequency 4F _SC . 8F
Both the _SC and 4F _SC clocks are synchronized by the phase compensators 82 and 83, and then, via the selector 84, the line memory write clock LWCLK and the read clock LR.
It is output to CLK. These output destinations can be changed by switching the selector 84 with the mode selection signal 85. Specifically, in double density conversion, 4F is added to LWCLK.
8F _SC is output to _SC and LRCLK, and L
WCLK to 8F _SC, switched so as to output a 4F _SC to LRCLK. The drivers 86 and 87 are provided in order to have a sufficient driving capability for the output load.

FIG. 6 is a timing chart showing write and read operations for the line memory 65 in the single density conversion. The notation is the same as in FIG. The circuit conditions other than the pulse switching, such as the delay time of the delay element, are the same as those in the first embodiment. Here, as in the first embodiment, the delay time d1 of the delay element 23 is
= 13t, the delay time of the delay element 24 is d2 = 3t,
The line memory 65 stores 768 pixels corresponding to a video signal in the horizontal effective scanning period, and 1H = 910t.
In the single density conversion, the timing generator 69
Controls LWE to a high level at a timing shifted by 1 / 2H with respect to the LRE, and controls to return to a low level after a horizontal effective scanning period of a double-density video signal. As a result, as shown as write data 100 and 101,
The double-density video signal is output every other horizontal scanning line to the line memory 6
No. 5 is written at addresses Y = 1 to 768. The data lines 102 and 103 are read data. The write data 100 is read as the read data 103 of the single density video signal. The write operation is (m + 1/2) H + (d1 + d2) by the delay element 23, where m is an integer.
, The read operation starts at mH / 2 + d1 and both operations have a period of 1H. By delaying LWE by 1 / 2H with respect to LRE, the write operation does not overtake the read operation on the line memory address, so that the image deterioration already described does not occur. The timing chart for the double density conversion is the same as that in FIG. The conversion operation is also the same as that described in the first embodiment, and therefore will be omitted.

The conventional single-density / double-density bidirectional video signal conversion device has two line memories for double-density conversion, and one line memory for single-density conversion separately. And used a total of three line memories. On the other hand, as described above, the video signal converter 61 performs bidirectional conversion on one line memory 5.
Can be done at.

[0032]

According to the video signal converter of the first aspect of the present invention, the number of line memories required for double density conversion is one. Since two line memories have been conventionally required, the present invention has an effect that the circuit scale of the video signal converter can be reduced.

According to the video signal conversion apparatus of the second aspect of the present invention, the number of line memories required for performing both the single density conversion / double density conversion is one. Since three line memories have been conventionally required, the present invention has an effect that the circuit scale of the video signal converter can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a video signal conversion processing circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a portion related to double density conversion.

FIG. 3 is a timing chart showing write and read operations in double density conversion.

FIG. 4 is a block diagram of a video signal conversion processing circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a clock switch.

FIG. 6 is a timing chart showing write and read operations in the single density conversion.

FIG. 7 is a block diagram of a conventional video signal conversion processing circuit.

FIG. 8 is a timing chart showing write and read operations in a conventional double density conversion.

FIG. 9 is a timing chart showing conventional problems.

FIG. 10 is a timing chart showing write and read operations in conventional single density conversion.

[Explanation of symbols]

1,61,121 Video signal converter, 2,122 input video signal, 3,123 input selector switch, 4,12
4 Single-density video signal processing circuit for external monitor output, 5,
8,65,125,126,128 line memory,
7, 127 Display double-density video signal processing circuit, 9 Timing generator, 21 field memory, 23, 24 Delay element, 25 Output video signal, 4
0,41,100,101,140,143,163,
180 write data, 43, 44, 103, 14
1,142,162,182 Read data, 80
Reference clock, 81 frequency divider, 84 selector, 85
Mode selection signal.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hideaki Sasaki 2-5-5 Keihan Hondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Shigeru Sawada 3-chome, Moriya-cho, Kanagawa-ku, Yokohama, Kanagawa 12th, inside Victor Company of Japan (72) Teruo Hotta, 3-12, Moriya-cho, Kanagawa-ku, Yokohama, Kanagawa Prefecture

Claims (2)

[Claims] 1. An input video signal synchronized with a first clock, comprising a line memory capable of storing a video signal of one horizontal scanning line and performing a writing operation and a reading operation of the video signal in parallel, In a video signal conversion device for converting an output video signal synchronized with a double speed clock having a frequency twice that of the first clock, the video signal conversion device is activated every horizontal scanning line period of the input video signal, and is synchronized with the first clock, A writing means for writing an input video signal of one horizontal scanning line into the line memory, and an output video of one horizontal scanning line from the line memory which is activated every ½ horizontal scanning line period of the input video signal and is synchronized with the double speed clock. Read-out means for reading out the signal and timing pulse and read-in for activating the writing means so that the horizontal blanking period of the input video signal includes the horizontal blanking period of the output video signal. A video signal conversion device, comprising: a start pulse supplying means for supplying both timing pulses with a phase difference from the timing pulse for activating the exclusive means. 2. A single-density video signal synchronized with the first clock, comprising a line memory capable of storing a video signal of one horizontal scanning line and performing a writing operation and a reading operation of the video signal in parallel. In a video signal conversion device for mutually converting a double density video signal synchronized with a double speed clock having a frequency twice that of the first clock, clock switching for switching the frequency of a write clock and a read clock according to an input video signal Means for writing the input video signal of one horizontal scanning line to the line memory in synchronism with the write clock, and the horizontal scanning line period of the output video signal. Read-out means that is activated each time and that reads the output video signal of one horizontal scanning line from the line memory in synchronization with the read clock; In order that the horizontal blanking period of the video signal includes the horizontal blanking period of the single-density video signal, a phase difference is provided between the timing pulse for activating the writing unit and the timing pulse for activating the reading unit, A start-up pulse supply means for supplying both of these timing pulses, and a video signal conversion device.