JPH0564129A - Picture signal processing unit - Google Patents

Abstract

PURPOSE:To improve the convenience of use by storing a reproduced picture signal in a frame memory according to a system clock synchronously with a horizontal synchronizing signal included in the picture signal so as to use effectively the frame memory. CONSTITUTION:When a picture signal is stored in a frame memory 5, a timing signal generator 12 generates a system clock signal used to frequency-divide an original oscillation clock with a frequency divider reset synchronously with a horizontal synchronizing signal included in a reproduction signal reproduced from a magnetic disk 11 and to operate the memory 5 and stores the picture signals by one frame for each field separately. Furthermore, when picture data of a 2nd field in the picture signal by one frame is read, after the picture data of the 2nd field are once stored in other storage area, the original oscillation clock signal is continuously frequency-divided without resetting the frequency divider thereby generating the system clock signal. Thus, the memory 5 is utilized efficiently and the convenience of use is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing apparatus for processing an image signal, and more particularly to an image signal processing apparatus having an image memory for temporarily storing an input image signal and outputting the stored image signal. Is.

[0002]

2. Description of the Related Art Conventionally, as an image signal processing device, there is a device having an image memory for temporarily storing an input image signal and outputting the stored image signal.

As an image signal processing apparatus as described above, there is an electronic still video camera, for example, but the image memory used in the electronic still video camera has a small number of connections and can be controlled by a simple memory controller. For the reason that data can be written and read at high speed, a FIFO (First In First Out) memory is often used.

In a conventional image signal processing device using a frame memory composed of a FIFO memory, when storing an image signal for one frame, the first half address area of the address of the frame memory is stored. The image signal of the first field is stored, and the image signal of the second field is stored in the latter half address area.

[0005]

However, in the above-mentioned conventional image signal processing apparatus, when the image signal for one frame stored in the frame memory is repeatedly read out for every one field, the frame memory is provided with the FIF.
Since it is an O memory, the image signal of the first field can be repeatedly read, but the image signal of the second field cannot be repeatedly read. For example, when the frame memory is used as a field memory,
Although the frame memory has a storage capacity capable of storing image signals for two fields, it can only write or read an image signal for one field, and thus can store two types of field images. When a signal is temporarily stored and the stored two types of field image signals are switched and output for each type, the field image signal must be stored and read for each type each time. The field image signal cannot be switched, which is very inconvenient.

According to the present invention, when the input image signal is temporarily stored in the image memory and the stored image signal is output, the memory can be effectively utilized and the image is not disturbed and stable. It is an object of the present invention to provide a user-friendly image signal processing device capable of outputting an image signal as a result.

[0007]

An image signal processing apparatus according to the present invention is an apparatus for processing an image signal, and includes a first field storage area for storing an image signal of a first field and a second field storage area.
A frame memory having a second field storage area for storing a field image signal and capable of storing an image signal for one frame; and an image signal for one frame separately for each field for the frame memory. When the image signal of the second field of the image signals for one frame stored in the frame memory after being stored in the second field storage area is read out, the second field stored in the second field storage area is stored. Image data is temporarily stored in the first field storage area and then read out, and when the input image signal is stored in the frame memory, a horizontal synchronization signal included in the input image signal. A system clock that operates the frame memory by dividing the source oscillation clock signal by a divider that is reset in synchronization with In the case of generating a black signal, reading the image data of the second field from the frame memory by the image data reading means, and storing the read image data again in the first field storage area of the frame memory, System clock signal generating means for generating a system clock signal for operating the frame memory by continuously dividing the frequency of the source oscillation clock signal without resetting the frequency divider in synchronization with a horizontal synchronizing signal. It is a thing.

[0008]

According to the above construction, when the input image signal is temporarily stored in the image memory and the stored image signal is output, the memory can be effectively utilized and the image is not disturbed. , The image signal can be stably output, and the usability can be improved.

[0009]

EXAMPLES The present invention will be described below with reference to examples of the present invention.

FIG. 1 is a block diagram showing a schematic structure of an electronic still video camera to which the present invention is applied, as an embodiment of the present invention.

In FIG. 1, 1 is a photographing lens unit, 2 is a diaphragm mechanism, and 3 is a photographed by the photographing lens unit 1, and an image through the diaphragm mechanism 2 is converted into an electric signal (that is, an image signal) and output. An image pickup sensor 13 is an image pickup signal which forms a luminance signal (hereinafter abbreviated as Y signal) and two types of color difference signal signals (hereinafter abbreviated as RY and BY signals) from the image signal output from the image sensor-3. A processing unit 4, an A / D converter for converting the input analog Y signal and analog RY, BY signals into a digital Y signal and digital RY, BY signals respectively, and outputting them, Digital Y signal output from A / D converter 4 and digital RY, BY
A frame memory for storing signals respectively, which is shown in FIG.
It is composed of two FIFO memories as shown in FIG.

Reference numeral 6 designates a digital Y state and a digital RY, BY signal read out from the frame memory 5 by performing a process such as a skew compensation process, a color difference signal serialization process or a simultaneous process, into a digital signal state. A digital signal processing section 7 for applying the digital Y signal and digital RY, B processed by the digital signal processing section 6;
A D / A converter for converting the -Y signal into an analog Y signal and analog RY and BY signals, respectively, and 9 for the D / A converter.
Analog Y signal and analog R output from A converter 7
A recording signal processing unit that forms a recording image signal by performing modulation processing or the like on the -Y and BY signals, 17, 1
Reference numeral 8 is a changeover switch, 11 is a magnetic disk on which a recording image signal is recorded, 10 is a magnetic head for recording a signal on the magnetic disk 11, and reproducing a signal from the magnetic disk 11, 16 is a magnetic disk 11 A motor 8 for rotating the disk is subjected to processing such as demodulation on the signal reproduced from the magnetic disk 11 by the magnetic head 10 to generate an analog Y signal and analog RY, BY signals.
A reproduction signal processing unit for restoring signals, 12 is a timing signal generator for generating various timing signals for controlling the operation of each unit, and 15 is an analog Y signal and an analog RY output from the reproduction signal processing unit 8. , B-Y signals to form and output a television signal of, for example, an NTSC system, and an encoder 14 is a control unit for controlling the operation of the entire system.

The operation of the electronic still video camera shown in FIG. 1 configured as described above during recording will be described below.

In FIG. 1, when a shooting / recording operation is instructed by an operation unit (not shown), the control unit 14 connects the changeover switches 17 and 18 to the R side in the drawing, and the shooting lens unit 1 shoots an image and the aperture is set. The image through the mechanism 2 is converted into an image signal by the image sensor 3 and input to the image signal processing unit 13.

In the image pickup signal processing section 13, a Y signal and RY, BY are obtained from the input image signal (for example, RGB signal).
A signal is formed and input to the A / D converter 4 via the changeover switch 18 connected to the R side in the figure.

Then, in the A / D converter 4, the Y signal converted into a digital signal and the RY and BY signals are
Once stored in the frame memory 5, the digital Y signal and digital R signal read from the frame memory 5 are stored.
The -Y and BY signals are input to the digital signal processing unit 6, and the digital signal processing unit 6 reads the digital Y and the digital RY and B- read from the frame memory 5.
The Y signal is subjected to processing such as skew compensation processing and RY and BY signal serialization processing in the state of a digital signal, which is then input to the D / A converter 7 to perform the D / A conversion. In the device 7, the digital Y signal and the digital RY, BY signals processed by the digital signal processing unit 6 are converted into an analog Y signal and analog RY, BY signals, respectively, and a recording signal is obtained. In the processing unit 9, the analog Y signal output from the D / A converter 7 and the analog RY and B signals.
A recording image signal is formed by performing a modulation process or the like on the -Y signal.

The recording image signal output from the recording signal processing unit 9 is input to the magnetic head 10 via the changeover switch 17 connected to the R side in the figure, and the motor 1
It is recorded on the magnetic disk 11 which is rotated by 6.

Next, the operation during reproduction of the electronic still video camera shown in FIG. 1 and configured as described above will be described.

In FIG. 1, when a reproducing operation is instructed by an operation unit (not shown), the control unit 14 causes the changeover switch 1 to operate.
7 and 18 are connected to the P side in the figure, and signals recorded on the magnetic disk 11 are transferred to the motor 16
The switch 17 is rotated by the magnetic disk 11 and is reproduced by tracing a track on the magnetic disk 11 by the magnetic head 10 and connected to the P side in the drawing as a reproduced signal.
Is input to the reproduction signal processing unit 8 via.

The reproduced signal processing unit 8 restores the analog Y signal and the analog RY and BY signals by performing processing such as demodulation on the input reproduced signal, and P and P in the figure respectively.
Via the changeover switch 18 connected to the
Input to the converter 4.

Then, in the A / D converter 4, the Y signal converted into a digital signal and the RY and BY signals are
Once stored in the frame memory 5, the digital Y signal and digital R signal read from the frame memory 5 are stored.
The -Y and BY signals are input to the digital signal processing unit 6, and in the digital signal processing unit 6, the digital Y signal read from the frame memory 5 and the digital RY,
Skew compensation processing, RY, BY for BY signals
After performing processing such as signal synchronization processing in a digital signal state, the signal is input to the D / A converter 7, converted into an analog Y signal and RY, BY signals, and input to the encoder 15. It

The analog Y signal and the RY and BY signals output from the D / A converter 7 are sent to the encoder 1
5, the signal is converted into a television signal of, for example, the NTSC system and is supplied to, for example, an external monitor device.

FIG. 2 is a diagram showing the detailed structure of the frame memory 5 of FIG. 1. In FIG. 2, 22 to 26 are data selectors, and 20 and 21 are field memories composed of FIFO memories.

FIG. 3 is a diagram showing a data storage state in the field memories 20 and 21 shown in FIG.

As shown in FIG. 3, the frame memory 5 constructed as shown in FIG. 2 has address areas Y1 and R for storing the Y signal of the image signal of the first field for the image signal of one frame. The address area where the -Y and BY signals are stored is C1, and the address area where the Y signal of the image signal of the second field is stored is the address area where Y2, RY, and BY signals are stored. When C2 is set, Y1 is stored in the upper address of the field memory 20, C2 is stored in the lower address, C1 is stored in the upper address of the field memory 21, and Y2 is stored in the lower address. ..

As shown in FIG. 3, the amount of data storage area in each field memory is determined by the Y signal and RY, B-.
The difference from the Y signal is that the sampling frequency when sampling the RY and BY signals is lower than the sampling frequency of the Y signal (here, the sampling frequencies of the RY and BY signals are This is because the sampling frequency of the Y signal is 1/4 frequency), and RY,
Since the signal band of the BY signal is located in a lower frequency band than the signal band of the Y signal, the sampling frequency can be lowered as described above, and the Y signal can be stored in each field memory as described above. Compared to the area, RY, BY
By reducing the signal storage area, the capacity of each field memory can be saved.

The operation of the frame memory 5 configured as shown in FIG. 2 during data storage will be described below with reference to the timing chart shown in FIG.

The timing chart shown in FIG.
FIG. 4 shows various timing signals supplied to the field memories 20 and 21 shown in FIG. 2, where a in FIG. 4 is a horizontal synchronization signal HD, b is a clock pulse CK supplied to the field memories 20 and 21, and c is a clock pulse. Field memory 20,
The write enable signal WE1 and d for storing Y data in the memory 21 is RY in the field memories 20 and 21,
It is a write enable signal WE2 for storing BY data.

The field memories 20 and 21 store Y data for one sample each time one pulse of the clock pulse CK is input while the write enable signal WE1 is at the high level (H in FIG. 4). , The clock pulse C while the write enable signal WE2 is at the high level.
Each time K is input as one pulse, RY for one sample,
It is configured to store BY data.

In FIG. 2, when storing one frame of image data, first, Y data of the first field image signal and RY, BY data are input, and the input Y data and R data are input. Data selector 2 for -Y and BY data
Image data storage areas Y1 and C1 of the first field of the field memories 20 and 21 via the channels 2 and 23 (see FIG. 3)
Memorize each.

At this time, the write enable signal WE1 and the clock pulse CK are input to the field memory 20, and the write enable signal W is input to the field memory 21.
E2 and the clock pulse CK are input.

Next, the Y data of the second field image signal and the RY and BY data are input, and the input Y data and the RY and BY data are exchanged in the data selector 22. The data is output and stored in the image data storage areas Y2 and C2 (see FIG. 3) of the second field of the field memories 20 and 21 via the data selector 23, respectively.

At this time, the write enable signal WE2 and the clock pulse CK are input to the field memory 20, and the write enable signal W is input to the field memory 21.
E1 and the clock pulse CK are input.

As described above, the image data for one frame is stored in the field memories 20 and 21 of FIG. 2 as shown in FIG.

Further, in FIG. 2, when the image data for one field is stored, it may be performed only by the operation for storing the image data for the first field described above.

The operation of reading data from the frame memory 5 configured as shown in FIG. 2 will be described below with reference to the timing chart shown in FIG.

The timing chart shown in FIG.
5 shows various timing signals supplied to the field memories 20 and 21 shown in FIG. 2, where a in FIG. 5 is a horizontal synchronizing signal HD, b is clock pulses CK and f supplied to the field memories 20 and 21, and Field memory 20,
The read enable signals RE1 and g for reading the Y data stored in 21 are the field memories 20 and 2.
1 is a read enable signal RE2 for reading the RY and BY data stored in No. 1.

Further, the field memories 20 and 21 read Y data for one sample each time one pulse of the clock pulse CK is input while the read enable signal RE1 is at the high level (H in FIG. 5). While the read enable signal RE2 is at the high level, every time one clock pulse CK is input, one sample of R-
It is configured to read Y, BY data.

In FIG. 2, when reading out one frame of image data, first, the field memories 20 and 2 are read.
1st field image data storage areas Y1, C1
The Y data and the RY, BY data of the first field image signal respectively stored in (see FIG. 3) are read out, and the read Y data and the RY, BY data are read out by the data selector 24. Output via.

At this time, the read enable signal RE1 and the clock pulse CK are input to the field memory 20, and the read enable signal R is input to the field memory 21.
E2 and the clock pulse CK are input.

Next, the second of the field memories 20 and 21
Y of the second field image signal stored in the field image data storage areas Y2 and C2 (see FIG. 3), respectively.
The data and the RY and BY data are read out, and the read Y data and the RY and BY data are exchanged at the data selector 24 and output.

At this time, the read enable signal RE2 and the clock pulse CK are input to the field memory 20, and the read enable signal R is input to the field memory 21.
E1 and the clock pulse CK are input.

As described above, the image data for one frame stored in the field memories 20 and 21 of FIG. 2 as shown in FIG. 3 is read out.

Further, in FIG. 2, when the image data for one field is read out, it is sufficient to perform only the above-mentioned operation for reading out the image data for the first field.

Next, in the frame memory 5 configured as shown in FIG. 2, the first of the field memories 20 and 21 is
The image data stored in the field image data storage areas Y1 and C1 and the image data stored in the second field image data storage areas Y2 and C2 are exchanged, or the first of the field memories 20 and 21 is exchanged. The image data stored in the field image data storage areas Y1 and C1 is stored in the second field image data storage area Y2.
The operation when dubbing to C2 will be described.

The timing chart shown in FIG.
6 shows various timing signals supplied to the field memories 20 and 21 shown in FIG. 2, where k and n in FIG. 6 are a read enable signal RE20 and a write enable signal WE20, l, o supplied to the field memory 20. ,
m and p are a read enable signal RE21 and a write enable signal WE21 supplied to the field memory 21,
The read address reset signal RSTR and the write address reset signals RSTW, g, r are the data selector 2
Data select signal SEL23 supplied to
It is SEL25.

Further, the data selectors 23 and 25 are adapted to select and output the data input to the lower stage of each data selector while the data select signals SEL23 and SEL25 are at the high level (H in FIG. 6). Is configured.

In FIG. 2, first, the field memory 2 is read according to the read enable signal RE21 (1 in FIG. 6).
1st field RY, BY data storage area C
The RY and BY data stored in No. 1 is read out, and the R of the first field of the field memory 21 is read again according to the write enable signal WE21 (o in FIG. 6) via the data selectors 26, 25 and 23. Written in the -Y, BY data storage area C1.

Then, the read enable signal RE20,
Field memory 2 according to RE21 (k, l in FIG. 6)
The Y data stored in the Y data storage area Y1 of the first field 0 and 21 and the Y data storage area Y2 of the second field are simultaneously read out, and the data select signal SE
The write enable signal WE is exchanged in the data selector 25 according to L25 (r in FIG. 6) and supplied to the field memories 20 and 21 via the data selector 23.
20 and 21 (n and o in FIG. 6), the Y data storage area Y of the first field of the field memories 20 and 21 is read again.
It is written in the Y data storage area Y2 of the first and second fields.

Similarly, the read enable signal RE20,
In accordance with RE21 (k, l in FIG. 6) and the read address reset signal RSTR (m in FIG. 6), RY of the first field of the field memories 20 and 21, BY data storage area C1 and R- of the second field are stored. The RY and BY data stored in the Y and BY data storage area C2 are simultaneously read out, and the data select signal SEL25 (see FIG. 6) is read.
Exchanged in the data selector 25 according to r) of
The field memories 20, 2 via the data selector 23
1 and the write enable signals WE20, 21
(N, o in FIG. 6) and write address reset signal R
Field memory 2 again according to STW (p in FIG. 6)
By writing in the RY and BY data storage areas C1 of the first field of 0 and 21 and the RY and BY data storage areas C2 of the second field, the field memory 20,
The image data of the first field and the image data of the second field stored in 21 are exchanged.

In the above operation, n, o in FIG.
6 instead of the write enable signals WE20 and WE21 shown in FIG.
0, WE21 are supplied to the field memories 20 and 21,
By supplying the data select signal SEL26 shown by u in FIG. 6 to the data selector 26, the field memory 2
The Y data of the first field is written in the Y data storage area of the second field of No. 1, and the RY and BY of the first field are stored in the RY and BY data storage areas of the second field of the field memory 20. By writing the Y data, the image data of the first field stored in the image data storage area of the first field of the field memories 20 and 21 is dubbed to the image data storage area of the second field of the field memories 20 and 21. Will be done.

Next, FIG. 7 shows a part of the structure of the timing signal generator 12 shown in FIG. 1, and FIG. 8 shows the signal waveform of each part of the structure shown in FIG. The operation of 12 will be described.

In FIG. 7, reference numeral 30 is a fall detection signal generator for detecting the fall of the signal, which is separated in the reproduction signal processing unit 8 from the reproduction signal reproduced by the magnetic head 10 from the magnetic disk 11 in FIG. Composite sync signal Sy
nc (w in FIG. 8) is input, and the fall detection signal generator 12 synchronizes with the clock signal having a frequency of 16 fsc (x and fsc in FIG. 8 are subcarrier frequencies) in synchronization with the reproduction signal processing unit. Composite sync signal Sy supplied from
The falling edge of the horizontal synchronizing signal in nc is detected, and the reset signal Reset (y in FIG. 8) is generated in synchronization with the falling edge of the horizontal synchronizing signal.

Reference numeral 31 is a gate circuit which gates the reset signal Reset output from the fall detection signal generator 30 according to a gate pulse input from a system controller (not shown), and 32 is the clock signal 16fsc.
Is a frequency divider that forms a clock signal 4fsc (z in FIG. 8) having a frequency of 4fsc by dividing the frequency by 4 and the frequency divider 32 is reset by a reset signal Reset output from the gate circuit 31. The clock signal 4fs output from the frequency divider 32 is
c is always synchronized with the trailing edge of the horizontal sync signal in the composite sync signal Sync.

Reference numeral 33 is a timing signal forming circuit which forms various timing signals from the composite synchronizing signal Sync supplied from the reproduction signal processing section 8 in synchronization with the clock signal 4fsc supplied from the frequency divider 32.

By the way, the gate pulse supplied from the system controller (not shown) to the gate circuit 31 is
1 is at a high level while the magnetic disk 11 is being rotated by the motor 16, and the gate circuit 31 opens the gate according to a high-level gate pulse while the magnetic disk 11 is being rotated by the motor 16. , Reset signal Reset output from the falling detection signal generator 30 is supplied to the frequency divider 32, and during this period, the reset signal Reset is supplied to the frequency divider 32.
The clock signal 4fsc synchronized with the horizontal synchronizing signal in the composite synchronizing signal Sync supplied from the reproduction signal processing unit 8 is generated by the frequency divider 32.

The magnetic disk 11 shown in FIG.
6 during the period when it is not rotated (that is, during the period when the composite signal Sync is not supplied from the reproduction signal processing circuit 8), or as described above, the first field stored in the field memories 20 and 21. Of the image data of the second field and the image data of the second field, and the image data of the first field stored in the image data storage area of the first field of the field memories 20, 21 is exchanged with the second field of the field memories 20, 21. During dubbing to the image data storage area of
A gate pulse supplied from a system controller (not shown) becomes low level, and the gate circuit 31 closes the gate according to the low level gate pulse, thereby dividing the reset signal Reset output from the fall detection signal generator 30. The frequency divider 32 is not supplied to the frequency divider 32, and the frequency divider 32 is not reset by the reset signal Reset during this period. The frequency divider 32 continuously generates the clock signal 4fsc by simply dividing the clock signal 16fsc by four. ing.

As described above, during the period in which the image signal recorded on the magnetic disk 11 is stored in the frame memory 5, the horizontal synchronization in the composite synchronization signal obtained from the reproduction signal reproduced from the magnetic disk 11 is performed. A clock signal 4fsc synchronized with the signal is formed, and a reproduced image signal is stored in the frame memory 5 according to the clock signal 4fsc.
Read out the image data stored in the frame memory 5,
For example, output as a reproduced image signal to an external monitor device or the like, exchange of image data of the first field and image data of the second field stored in the field memories 20 and 21 forming the frame memory 5, During dubbing of the image data of the first field stored in the image data storage area of the first field of the field memories 20 and 21 to the image data storage area of the second field of the field memories 20 and 21. Is configured to continuously generate a clock signal 4fsc obtained by simply dividing the clock signal 16fsc by 4, and to perform an image data read / write operation in the frame memory 5 in synchronization with the generated clock signal 4fsc. By configuring, the field memory configured by the FIFO memory is 2 It is possible to efficiently use the frame memory that it has, and when two types of field image signals are temporarily stored and the stored two types of field image signals are switched and output for each type, the field image signals You can switch, without disturbing the image,
The image signal can be stably output, and the usability can be improved.

[0059]

As described above, according to the present invention, when the input image signal is temporarily stored in the image memory and the stored image signal is output, the memory can be effectively utilized. At the same time, it is possible to provide an easy-to-use image signal processing device that can stably output an image signal without disturbing the image.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an electronic still video camera to which the present invention has been applied, as an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration of a frame memory 5 of FIG.

3 is a diagram showing a data storage state in field memories 20 and 21 shown in FIG.

FIG. 4 is a timing chart showing various timing signals supplied to the field memories 20 and 21 shown in FIG.

5 is a timing chart showing various timing signals supplied to the field memories 20 and 21 shown in FIG.

FIG. 6 is a timing chart showing various timing signals supplied to the field memories 20 and 21 shown in FIG.

7 is a diagram showing a partial configuration of a timing signal generator 12 shown in FIG.

8 is a diagram showing a signal waveform of each part of the configuration shown in FIG.

[Explanation of symbols]

 1 Imaging Lens Section 2 Aperture Mechanism 3 Imaging Sensor 4 A / D Converter 5 Frame Memory 6 Digital Signal Processing Section 7 D / A Converter 8 Playback Signal Processing Section 9 Recording Signal Processing Section 10 Magnetic Head 11 Magnetic Disk 12 Timing Signal Generation Device 13 Imaging signal processing unit 14 Control unit 15 Encoder 16 Motor 17 Changeover switch 18 Changeover switch

Claims (1)

[Claims] 1. An apparatus for processing an image signal, comprising: a first field storage area for storing a first field image signal; and a second field storage area for storing a second field image signal. A frame memory capable of storing the image signal of
When the image signal of the second field is read out from the image signals of one frame stored in the frame memory after storing in the separate storage areas for each field
When the image data of the second field stored in the field storage area is temporarily stored in the first field storage area and then read out, and when the input image signal is stored in the frame memory, A system clock signal for operating the frame memory is generated by dividing a source oscillation clock signal by a frequency divider that is reset in synchronization with a horizontal synchronizing signal included in an input image signal, and the image data reading means is provided. Thus, when the image data of the second field is read from the frame memory and the read image data is stored again in the first field storage area of the frame memory, the frequency divider is synchronized with the horizontal synchronizing signal. The frame memory is generated by continuously dividing the source oscillation clock signal without resetting. And a system clock signal generating means for generating a system clock signal for operating the image signal processing apparatus.