KR910006031Y1 - Selecting circuit of frame & field memory in case of reproducing still mode for digital image processing system - Google Patents

Abstract

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Description

Frame and Field Memory Selection Circuit of Still Image in Digital Image Processing System

1 is a block diagram of the present invention.

2 is a detailed circuit diagram of an address generator and an initial value selector during the first step.

3 is a timing diagram of a storage addressing interval of a memory.

4 is a memory diagram.

* Explanation of symbols for main parts of the drawings

1: A / D converter 2: memory

3: first control unit 4: D / A conversion unit

5: vertical synchronization detection unit 6: function selection unit

7: second control unit 8: address generating unit

9: Initial value selector

The present invention relates to a still picture implementing apparatus of a digital image processing system, and more particularly to a circuit that can select the still picture data in units of frames or fields.

Conventionally, when a still picture is implemented in a general VTR, the video head cannot properly scan a tape because the video head does not scan the tape correctly. As a result, a field of a video signal is stored in memory and played back. Was used. Electronic still cameras and the like used a technique of recording and reproducing one frame of a video signal. However, in the former case, since the still image is composed of one field of data on one screen, the resolution of the screen is reduced by half. In the latter case, a clear screen can be realized for a stationary subject. There was a problem that could not be avoided flicker (shake) of the flicker.

Accordingly, an object of the present invention is to provide a circuit capable of selecting a video data amount of a still image in a frame or field unit by a user's selection in a digital image processing system.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is an A / D converter 1 for converting and outputting an analog video signal received as a block diagram according to the present invention into a digital video signal by a sampling signal, and in a write mode upon receiving a second control signal. Memory 2 for storing digital video data of an image by receiving address signals and reproducing digital video data being stored in a second path formed by an address signal received in a read mode upon receiving a third control signal as a still picture; And receiving the output of the A / D converter 1 or the memory 2, and outputting the digital video data received by forming the first passage or the second passage according to the state of the fourth control signal. A control unit 3, a D / A conversion unit 4 which receives the output of the first control unit 3, converts and outputs an analog video signal by the sampling signal, and the received analog A vertical synchronous detection unit 5 for detecting a vertical synchronous signal from the video signal, and a second switching signal for switching the still image recording and reproducing or a first switching signal for continuously reproducing the received video signal. And a function selector 6, a function selector 6, and the function selector 6 for generating a mode signal for selecting an address in units of fields and frames when the second switching signal is generated. Outputting the fourth control signal for forming the first passage upon receiving the first switching signal, and generating the first control signal by the vertical synchronization detection signal upon receiving the second switching signal; Generating the second control signal for operating 2) in the write mode, and operating the memory 2 in the read mode upon receiving the first control signal. Inputs a second control unit 7 for generating the third control signal and the fourth control signal for forming the second passage, and an initial value address value of a predetermined standard, and is enabled when the first control signal is received; The address generator 8 generates an address signal and generates the fifth control signal when the address signal generation of the standard is completed and the mode signal of the function selector 6 to the address generator 8. It consists of an initial value selection section 9 for loading the address value having a field or frame specification.

Hereinafter, the present invention will be described in detail with reference to FIG. 1.

In the present invention, a process of directly outputting a video without recording and a process of realizing and reproducing a still image after recording a video signal are disclosed in detail in Utility Model Registration Application No. 88-8031 filed by the present applicant.

First, a process of directly outputting a video signal will be described. In order to directly output the received video signal as described above, the user may generate the first switching signal through the function selection unit 6.

In this case, the first switching signal (free-run) is a signal for directly selecting a video signal, and the second switching signal (still) selects a function of recording digital video data and then reproducing the still image.

At this time, when the second control unit 7 receives the first switching signal, the second control unit 7 generates the first control signal CR in the second state to clear the address generator 8. Fourth control signal Is generated to form the first passage of the first control unit 3. In this case, the address generator 8 does not perform an address operation, and the first controller 3 may be applied to the D / A converter 4 without output from the A / D converter 1. Form an output passageway.

Therefore, when an analog video signal is received through a VTR or a video camera, the A / D converter 1 converts the received analog video signal into digital video data by a sampling signal fs, and the first controller 3 ) Is the fourth control signal of the first state Digital video data received by the D / A converter 4 is applied to the D / A converter 4; The D / A converter 4 converts the digital audio data into an analog video signal by the sampling signal fs and outputs the analog video signal to a TV or a monitor. Therefore, this process is a case where the video signal is output directly without storing in the memory 2. Here, the video signal refers to a composite video frequency signal.

Secondly, the process of recording received digital video data and playing back to a still image will be described. In order to implement the reproduction function of the still picture, the user generates a second switching signal via the function selection unit 6. The second control unit 7 waits for the vertical synchronization signal to be detected from the vertical synchronization detector 5 by the second switching signal, and when the vertical synchronization signal is detected, the first control signal in the first state. Is generated to release and enable the address generator 8 in the clear state. At this time, the address generator 8 starts to receive an initial address value as an input terminal to store a video signal of a predetermined standard, and the second control unit 7 controls the first state of the first state. signal And a fourth control signal in a first state forming a first passageway The digital video data output from the A / D converter 1 is stored in the address position of the corresponding memory 2 outputted to the address generator 8. At this time, the address generator 8 generates a write address of the memory 2 by counting up to the initial address value loaded at the address enable time.

Thereafter, the address generator 8 generates a fifth control signal when all addressing of the standard data by the initial value is completed. When the fifth control signal is generated, the address generator 8 loads the corresponding initial value address again to perform a read address generation operation. In this case, the second control unit 7 controls the fourth control signal in the first state by the fifth control signal. Inverts to generate the fourth control signal 0C in the second state, and generates the third control signal in the first state. Occurs.

Accordingly, by the fourth control signal 0C in the second state, the first control unit 3 forms a second passage to block the passage of the received video signal and forms an output passage of the memory 2 to form the second passage. The data of the standard stored in the memory 2 are read out in accordance with the output address value of the address generator 8 by the third control signal in two states. Therefore, the first control section 3 outputs the digital video data being read from the memory 2, and the D / A converter 4 converts the digital video data into an analog video signal and outputs the analog video signal.

The process is a case in which the still image is reproduced by the stored data after the completion of storing the predetermined standard data. When the user selects the second switching signal again, the second control unit 7 causes the first control unit 2 to reproduce the still picture. Forms a first passage so that the received video signal is directly output again.

In the above configuration, the initial value selector 9 performs a function of selecting an initial address value of the address generator 8. That is, according to the selection of the function selection unit 6, the initial value selection unit 9 may select the function selection unit 6. The address generator 8 sets an initial address value so that the address value in units of frames can be loaded. Therefore, the address generator 8 generates an address signal in field or frame units according to the initial value address value determined by the initial value selector 9.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a detailed circuit diagram of the address generator 8 and the initial value selector 9 according to the present invention, wherein the address generator 8 includes the inverters 58, 59, 65, 66 and the 4-bit counter 60-64. The first control signal is received at the clear stage, and the burrow signal output terminal of the final count 64 is the burrow signal output terminal of each counter 60-63, and the down terminal of each counter 60-64 is configured. And an initial value address applied to an input terminal when the first control signal transitions to a first state and down counts an initial value address by a predetermined address clock, and when the count value is completed, the burrow. A counter circuit 71 for generating a fifth control signal at the output and simultaneously loading an initial value, and a decoder for decoding the MSB 3-bit output of the counter circuit 71 to generate a chip enable signal of the memory 2 ( Consists of 72) The.

In addition, the multiplexer 70 is configured as an input terminal of the counter circuit 71 by selecting an address value on the field or an address value in units of frames by the field or frame selection signal of the function selection unit 6.

3 is a view for explaining the process of setting the addressing section of the memory 2 in units of frames or fields according to the vertical synchronization signal, wherein one vertical synchronization section is a field memory section, and the vertical synchronization section is a frame memory section. Becomes

4 shows a configuration diagram of the memory 12.

Based on the above-described configuration, the present invention will be described in detail with reference to the second, third and fourth.

Here, the sampling signal fs of the A / D converter 1 and the D / A converter 4 is 14.3MHZ (4fsc = 4 × 3.58MHZ (color frequency), and the processing time is about 70ns, and the digital processing bit is It is assumed that the memory 2 is composed of 16 chips (4 Mbits in total) of 256 KSRAM (eight I / O ports, access time of about 100 ns), and therefore, the access time of the memory 2 is assumed. The A / D conversion output data (8 bits) are collected twice and processed into 16 bits to write / read the data accordingly. Chips are configured to be commonly enabled.

4 is a diagram illustrating a memory configuration, and may be used to set an initial value address in units of frames or fields.

First, the address of one frame memory is expressed by the following expression (1).

× 4 fsc (sampling frequency) × 525 × 8 (bit) × (16 bit I / O) = 238.875 (10) = 111010010100011011 (2)... … (One)

here × 4fsc is the number of horizontal pixels, and 525 is the number of vertical pixels.

Secondly, the number of addresses of one field memory is expressed by the following expression (2).

× 4 fsc (sampling frequency) × 263 (0.5H skew correction) × 8 (bit) × (16 bit I / O) = 119.665 (10) = 11101001110001... … (2)

here × 4fsc is the number of horizontal pixels, and 263 is the number of set pixels.

Comparing 2) equations as shown in Table 1 can detect common parts.

TABLE 1

As shown in Table 1, the common values of the initial address values of the frame memory and the field memory are 1A, 1C, 2A, 2D, 3A, 3D, 4D, and 5A, and 1B, 1D, 2B, 2C, 3B, It can be seen that 3C, 4A, 4B, and 5B. At this time, the initial value selection unit 9 for inputting the initial value selection signal of the function selection unit 6 outputs the result according to the field or frame selection signal as shown in Table 2 below.

TABLE 2

That is, since the initial selector 9 performs a multiplexer function, when the frame selection signal is generated when the memory 2 is used in units of frames, the multiplexer 70 outputs a "high" signal to the 2Y terminal side and 1Y. Outputs a "low" signal to the terminal. In addition, when the field selection signal is generated, the memory 2 performs the reverse operation.

Therefore, in Table 1, the common parts of the above formulas (1) and (2) are directly connected to the parallel input terminals of the counters 60-64 according to the corresponding logic values, and the logic " high " The part connects the 2Y terminal of the initial value selecting section 9, and the logical "high" part of the field memory connects the 1Y terminal. Therefore, when the frame selection signal is input, the multiplexer 70 applies the initial value address for the frame data as the count (60-64), and when the field selection signal is input, the multiplexer 70 also counters (60-64). Apply an initial value address for the field data.

When the first control signal of the first state is first generated by the second control unit 7, the counters 60-64 are released from the clear state. At this time, since the address outputs are all 0, the counter 64 is input when the address clock is input. The Burrow signal, which is the fifth control signal, is output. The counters 60-64 load down count the initial value address values generated by the initial value selector 9 by the fifth control signal, and the memory 2 is output from the counters 60-64. Stores digital video data received by the address signal. When the lead address of the memory 2 is generated as described above, when the counting of the initial value loaded from the counter 60-64 is completed (that is, addressing is completed), the counter 64 outputs the fifth control signal again. do.

Each of the counters 60-64 then reloads the initial value address value by the field or frame specification that is selectively output to the initial value selector 9. In addition, the fifth control signal is applied to the second control unit 7. At this time, when the second control unit 7 detects the fifth control signal, the third control signal in the first state is output to operate the memory 2 in the read mode, and the first control unit 3 generates a third control signal. A fourth control signal in a second state for forming the two passages is output.

From this point on, the address signals generated by the counters 60-64 are read addresses, so that field or frame video data recorded by realizing a still image is reproduced.

As described above, the storage standard data of the video data can be set according to the user's selection, so that the frame memory function for high resolution pursuit of the moving picture and the field memory function for eliminating the flicker phenomenon of the moving picture can be shared. There is an advantage.

Claims (1)

In the digital image processing system, a function selection unit 6 which is switched by a user's selection to generate a first switching signal for recording and reproducing a still image, and generates a field or frame selection signal for selecting a still image standard. And selecting the switching signal of the function selection unit 6 to generate a first control signal synchronized with the vertical synchronization signal, and to generate a second control signal and a fourth control signal in a first state, and to generate a fifth control signal. A second control unit 7 for releasing the second control signal and transitioning the fourth control signal to a second state when receiving the signal, and controlled by the second control unit 7 to write when the second control signal is received; The digital video data received in the set mode is stored in the reception address position, and the video read stored in the read address position is set in the read mode when the third control signal is received. A memory 2 for outputting and digital video data is received, and is controlled by the fourth control signal of the second control unit 7 to apply the received digital video data to the memory 2 in a first state. And a first control unit 3 for controlling a passage of the received digital video data at a second state and outputting the stored data of the memory 2, and the still image standard signal of the function selection unit 6; Generate a field initial value address for storing and reproducing the digital video data, and generating a frame initial value address for storing and reproducing digital video data of the frame selection signal temporal frame standard. It is enabled by the initial value selection part 9 which outputs, and the said 1st control signal of the said 2nd control part 7, Inputs the output of the banner selector 9 to generate an address in a selection standard unit, and outputs the address to the memory 2. When the address generation is completed, the fifth control signal is generated and supplied to the first controller 7. And a frame and field memory selection circuit of a still picture in a digital image processing system, characterized in that it comprises an address generator (8) for reloading said initial value address at the same time.