JP3070198B2 - Synchronizer for asynchronous video signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction device (TBC) for synchronizing an output video signal of a magnetic recording / reproducing device and video signals having different frequencies and phases with a reference video signal, and a synchronizing device. More specifically, in a video editing device such as a switcher that switches and outputs different video signals, synchronization of video signals having different time axes used for pre-processing of switching is used in order to prevent video synchronization disturbance at the time of switching. The present invention relates to a gasifier.

[0002]

2. Description of the Related Art In a magnetic recording / reproducing apparatus for handling video signals, generally, in the field of a broadcast VTR or the like having a strict standard,
A time axis correction device (TBC) is incorporated in the reproduction processing circuit of the VTR, and is controlled so that the vertical, horizontal, and color subcarrier phases of the reproduced video signal match the externally provided reference video signal. One reason for using TBC is that the video signal reproduced from the recording medium generally has insufficient mechanical accuracy of the medium and the accuracy of the speed control of the pickup, so that the reproduced video signal has many time-axis fluctuations. This is because they do not satisfy the vertical, horizontal, and color subcarrier frequencies specified by the broadcast standards and the like, and cannot be transmitted as a broadcast program as it is. Another reason is that in the field of production such as program software creation, video editing is performed, so switching video from multiple video devices,
Mixing or dubbing editing from VTR to VTR is performed, and in order to prevent the sync signal from being discontinuous at the video editing point and disturbing the video,
This is because it is necessary to synchronize the plurality of video signals on an absolute video basis.

FIG. 11 shows an example of a block diagram of a synchronizing device for a plurality of video signals. FIG. 12 is a timing waveform chart of each part in FIG. In FIG. 11, 1
Is a TBC, and 2 is a switcher, which switches the video signals Vin1 and Vin2 to obtain an output Vout by the above configuration. TBC1 converts the video signal to V
In1 and Vin2 are synchronized. As a method of synchronizing two video signals, a method of performing time axis correction on each of two video signals based on an absolute video reference and another simple method As a method, there is a method in which one video signal is used as a reference and the other video signal is subjected to time-axis processing and synchronized, and FIG. 11 corresponds to the latter. That is, the output reference which is based on the video signal Vin2
The two video signals are synchronized by correcting the time axis of the video signal Vin1 with the TBC1 as the video signal.

Here, the video signal is a composite video signal as shown in FIG. 12 in which a luminance signal and a carrier chrominance signal are multiplexed, and Vin1 and Vin2 are digital data (video) sampled at an integer multiple of the color subcarrier frequency. Signal data). The waveform of FIG.
1 represents the data value of each part in analog magnitude. CK1 and CK2 shown in FIG. 11 are sampling clocks for Vin1 and Vin2, respectively.
2. Description of the Related Art Conventionally, many types of composite video signal time axis correction devices have been proposed, which use a line memory for storing video signal data in several H sections (H is one horizontal cycle of the video signal) (Japanese Patent Application Laid-Open No. H10-163,028). No. 58-34688)
Or a combination of a line memory and a frame memory (capable of storing video signal data for one frame) (JP-A-62-168485, JP-A-62-23)
0192).

[0005]

The structure using only the line memory has a simple structure, but it is necessary to keep the horizontal and vertical phases of the input video signal data within a certain range with respect to the output reference video signal. . For example, nH
In the case of using a (n is an integer) line memory, the input video signal data must be input about (nH) / 2 earlier than the reference video signal. This is because there is always a delay in processing for correcting the time axis. Therefore, it is necessary to perform some kind of timing control on the source of the input video data. The phase change width of the input that can be corrected is also within the range of the capacity of the line memory. For example, for a reference video signal,
For video signal data input later than the minimum advance video data required for time axis correction processing, video signal data input with a delay relative to the reference video signal, and data whose phase is shifted by more than the correctable phase change width On the other hand, correct correction is not performed, and the horizontal position of the output image is shifted, and color hue of the image is changed due to discontinuity of color subcarriers.

The above-mentioned problem has been solved in the case of using a line memory and a frame memory in combination. This is because the large capacity of the memory allows correction even for a phase change of one or more fields. In addition, a large margin of timing control can be provided for the source of the input video signal data. The operation of shifting the vertical position of the horizontal line of the video data to be output with respect to the video reference without any control (referred to as line shift), Even when the field of the input video signal data differs from the field of the reference video signal by an operation of slightly shifting the phase (referred to as a sample shift), the time axis can be corrected without deteriorating the video. However, a large-capacity memory is required, and writing / reading control of the memory is complicated, so that the circuit scale becomes large, which is not practical in terms of miniaturization and cost reduction.

[0007]

In order to achieve the above object, an asynchronous video signal synchronizing apparatus according to the present invention is arranged so that the horizontal period of input video signal data is substantially n times (n is an integer), and
A first counter that counts a period that is m times (m is an integer) of the color subcarrier period, and that is substantially n times the horizontal period of the output reference video signal and that the color subcarrier period is m
A second counter that counts twice as many cycles, and an input video signal data that is written using the count output of the first counter as an address and reads data using the count output of the second counter as an address.
AM (random access memory).

[0008]

According to the present invention, the input video signal is output to the RAM by using the output of the first counter as a write address.
Written to, by reading the image data written from the RAM as a read address output of the second counter, the read data matches the horizontal phase and the color sub-carrier phase with respect to the output reference video signal It will be.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. In the following description, portions performing the same operations as those in the other drawings are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 1 is a block diagram of an apparatus for synchronizing an asynchronous video signal according to a first embodiment of the present invention. In FIG. 1, 3 is a first counter, 4 is a second counter, 5 is a 2H line memory, 6 is a first color frame detection circuit, and 7 is a second color frame detection circuit. FIG. 1 corresponds to TBC in FIG. FIG.
FIG. 2 is a timing waveform diagram of each part in FIG. As in the description of the conventional example, the input video signal Vin1, the output reference video
The signal Vin2 has an integer multiple of the color subcarrier frequency.
Digital data sampled by lock
The form of the video signal is a composite video signal. Also V
crr indicates the time axis of the input video signal Vin1 as the output reference video.
An output video signal synchronized with the image signal Vin2,
Is a composite video signal.

A composite video signal is generally composite data in which a horizontal synchronizing signal, a vertical synchronizing signal, color subcarrier phase information (burst) and video information are multiplexed.
In the video signal of the TSC system, the color subcarrier frequency fsc and the horizontal frequency fh have a relationship represented by the following equation.

4fsc = 910fh (1) Therefore, 1H is 455/2 times the color subcarrier period, and the color subcarrier phase of the video signal is inverted by 180 ° at the same horizontal position every 1H, and every 2H (N =
In 2) , the color subcarrier phases at the same horizontal position match , and 2H is the color subcarrier circumference.
455 times (m = 455). So, for example,
The sampling frequency of the input video signal Vin1 and the output reference video signal Vin2 is set to 4fsc, which is four times the frequency fsc. In FIG. 1, clocks CK1 and CK2 are clocks each having a frequency of 4 fsc. Counter 3 and 4 divides the clock CK1, CK2, respectively, the input video signal
Signal Vin1 and the horizontal cycle of the output reference video signal Vin2.
2H (n = 2) and the period of the color subcarrier
455 times (m = 455) is counted, and 1820 clocks are counted. The output of the counter 3 is the write address WADR, and the output of the counter 4 is the read address RA.
It is supplied to the 2H line memory 5 as DR. The line memory 5 receives the input video signal Vin according to the address WADR.
1 is written and read according to the address RADR.

As described above, according to this embodiment, the write address WADR and the read address RADR of the line memory 5 circulate at a cycle of an integral multiple of H, and the phase of the color subcarrier at the same address is constant. , Input video signal Vin1, output reference video signal Vin
Even if a large time-axis fluctuation occurs during the period 2 and the fluctuation cannot be absorbed within the capacity of the line memory, the data in which the horizontal position and the color subcarrier phase coincide with each other are repeatedly output or are output by skipping several Hs. Therefore, it is possible to prevent a shift in the horizontal position of the output image and a change in the hue of the image due to discontinuity of the color subcarriers, which has been a problem in the related art.

That is, writing and reading of the line memory 5
The circulating cycle of each outgoing is n times the horizontal cycle (n is
Integer) and m times the color subcarrier (m is an integer)
The output video signal when the memory fails.
The horizontal phase shift and the color subcarrier phase shift
With no visual problems.
Without having to worry about reducing the amount of memory needed.
it can. In FIG. 1, CFR1 and CFR2 are reset pulses for the counters 3 and 4, respectively, and determine the initial phase of each cycle of writing and reading of the line memory 5. In this embodiment,
Is n = 2 and m = 455 in the NTSC video signal.
As described in a certain case, the values of n and m are limited to this.
Color subkey, as shown in equation (1).
Derived from the relationship between carrier frequency fsc and horizontal frequency fh.
Value is acceptable.

FIG. 3 is a block diagram showing an apparatus for synchronizing an asynchronous video signal according to a second embodiment of the present invention. In FIG. 3, the embodiment of FIG. 1 is based on the PAL video signal. The components and operations are the same as those of the embodiment of FIG. 1, 8 is a first counter, and 9 is a first counter. 2 counter, 10 is 4H line memory, 11 is first
Is a second color frame detection circuit. FIG. 4 is a timing waveform chart of each part in FIG. As in the first embodiment, the input video signal
Vin1 and the output reference video signal Vin2 are
Data sampled with a clock that is an integer multiple of the rear frequency
Digital data, and the format of the video signal is composite
This is a video signal. Vcrr is the input video signal Vin
1 is synchronized with the output reference video signal Vin2.
Video signal, and similarly a composite video signal
And

The video signal of the PAL system is different from the video signal of the NTSC system, and the color subcarrier frequency fsc and the horizontal frequency fh have a relationship expressed by the following equation.

4fsc = (1135 + 4/625) fh (2) In other words, 1H is approximately 1 of the color subcarrier period.
135/4 times, and the color subcarrier phase of the video signal is inverted by 180 ° at the same horizontal position every 2H,
The color subcarrier phase at the same horizontal position matches every four horizontal periods (4H) . In this case, 4H is empty
-(1135 + 4/625) times the subcarrier period
However, the period of 4/625 times cannot be actually counted.
Therefore, it is set to 1135 times (m = 1135). For example, FIG.
Input video signal Vin1 and output reference video signal
The sampling frequency of the image signal Vin2 is 4 fsc. In FIG. 3, clocks CK1 and CK2 are clocks each having a frequency of 4 fsc. The counters 8 and 9 divide the clocks CK1 and CK2, respectively.
It is almost 4H (n = 4) of the horizontal cycle of Vin2 , and
1135 times the period of the error subcarrier (m = 1135)
4540 clocks, which is the cycle of The output of the counter 3 is supplied to the 2H line memory 5 as a write address WADR, and the output of the counter 4 is supplied as a read address RADR. The line memory 10 has the address WAD
The input video signal Vin1 is written according to R, and read according to the address RADR.

According to the present embodiment as described above, even in the case of the PAL video signal, the NTSC in the embodiment of FIG.
The same effect as that for the video signal of the system can be obtained.

CFR1 and CFR2 in FIG. 3 are used for reset pulses of counters 8 and 9, respectively.
In the case of the system, an eight-field period of an image is detected), and a reset pulse C
Generate FR1 and CFR2. As is clear from equation (2), the color subcarrier period is set to S for four horizontal periods (4H).
If C, it is expressed by the following equation.

4H = (1135 + 4/625) SC (3) That is, when the read timing is shifted from the write timing of the line memory 10, (4/4 /
625) The horizontal phase on the reading side is shifted by SC. Moreover if the address WADR not to apply reset counter 8,9, since the horizontal phase of the data for the RADR changes from moment to moment, the output reference video signal Vin2
May be unstable in the output video signal Vcrr. As is clear from equation (3), the address WA
The horizontal phase of data written to the line memory 10 with respect to DR is shifted by 625 times 4H, that is, 4 SC in one color frame (8 fields) of a PAL video signal. In other words, the relationship between the color subcarrier phase and the horizontal phase matches in one cycle for one color frame.

Therefore, in this embodiment, the detection circuit 1
1 and 12 detect the color frames of the video signals Vin1 and Vin2, respectively, and reset the count values of the counters 8 and 9 by reset pulses CFR1 and CFR2 generated at the head of the color frame, thereby obtaining the address WAD.
The values corresponding to the horizontal positions of R and RADR are made substantially constant. That is, it is possible to prevent the horizontal phase of the output video signal Vcrr from becoming unstable with respect to the output reference video signal Vin2 because the horizontal positions of the addresses WADR and RADR are not determined. In the present embodiment, P
When n = 4 and m = 1135 in the AL video signal
However, the values of n and m are not limited to these values.
Rather than a color subcarrier as shown in equation (3)
A value derived from the relationship between the frequency fsc and the horizontal frequency fh
Should be fine.

FIG. 5 is a block diagram of an asynchronous video signal synchronizing apparatus according to a third embodiment of the present invention. In the figure, reference numerals 8 and 9 denote first and second counters, which have the same configuration as the counters 8 and 9 in FIG. Similarly,
The line memory 10 has the same configuration as the line memory 10 in FIG. In this embodiment, the counter 8,
The reset pulses FR1 and FR2 supplied to 9 are pulses generated at the head of the video field, and are different from the embodiment of FIG. 13 and 14 are reset pulses FR1 and F
This is a reset pulse generation circuit for creating R2.
The reset pulse generation circuit 13 generates a write-side reset pulse FR1 and the reset pulse generation circuit 14 generates a read-side reset pulse FR2. The reset pulse generation circuits 13 and 14 generate pulses FR1 and FR2
Are different from the input video signal Vin1 and its sampling clock CK1 only in that they are the input video signal Vin1 and its sampling clock CK1, and the components are completely the same. . In the reset pulse generation circuits 13 and 14, 51,
52 and 54 are frequency dividing circuits, and 53 is an inverting circuit (gate). Similarly, 60, 61, 62, 64, 65 and 66 are latches, and 63 and 67 are gates, and constitute a reset pulse output synchronizing circuit. FIG. 6 is a timing waveform diagram of the reset pulse generating circuit 13 and the counter 8. Since the reset pulse generating circuit 14 has the same configuration, a duplicate description will be omitted.

As described above, in the embodiment of FIG. 3, the pulses CFR1 and CFR2 are one pulse in a color frame.
The address WADR and RADR always have a remainder of 4 SC for each color frame. Clock CK1, CK
If the frequency of 2 is four times that of the subcarrier, addresses 0 to 15 are generated at the end of the color frame as shown in the timing waveform diagram of FIG. In other words, since one color frame has eight fields, the addresses WADR and RADR are shifted from the horizontal phase by two clock periods per field. For example, when the video signal is edited in units of fields, the output reference video signal Vi is output.
It is often possible that the field of the input video signal Vin1 does not match n2. The field mismatch described above is not preferable because it causes a shift in the horizontal phase of the output video signal Vcrr and a fluctuation of the video for each color frame.
In this embodiment, reset pulses FR1 and FR2 generated at the timing when the color subcarrier phase and the horizontal phase coincide with each other are supplied to the counters 8 and 9 for each field.

As described above, since the address WADR representing the 4H period is delayed by about two clock horizontal phases in one field, the operation of advancing the phase of the address WADR by two clocks for each field is performed. Two clocks correspond to half of the color subcarrier period SC, and the address WADR
The sub-carrier phase for the address WADR is inverted by the phase change, and the color phase of the output video signal Vcrr becomes discontinuous for each field as it is. However, the two horizontal periods are almost equal to (1) from Expression (3).
135/2) SC, and by further changing the address WADR by 2H (2270 clocks), the color subcarrier phase is further inverted with respect to the address WADR, and the relationship between the WADR and the carrier phase changes the phase of the WADR. The phase before and after the change is the same, and the phase of the address WADR with respect to the horizontal cycle can be substantially the same as the state one field before.

The reset pulse generating circuit 13 changes the phase of the above-mentioned address WADR, and its operation will be described below. The detection circuit 50 detects the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSY from the input video signal Vin1.
Detect NC. The timing is as shown in FIG.
The frequency dividing circuit 52 divides the frequency of the vertical synchronizing signal VSYNC and outputs a signal DV which is inverted for each field. Further, the frequency dividing circuit 51 divides the horizontal synchronization signal HSYNC by four and outputs a signal DH having a 4H cycle. The detection circuit 50 similarly detects a color frame and outputs a reset pulse CFR generated at the head of the color frame. The operation of the reset pulse generation circuit 13 makes one cycle in one color frame, and the pulse CFR
Determines the initial phase. The signal obtained by inverting the signal DH of the 4H cycle with the signal DV by the inverting circuit 53 is 1
The signal G0 has a phase inverted by 2H for each field. Signals DV are latches 60, 61, 62, 64, 65,
66 and the output G of the inverting circuit 53 by the gates 63 and 67
Synchronization is performed at 0, and a reset pulse FR1 is output at the change point. Since the signal DH is a horizontal synchronizing signal separated from the video signal Vin1, the phase after one field with respect to the address WADR is earlier by two clocks CK2. That is, the reset pulse FR1 is generated for each field and becomes a reset pulse FR1 having a constant phase with respect to the horizontal phase and the color subcarrier phase of the video signal. The same applies to the reset pulse FR2. The frequency dividing circuit 54 generates a subcarrier, and the generated subcarrier is unstable because the period of the horizontal synchronization signal HSYNC is not an integral multiple of the clock CK1 or CK2, and the gate generated from the timing of the horizontal synchronization signal HSYNC. It is supplied as a clock for the latch 64 to stabilize the timing of the output G1 of the 63. This can be omitted when the signal G1 is always generated in a stable portion of the horizontal synchronization signal HSYNC.

By resetting the count values of the counters 8 and 9 with the pulses FR1 and FR2, addresses WADR and RADR having a constant horizontal phase and a constant color subcarrier phase with respect to the video signals Vin1 and Vin2 in each field of the color frame. can get. The operation of the line memory 10 by the addresses WADR and RADR is the same as the operation of the embodiment of FIG.

As described above, according to the present embodiment, the reset pulse generation circuits 13 and 14 generate the pulses FR1 and FR2 having a constant phase with respect to the horizontal phase and the subcarrier phase for each field, and the counters 8 and 9 Since the count value is reset, even when the field of the input video signal Vin1 is different from the output reference video signal Vin2, the color subcarrier phase and the horizontal phase are output substantially constant, and horizontal phase shift and image fluctuation for each color frame are prevented. Can be prevented.

The reset pulse generating circuits 13 and 14
, The detection of the signals HSYNC and VSYNC is omitted, the signal is reset by the pulse CFR, and the clocks CK1 and CCK are reset.
A counter that operates at K2 and counts the horizontal period and the field period is provided. For example, as in the case of the WADR of FIGS. The pulses FR1 and FR2 can be created, and the output of the counter of the 4H cycle is directly used as the address WA.
It is also possible to supply them as DR and RADR and omit the counters 8 and 9.

FIG. 7 is a block diagram of a device for synchronizing asynchronous video signals according to a fourth embodiment of the present invention. In the figure, reference numerals 8 and 9 denote first and second counters, which have the same configuration as the counters 8 and 9 in FIG. Similarly,
The line memory 10 has the same configuration as the line memory 10 in FIG. 15 and 20 are color frame detection circuits, 16 and 18 are latches, 17 is an adder, 21 and
2 is a frequency dividing circuit, 23, 24, 25, 26 and 27 are gates, 28 is a counter, 29 is a decoder, 30 is a shift register, and 31 is a selector.

The operation of the video signal blanking processing apparatus configured as described above will be described below.

When a PAL video signal is handled, according to the third embodiment shown in FIG. 5, the output reference video signal Vin2
In contrast, a stable output video signal Vcrr was obtained even when the phase of the input video signal Vin1 was shifted in units of fields. However, when the output reference video signal Vin2 and the input video signal Vin1 are completely asynchronous, for example, the input video signal is located at the center of the field of the output reference video signal Vin2.
When the field of the signal Vin1 switches, the output video signal Vcrr is not stable. In the third embodiment, the write address WADR is shifted backward by (SC / 2) from the horizontal phase at the beginning of the field of the input video signal Vin1, and the address RADR is similarly shifted at the beginning of the field of the output reference video signal Vin2. Shift backward by (SC / 2). Consequently the output video signal Vcrr is a shift of the write address WADR, shifts the phase fraction ahead of the top field of the input video signal Vin1, i.e. the video in the vertical synchronization period (SC / 2), the output reference
At the beginning of the field of the video signal Vin2, the address RAD
The image is shifted backward by the phase of (SC / 2) by the shift of R. That is, the obtained output video signal Vcrr has a horizontal phase shifted near the center of the screen, and the lower part of the screen is shifted to the right with respect to the upper part of the screen, resulting in an unsightly screen. Therefore, in the present embodiment, the input video signal Vin1
Even when the output reference video signal Vin2 is asynchronous, no video shift occurs.

The detection circuit 15 detects a color frame of the input video signal Vin1, generates a reset pulse CFR1 once at the head of the color frame, and determines the current field of the PAL color frame sequence (8 fields). Is a 3-bit field number INFNO.
Outputs 0-2. The counter 8 has a reset pulse CFR
The count value is reset by 1 and the address WA in the 4H section
DR is counted, and the operation is exactly the same as that of the counter 8 in FIG. The clocks CK1 and CK2 have a color subcarrier frequency of 4 as in the second and third embodiments.
Double the clock. Field number INFNO. 0 to
2 is used to count the number of fields in the color frame sequence.
Count from 0 to 7. The latches 16 and 18 and the adder 17 provide a field number INFNO. For the field of the output reference video signal Vin2. The output reference video signal Vin2 detected by the detection circuit 20 is synchronized.
Of the field number INFNO. 0-2 are latched, and the adder 17
1 After subtracting in the output reference by further latched at the beginning of the pulse FST field of the video signal Vin2, the field number of output reference video signal of the signal Vin1 at near the center of the field of the output reference video signal Vin2
And output in synchronization with the field of the signal Vin2. The synchronized field number is WFNO. The subtraction of 1 by the adder 17 is for correcting the delay of one field on average which occurs in the latches 16 and 18. The detection circuit 20 detects the output reference video signal Vin2, and in addition to the pulses VCENT and FST, the pulse HST outputted at the beginning of one horizontal period, the pulse CFR2 outputted at the beginning of a color frame, and the field of the current field is an even number. Signal RFNO. Indicating whether the field is an odd field or an odd field. Outputs 0. Signal RFN for convenience of explanation
O. 0 is the output reference video signal V generated by the detection circuit 15
in2 field number INFNO. The polarity is matched with the least significant bits 0 to 2, and the odd field is set to “L” and the even field is set to “H”. Here, the gate 23 outputs the pulse F
Outputs the logical sum of ST and pulse HST, and outputs 1 in the field.
The reset pulse is supplied to the counter 28 times. All inputs and outputs of the gate 23 are "L" active. The output timing is at the beginning of the field at the output reference video signal Vi.
This pulse has a constant phase with respect to the horizontal period of n2. The counter 28 sets the horizontal cycle to 113 of the clock CK2.
Counting as five clocks, the decoder 29 counts the count value of the counter 28 and outputs one pulse ADVHST in a horizontal cycle. The frequency divider circuits 21 and 22 divide the frequency of the pulse ADVHST, and the signal LAL which is inverted every horizontal cycle and the signal 1/2 which is inverted every two horizontal cycles.
Create LAL. The phases of the signals LAL and 1/2 LAL are initialized by a reset pulse CFR2 once in a color frame. The gate 24 controls the field number WFNO. Of the input video signal Vin1 synchronized with the field of the output reference video signal Vin2. This is for comparing whether or not the timings of the odd-numbered and even-numbered fields of the fields represented by 0 to 2 coincide with each other. If they do not coincide, the output of the gate 24 becomes "H" and the signal 1/2 LAL is 25
Is inverted by As a result, the output of the gate 26
The pulse WND becomes “H” only during the 1H period of the 4H period in which the phase output is controlled by the phase relationship between the input video signal Vin1 and the output reference video signal Vin2 .
To simplify the description, first, the timing (field number W) at the beginning of the color frame of the input video signal Vin1 is set.
FNO. 0-2 is considered as 0). Assuming that the pulse ADVHST is supplied in place of the input pulse SELH of the gate 27 in FIG. 7 ignoring the shift register 30 and the selector 31, the output RR of the gate 27 is one pulse every 4H. The phase is constant with respect to the color subcarrier phase with respect to the input video signal Vin1, and the horizontal phase is also constant at the head of the field. At this time, the counter 9 whose count value has been reset by the reset pulse RR counts the clock CK2 and repeats the counting in the 4H section (4540 clocks). In the embodiment of FIG. 7, the field number WFNO. FIG. 8 shows a timing waveform diagram of each part when the video field of the output reference video signal Vin2 is the first field and the second field when the value of 0 to 2 is 0. Regarding the timing of the other fields of the color frame, since the period of one frame (two fields) is 625H, the relation of the pulse WND with respect to the head of the field (vertical synchronization signal) is compared with the signal of one frame before. The description is omitted because it is only shifted by 1H. Phase relationship between the output address RADR and output reference video signal Vin2 of the counter 9, the counter in the third embodiment in FIG. 5 8
Is the same as the phase relationship between the output address WADR and the output reference video signal Vin2 after the reset pulse FR1 is supplied. Since the operation is the same as that of the third embodiment of FIG. 5, detailed description is omitted. However, the frequency divider 51 in the reset pulse generating circuits 13 and 14 in FIG. 5 corresponds to the frequency dividers 21 and 22 in FIG. , Gate 53 corresponds to gate 25. In the embodiment of FIG. 5, reset pulses FR1 and FR2 are generated at the beginning of each field so that the horizontal position and the color subcarrier phase are constant with respect to the input video signal Vin1 and the output reference video signal Vin2 . Therefore, the inverted pulse supplied to the gate 53 is
This is a signal for determining the odd-numbered and even-numbered fields of the video signal. In the embodiment of FIG. 7, the field number WFNO. Output reference video signal when 0-2 is 0
Address RADR at the beginning of the Vin2 field
The relationship between the horizontal phase and the subcarrier of the output reference video signal Vin2 and the sub-carrier is determined by the output address WADR of the counter 8 and the input video signal at the beginning of the first field of the input video signal Vin1 (the field where INFNO.
And the inverted pulse supplied to the gate 25 is an output reference video signal supplied from the detection circuit 20 created by the gate 24.
Vin2 odd / even field discrimination signal and field number WFNO. 0 to 2 as the least significant bit WFNO. This is a signal that is compared with 0.

In this embodiment, the output address WADR of the counter 8 is reset once at the beginning of the color frame, unlike the embodiment shown in FIG. 3, so that the address WADR is input as the field advances with respect to the first field.
The horizontal phase of the input video signal Vin1 is shifted forward by two clocks per field. The reason why the values for the horizontal phase of the address WADR are not aligned for each field is that the input video signal Vin1 and the output reference video signal Vin
This is to prevent a horizontal phase shift between the top and bottom of the screen of the output video signal Vcrr when 2 is asynchronous.
However, as is apparent from the above description, the output ADVHST of the decoder 29 is a pulse generated so as to have a constant phase with respect to the horizontal phase at the beginning of the field of the output reference video signal Vin2 , and is supplied as it is as the pulse SELH. Then, the horizontal phase of the output video signal Vcrr read from the line memory 9 at the output address RADR of the counter 9 is shifted backward by two clocks for each field. At the same time, the color subcarrier phase of the output video signal Vcrr is also inverted, and the color phase becomes discontinuous. Therefore, in this embodiment, the pulse ADVHS
T, ten pulses having a phase shift of two clocks each from clock T are generated. 0-2
And INFNO. 0 to 2 most significant bits INFNO. 2
By appropriately selecting the pulse according to
Create an ELH. Shift register 30 and selector 31
Is shown in FIG. FIG. 10 is a timing waveform chart of each part in FIG. In FIG. 9, 70
To 87 are pulses P0 whose pulses ADVHST are sequentially delayed by the clock CK2 and whose ten phases are different from each other by two clocks.
To P9, and constitute a shift register 30. Reference numeral 90 denotes a decoder, which has a field number WF.
NO. "H" is applied to the signal lines F0 to F7 corresponding to the values of 0 to 2.
The signal of is output. For example, when the value of the field number is 0, the signal F0 becomes “H”. 88, 89, 91-9
9 is a gate, and outputs F0 to F7 of the decoder 90 and a field number INFNO. Most significant bit IN of 0-2
FNO. 2, one of the pulses P0 to P9 is selected, and the pulse SEL finally selected from the gate 99 is selected.
H is output. Decoder 90, gates 88, 89, 91
To 99 constitute the selector 31. The apparatus for synchronizing asynchronous video signals according to the present embodiment will be further described with reference to FIGS. As described above, the pulse SELH has the field number WFNO. The value of 0-2 is 0-7
Every time the value increases, it is necessary to advance the timing forward by two clocks, and eight pulses P8 to P1 having different phases are generated in eight fields. Actually, pulses P9 and P0 having different phases by two clocks before and after the pulse groups P8 to P1 are also created for a reason to be described later, and a total of ten pulses having different phases P0 to P9. The pulse P9 having the earliest phase is the pulse ADV as shown in FIG.
HST may be used as it is. Normally, the field number INFO. 0 to 2 and the field numbers WFNO.0 to synchronize them with the field pulse FST of the output reference video signal Vin2. 0 to 2 are the same number, and the field number WFNO. If the value of 0 to 2 is 0, it is the top of 8 fields, so that 8 pulses P
1 to P8, the pulse P1 having the latest phase is the selector 3
1 is selected as pulse SELH and field number WFN
O. As the value of 0 to 2 increases, P2, P3, P
4, P5, P6, P7, and P8 are selected in this order. Therefore, the pulse ADVHST corresponds to the field number INFN.
O. When the value of 0 to 2 is 0, the input image of the address WADR created by the counter 8 when initialized by the pulse CFR1
In this embodiment, the clock signal is output 20 clocks earlier so that the phase for the image signal Vin1 and the phase for the output video signal Vin2 of the address RADR created by the counter 9 match. In FIG. 7, it is assumed that the horizontal phase of the reset pulse timing generated at the gate 23 with respect to the signal Vin2 is equal to the horizontal phase of the reset pulse CFR1 with respect to the input video signal Vin1, and the output HAD of the counter 28 is generated at the next clock generated at the gate 23. If it is set to 0, the decoder 29 may be configured so that the position where the pulse ADVHST of the decoder 29 is generated becomes the position 1124 of the counter output HAD.

As described above, according to the present embodiment, the field number WFNO. Address W when the value of 0-2 is 0
The address WADR is set to be equal to the horizontal phase and the subcarrier phase of the ADR input video signal Vin1 .
2 with respect to the output reference video signal Vin2 , and the sub-carrier phase is controlled. The value of 0 to 2 is faster phase of early the address RADRS the phase of the reference pulse ADVHST the horizontal phase aligned by two clocks per field in accordance with increases, the input video signal
Even when the color fields of Vin1 and the output reference video signal Vin2 are different, the horizontal and color subcarrier phases of the output video signal Vcrr are controlled to be constant in the first field of the color frame of the input video signal Vin1 . Thereafter, in the color frame, writing and reading to and from the line memory 10 are performed at addresses WADR and RADR of a continuous 4540 clock cycle without aligning the horizontal phase for each field. Therefore, the input video signal
Even if Vin1 and the output reference video signal Vin2 are asynchronous, no horizontal phase shift occurs in the output video signal Vcrr as in the third embodiment.

However, in this embodiment, the addresses WADR and RADR are continuous in the color frame, but a fraction of 4 SC (16 clocks) is generated at the end of the color frame for the same reason as in the second embodiment.
The discontinuity is caused, for example, when the signals Vin1 and Vin2 are asynchronous and the synchronized field number WFNO. Although the value of 0 to 2 is 0, the line memory 10
The written signal Vin1 is delayed, and the last field (field numbers INFNO.
Is not completed, or vice versa, the synchronized field number WF
NO. Even if the value of 0 to 2 is 7 (the last field of the color frame), the input image is actually stored in the line memory 10.
When the phase of the signal Vin1 advances and the writing of the data of the first field of the color frame has been started, the horizontal phase of the output video signal Vcrr is shifted by 4 SC (16 clocks). Accordingly, in the present embodiment, the input video signal Vin1 and the output reference
Even when the image signal Vin2 is asynchronous, a phase shift of the output video signal is prevented from occurring. As apparent from the above description, there is a possibility that the phase shift occurs. The field number WFNO. Of the input video signal Vin1 synchronized with the output reference video signal Vin2 as a reference. The values of 0 to 2 are the case of the leading 0 and the case of the final 7. For the first field,
Field number INFNO. If the field before synchronization represented by 0 to 2 is still the last field, the phase of the output video signal Vcrr is shifted backward by 16 clocks. In this case, the phase of the pulse ADVHST may be set 16 clocks earlier. The gate 89 in FIG.
Perform the operation that sets VHST ahead. Before the field number INFNO. Most significant bit INF of 0-2
NO. 2, "H" and "L". Similarly,
If the synchronized field is the last field, an operation of delaying the pulse ADVHST by 16 clocks is required.

As described above, according to the present embodiment, the address WA in one field is set by the shift register 30.
The horizontal pulse shifted by 2 clocks corresponding to the shift of the horizontal phase of the DRS is generated for eight fields, P1 to P8, and the phases P0 and P9 before and after the same, and the synchronized field number WFNO. 0 to 2 are selected and the field number WFNO. 0-2
, The field number INFNO.
By providing a selector 31 for detecting a shift at the head of a color frame of 0 to 2 and switching between the pulses P8 and P0 or a pulse P1 and P9, a phase shift of 4 SC of the output video due to the phase shift at the head of the color frame is also removed. be able to. That is, even if the input video signal Vin1 and the output reference video signal Vin2 are completely asynchronous, the input video signal
Vin1 is synchronized with the output reference video signal signal Vin2 , and the output video signal V has a small horizontal phase shift of the video.
crr can be obtained.

[0037]

As described above, according to the present invention, the number of cycles that is substantially n times (n is an integer) the horizontal cycle of the input video signal and m times (m is an integer) of the color subcarrier cycle is counted. 1 counter, a second counter that counts a period substantially equal to n times the horizontal period of the output reference video signal and m times the color subcarrier period, and the count output of the first counter as an address. Since it is composed of a RAM (random access memory) in which input video signal data is written and data is read using the count output of the second counter as an address, the horizontal phase and color of video can be reduced with a small memory capacity. The subcarrier phase can be efficiently synchronized.

A first detection circuit for generating a reset pulse once in a color frame sequence of the input video signal supplied to the first counter; and the output reference video signal supplied to the second counter. And a second detection circuit for generating a reset pulse once for the color frame sequence described above, whereby the horizontal phase of the output video can be easily determined, and an output video signal having a stable horizontal phase can be obtained.

Further, even when the period of n times of the horizontal period and the period of m times of the color subcarrier period are slightly different from each other as in the case of the video signal of the PAL system, the input video signal is supplied to the first counter. A first reset pulse generating circuit for generating one reset pulse at the beginning of a video field to be output;
A second reset pulse generating circuit for generating one reset pulse at the beginning of a video field supplied to the counter of each of the above, wherein each of the reset pulse generating circuits divides the horizontal frequency of the video signal by 1/4. A frequency dividing circuit, a second frequency dividing circuit for dividing a field frequency to generate a signal for discriminating an odd field and an even field of a video field, and determining the output of the 周 frequency signal of the horizontal frequency for the field. An inverting circuit that inverts with a signal, and a synchronization circuit that generates the reset pulse at a change point after synchronizing the discrimination signal of the field with the output of the inverting circuit, by correcting the horizontal phase for each field, Even when the color fields of the input video signal and the output reference video signal are different, the output video signal can be output without changing the horizontal phase and color phase. It can be initialized.

Similarly, when a PAL video signal is handled, a reset pulse indicating the head of a color frame sequence of the input video signal supplied to the first counter and a sequence number of the color frame sequence number are generated. A first detection circuit, a second detection circuit that generates a pulse indicating a head of a color frame sequence of the output reference video signal, a head of a field, and a head of a horizontal cycle, and a head and a horizontal of the output reference video signal. A horizontal counter that counts one horizontal cycle reset at the beginning of a field from the first pulse of the cycle, a decoder that creates horizontal pulses generated at the same count value of the horizontal counter, and a color frame of the output reference video signal The horizontal pulse is reset by a pulse indicating the beginning of the sequence, and is divided by 4 to A line counter for generating a gate pulse generated only during one horizontal cycle of a flat cycle, a shift register for delaying the horizontal pulse of the input video signal and generating a plurality of horizontal pulses having different phases, and a color for the input video signal A latch circuit that latches the sequence number of the frame with a pulse indicating the beginning of the field of the output reference video signal, and corresponding to the sequence number latched by the latch circuit and the sequence number before being latched,
A selector for selecting one horizontal pulse from the plurality of horizontal pulses having different phases; and a four-horizontal gate that gates the horizontal pulse selected by the selector with a gate pulse from the line counter and supplies the horizontal pulse to the second counter. By using a gate circuit that generates a reset pulse once per cycle, the input video signal is completely asynchronous with the output reference video signal. The optimum phase of the video signal to be output is selected, an average horizontal phase shift is small, and an output video signal free from discontinuous horizontal phase shift occurring at a field change point or the beginning of a color frame is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an apparatus for synchronizing an asynchronous video signal according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing timings of respective parts in the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of an asynchronous video signal synchronization device according to a second embodiment of the present invention.

FIG. 4 is a waveform chart showing the timing of each unit in the second embodiment.

FIG. 5 is a block diagram illustrating a configuration of an asynchronous video signal synchronization device according to a third embodiment of the present invention.

FIG. 6 is a waveform chart showing timings of a reset pulse generating circuit 13 and a counter 8 in the third embodiment.

FIG. 7 is a block diagram illustrating a configuration of an asynchronous video signal synchronization device according to a fourth embodiment of the present invention.

FIG. 8 is a waveform chart showing the timing of each part in the fourth embodiment.

FIG. 9 is a block diagram showing a detailed configuration of a shift register 30 and a selector 31 in the fourth embodiment.

10 is a waveform chart showing the timing of each unit in FIG.

FIG. 11 is a block diagram showing an example of a conventional asynchronous video signal synchronization device.

FIG. 12 is a timing waveform chart of each unit in FIG. 11;

[Explanation of symbols]

3,8 First counter 4,9 Second counter 5,10 Line memory 6,11,15 First detection circuit 7,12,20 Second detection circuit 13,14 Reset pulse generation circuit 16,18, 60-62, 64-66, 70-87 Latch 17 Adder 21, 22, 51, 52, 54 Frequency divider 23-27, 63, 67, 88, 89, 91-99 Gate 28 Counter 29, 90 Decoder 30 Shift register 31 selector 50 detection circuit 53 inversion circuit

Claims (4)

(57) [Claims] (1) a frequency of an integer multiple of a color subcarrier;
The input video signal sampled by the sampling clock
Same as the output reference video signal that is asynchronous with the input video signal
A synchronizing device for an asynchronous video signal to be synchronized, wherein the input video signal is synchronized with a sampling clock of the input video signal.
It is substantially n times (n is an integer) the horizontal period of the video signal , and
A first counter that counts a cycle of m times (m is an integer) the color subcarrier cycle, and a sampling clock of the output reference video signal,
A second counter that counts a cycle that is substantially n times the horizontal cycle of the output reference video signal and m times the color subcarrier cycle; and that the input video signal data has the count output of the first counter as an address. The input which has been written and written using the count output of the second counter as an address.
And a RAM (random access memory) configured to read the input video signal. 2. A first detection circuit for generating a reset pulse once in a color frame sequence of an input video signal supplied to a first counter, and a color frame sequence of an output reference video signal supplied to a second counter. 2. The asynchronous video signal synchronizing device according to claim 1, further comprising a second detection circuit for generating a reset pulse once. 3. A first reset pulse generating circuit for generating one reset pulse at the head of a video field supplied to a first counter from an input video signal, and supplied to a second counter from an output reference video signal. A second reset pulse generating circuit that generates one reset pulse at the beginning of a video field, wherein each of the reset pulse generating circuits divides a horizontal frequency of the input video signal by four; A second frequency divider circuit for dividing the field frequency of the input video signal to generate an odd field and even field discrimination signal; and inverting the output of the horizontal frequency divided by 4 signal with the discrimination signal of the field An inverting circuit, and a synchronizing circuit that generates the reset pulse at a change point after synchronizing the discrimination signal of the field with the output of the inverting circuit. 2. The apparatus for synchronizing asynchronous video signals according to claim 1, wherein: 4. A reset pulse indicating a head of a color frame sequence of an input video signal supplied to a first counter, a first detection circuit for generating a sequence number of the color frame, and a color frame of an output reference video signal. The beginning of the sequence,
A second detection circuit for generating a pulse indicating the beginning of the field and the beginning of the horizontal period; and counting one horizontal period reset at the beginning of the field from the beginning of the field and the beginning of the horizontal period of the output reference video signal. A horizontal counter, a decoder for generating a horizontal pulse generated with the same count value of the horizontal counter, and a pulse indicating the beginning of a color frame sequence of the output reference video signal, and dividing the horizontal pulse by 4 a line counter for generating a gate pulse generated only for one horizontal period of 4 horizontal period interval period, delaying the horizontal pulse, a shift register for generating a plurality of horizontal pulses having different phases, of the input video signal Latch the sequence number of the color frame with the pulse indicating the beginning of the field of the output reference video signal A selector circuit for selecting one horizontal pulse from the plurality of horizontal pulses having different phases in accordance with the sequence number latched by the latch circuit and the sequence number before being latched; 2. The asynchronous video according to claim 1, further comprising: a gate circuit that gates the selected horizontal pulse with a gate pulse from the line counter and generates a reset pulse once every four horizontal cycles to be supplied to a second counter. Signal synchronization device.