JP2800724B2 - Image synthesis circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image synthesizing circuit,
In particular, the present invention relates to an image synthesizing circuit that displays a video image using an image such as a personal computer (hereinafter simply referred to as a personal computer) by using chroma key synthesis or the like.

[0002]

2. Description of the Related Art Conventionally, there are several methods for synthesizing an image of a personal computer or the like and an image of a video, and a method called superimpose is the most typical example. 3 and 4 show typical examples of the prior art.

FIG. 3 is a diagram showing a conceptual configuration of Japanese Patent Application Laid-Open No. 1-110181. Basically, the input analog video signal and the digital image output from the digital image generation circuit 24 are
Superimpose with 5 In this superimposition, the VCO 20, the phase comparator 21, the saw-tooth wave generator 22, and the 1 / N frequency divider 23 generate a PLL (ph
An ase-locked loop) circuit 26 is configured to generate a clock for the input video signal. This clock is used as a dot clock for the digital image generation circuit 24, and the output image and video signal are superimposed by the superimposition circuit 25. In this conventional example, even if the display frequency on the digital image side changes, P
It is characterized by being constituted by one PLL circuit without using a plurality of LL circuits 26.

FIG. 4 is a diagram showing a conceptual configuration of Japanese Patent Application Laid-Open No. 3-59438. In this method, an image of one of a television and a personal computer is cut and superimposed on the other screen. In this superimposition procedure, the synchronization signal of the personal computer is made to coincide with the synchronization signal of the television using the TV signal synchronizing separation 32, the television signal processing circuit 31, and the clock number conversion phase matching circuit 33. In addition, a clock number conversion phase matching circuit 33 for matching the phases of the subcarriers for equalizing the color reproducibility and reproducing the pixels of the personal computer with the synchronization signal of the television is provided. Further, in order to detect a switching signal in which one of the television and the personal computer is prioritized and a superimposed signal having a level equal to or lower than the level of the synchronizing signal is added to the prioritized signal, a detection circuit 36, a delay circuit 35, a matrix 37, It has a high-speed switching circuit 30 that switches between a television signal and a personal computer signal at high speed by a switching signal. This conventional example is characterized in that superimposition can be performed with a few circuits such as the detection circuit 36 and the phase matching circuit 33.

[0005]

However, the above-mentioned Japanese Patent Application Laid-Open Nos. Hei 10-17881 and Hei 3-59438.
In the conventional example shown in the above publication, the video image and the image of the personal computer are simply superimposed.

In recent years, there has been a demand for a function of providing a frame such as a window on a part of a personal computer screen and outputting a video image within the frame (hereinafter referred to as a window). In the conventional example shown in FIG. 4 such as Japanese Patent Application Laid-Open No. 3-59438, it is possible to simply output a video image to a part of the personal computer screen, but in a recent personal computer having various windows, the windows overlap each other. And you get a video. For this reason, it is difficult to use it for a personal computer having a complicated window. In order to eliminate this, a function of chroma key synthesis such as outputting a video image to a specific color of a personal computer by a function of making the color transparent is required.

[0007] Further, personal computers are of various models, and display timings on the personal computer side are slightly different. If the timing is shifted, the timing of the portion for displaying a specific color and the portion for outputting the video in the chroma key synthesis may not match, and the video may not be properly displayed in a predetermined window of the personal computer and may be shifted. Conventional image synthesis circuits have these problems.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image synthesizing circuit which facilitates adjustment of a display position when synthesizing image data of various image sources.

[0009]

In order to achieve the above object, an image synthesizing circuit according to the present invention determines whether or not a specific portion of first image data has a predetermined coloring, and based on the determination, determines whether or not the first portion has a predetermined color.
Comparator means for outputting an image switching signal synchronized with the horizontal and vertical regions of the image data, storage means for storing second image data to be synthesized with the first image data, and synchronization with the image switching signal and, and the image detects the phase difference between the key signal for identifying the switching signal and an image synthesis position phase correcting rows Utotomoni, a read timing signal generating means for outputting a timing signal for reading the second image data, Image synthesizing means for inputting the first image data, the second image data, and the image switching signal, synthesizing the second image data with the first image data, and outputting the synthesized image data; The phase correction automatically adjusts the image combining position of the first image data and the second image data.

The read timing signal generating means displays a window register for specifying an image combining position and size for combining the second image data with the first image data, and displays the combined image data. Operation with the dot clock and horizontal synchronization signal for
A counter for outputting a plurality of window key signals by a window register, and a plurality of windows by a window register.
A decoder that selects one of the dow key signals to generate a key signal, and a phase difference between the image switching signal and the key signal, and determines a window key signal to be selected by the decoder.
It is preferable to have a phase determination unit that outputs a selection signal for correction, and an image data read timing generation unit that receives a dot clock and an output signal of a counter and outputs a timing signal.

Further, the window register, the counter and the decoder are preferably composed of a pair for a horizontal direction and a pair for a vertical direction for displaying a synthesized image, respectively.

[0012]

Therefore, according to the image synthesizing circuit of the present invention,
It is determined whether or not a predetermined portion of the first image data has a predetermined coloring, and based on this determination, an image switching signal synchronized with the horizontal and vertical regions of the first image data is output. First storing second image data to be image compositing the image data, the image synchronization vital image switching signal switching signal and image
A phase difference from a key signal for identifying the image combining position is detected and the phase is corrected, and a timing signal for reading the second image data is output. The first image data, the second image data, and the image switching signal are input, the second image data is combined with the first image data, and the combined image data is output. Therefore, by the phase correction of the read timing of the second image, the image combining position of the first image data and the second image data is automatically adjusted.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an image synthesizing circuit according to the present invention. Referring to FIGS. 1 and 2, there is shown an embodiment of an image synthesizing circuit according to the present invention. FIG. 1 is a block diagram showing the circuit configuration of one embodiment, and FIG. 2 is a timing chart for explaining the operation of the circuit of FIG.

In FIG. 1, the image synthesizing circuit of this embodiment is
A comparator section 1 for determining whether or not a specific portion of the first image data has a predetermined coloring; a video memory (storage section) 3 for storing the image data; and a read timing for outputting a timing signal for reading the image data It comprises a signal generation unit 2 and a selector (image synthesis unit) 4 that synthesizes the first image data with the second image data and outputs the synthesized image data.

The comparator 1 has a color key register 10 for holding a predetermined color signal and a color for outputting a display switching signal 7a, 7b based on the determination as to whether the color key register 10 is a predetermined color or a palette index. A key comparator 11 is provided.

The read timing signal generator 2 includes a horizontal window register 14a and a vertical window register 14 for designating a display position on a screen.
b, a horizontal counter 13a and a vertical counter 13b that synchronize with the dot clock, a horizontal decoder 12a and a vertical decoder 12a, and a phase determination for outputting a predetermined selection signal to these decoders 12a and 12b. And a video image data readout timing generation unit 16 for generating a timing signal for reading out video image data as second image data from the video memory 3 simultaneously with the display switching signals 7a and 7b. Is done.

The color key register 10 is a storage unit for storing a predetermined color signal or a color or area designation symbol in a palette index. The signal held in the color key register 10 is output to the color key comparator 11.

The color key comparator 11 determines whether the image data of the PC image, which is the first image data, is the color or area designated by the color key register 10, and stores the data in the corresponding horizontal and vertical areas. A discriminator that outputs display switching signals 7a and 7b. In this determination, a PC image or the like, which is output image data of a personal computer transferred digitally, is compared with an output signal specified by the color key register 10, and the display switching signal 7a, 7b is output.
Further, in response to an instruction of the selection signal 19c from the CPU (not shown), the above-described phase determination is not performed, and the horizontal
a and the output signal from the vertical decoder 12b, the horizontal key signal 18a and the vertical key signal 18b
Can be output as is.

The horizontal decoder 12a and the vertical decoder 12b include a horizontal window register 14a.
And a circuit unit for generating and outputting a horizontal key signal 18a and a vertical key signal 18b for enabling each window based on the values output from the vertical window register 14b. The decoders 12a and 12b have a function of decoding several dots and several lines before and after the values of the horizontal and vertical window registers 14a and 14b.
Decoders 12a and 12b and phase discriminator 1
Reference numeral 5 denotes a PLL circuit that automatically corrects the timing of the output key signals 18a and 18b based on the selection signals 19a and 19b output from the phase determination unit 15. That is, when the phase determination unit 15 determines that there is a phase difference, the dot signals and / or the key signals 18a, 18b shifted forward and backward by one each before or after the line.
Generate

The horizontal counter 13a operates according to a dot clock, and the vertical counter 13b operates as a horizontal synchronizing signal. Based on the count values of these counters 13a and 13b, a timing signal for reading out the image data stored in the video memory 3 is generated. Each timing signal is output to the horizontal decoder 12a and the vertical decoder 12b.

The horizontal window register 14a and the vertical window register 14b are storage units for storing a position specifying signal for specifying a position and a size of a video image to be displayed on the screen. .
The position designation signal is written by a write signal from the CPU, and the written signal is divided into a horizontal counter 13a, a decoder 12a and a vertical counter 13a.
b and the decoder 12b.

The timing generation section 16 is a circuit section for generating a timing signal for reading out video image data to be synthesized with a PC image from the video memory 3. This timing signal includes timing signals output from the horizontal counter 13a and the vertical counter 13b,
It is generated based on the dot clock signal.

The selector 4 is a two-input one-output line selection circuit. Each of the two input terminals A and B has
The PC image signal and the video image data output from the video memory 3 are individually input. Selection of any one of these two signals is based on the display switching signals 7a and 7b input to the input terminal S for selection control. The selected image signal is output from the output terminal Y.

FIG. 2 is a timing chart showing the procedure for correcting the position of the image synthesizing operation in this embodiment. The waveforms (a) and (a ') are for horizontal or vertical decoder 12
a, 12b, ie, the key signal 18a or 1
8b. Waveforms (b) and (b ') are display switching signals 7a or 7b which are output signals of the color key comparator 11. Waveform (c) is waveform (a) and waveform (b)
The portion that matches is cut out. Further, the waveform (a) based on the key signal 18a of the horizontal decoder 12a as a reference and the waveform (b) at the timing non-coincidence portion are (d).

The waveforms (a ') to (d') and the waveform (a)
The difference between (d) and (d) is the difference in the positional relationship between the PC image and the video image before and after. If the waveform (d) follows the rising edge of the waveform (a), it indicates that the display switching signal 7a or 7b of the color key comparator 11 of the waveform (b) is earlier than the waveform (a). . In the case of the waveform (a ′) to the waveform (d ′), the opposite is shown. Based on this, the phase determining unit 15 determines the coincidence / non-coincidence of the mutual image positions and the order of the non-coincidence.

The color key comparator 11 outputs the waveform (b) so that the waveforms (d) and (d ') do not occur.
And the phase discrimination and phase correction of (b ′) are executed.
As a result, the timings of the key signals 18a, 18b and the display switching signals 7a, 7b from the color key comparator 11 can be stably matched.

Using the display switching signals 7a and 7b of the color key comparator 11 at this time, the selector 4 reads out from the video memory 3 using the dot clock and the horizontal counter 13a and the vertical counter 13b. The video image data and the PC image data are combined.
As a result, it is possible to combine the video image and the PC image using the chroma key having no positional deviation.

The image synthesizing procedure of the image synthesizing circuit of the embodiment constructed as described above is as follows. Make sure that either the color of the PC image data transferred digitally or the palette index is designated as a specific color.
The color key comparator 11 determines. The display switching signal 7 is applied to the determined horizontal and vertical areas.
a and 7b are output.

On the other hand, a window signal for setting the position and width of the window to be displayed is written into the horizontal window register 14a and the vertical window register 14b by the CPU connected to the image synthesizing circuit of this embodiment. It is.

The horizontal counter 13a operates according to the dot clock, the vertical counter 13b operates according to the horizontal synchronization signal, and generates a horizontal window key signal from several dots before and after the horizontal window register 14a. Is selected by the horizontal decoder 12a, and similarly the vertical window register 14b is selected.
Generating a window key signal for vertical than before and after several lines of the one of them vertical decoder 12b to-select <br/>.

The phase discriminating section 15 calculates the difference between the phases of the display switching signals 7a and 7b output from the color key comparator 11 and the key signals 18a and 18b output from the horizontal and vertical decoders 12a and 12b. Is determined. This determination procedure is based on the detection of the waveforms (a) and (b) to (d) or the detection of the waveforms (a ′) and (b ′) of (d ′) in FIG. This display switching signal 7
If a phase difference occurs between a and 7b before and after the key signals 18a and 18b, the horizontal decoder 12a and the vertical decoder 12b correct which of the window key signals should be selected. Select signals 19a and 19b are output.

The video image data read timing generator 16 generates and outputs a timing signal for reading video image data from the video memory 3 in synchronization with the display switching signals 7a and 7b. The selector 4 selects and outputs PC digital image data and video image data based on the notation switching signals 7a and 7b.

In this embodiment, a circuit having such a chroma key combination is constructed. For example, when connecting various types of image sources to a personal computer, the timing of the personal computer and the timing of the video display position are automatically adjusted. Is adjusted. Therefore, there is no need for the user to adjust the display position many times while watching the display screen.

Although the above embodiment is one preferred embodiment of the present invention, the present invention is not limited to this embodiment, and various modifications can be made without departing from the gist of the present invention.

[0035]

As is clear from the above description, the image synthesizing circuit of the present invention determines whether or not a specific portion of the first image data has a predetermined coloring, and based on the determination, determines whether the first image data has a predetermined color. And outputs an image switching signal synchronized with the horizontal and vertical areas of the image. A second image data to be synthesized with the first image data is stored, and a phase difference between the image switching signal and a key signal for identifying an image synthesis position is detected in synchronization with the image switching signal. The phase correction is performed, and a timing signal for reading the second image data is output. Inputting first image data, second image data, and an image switching signal;
The second image data is combined with the first image data, and the combined image data is output.

Therefore, by the phase correction of the read timing of the second image, the image combining position of the first image data and the second image data is automatically adjusted. This automatic adjustment function supports a variety of external image source models such as a VTR, and eliminates the need for the user to adjust the timing of screen display on the personal computer side while repeatedly looking at the screen. Further, it is easy to cope with image display by chroma key synthesis in a system having a plurality of windows as well as the synthesis of two images of a video and a personal computer as in the conventional superimposition.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of an image composition circuit of the present invention.

FIG. 2 is a timing signal diagram illustrating a concept of determining a phase in the embodiment.

FIG. 3 is a diagram showing the concept of processing in the first conventional example.

FIG. 4 is a diagram showing a processing concept in a second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Comparator part 2 Readout timing signal generation part 3 Video memory (storage part) 4 Selector (image synthesis part) 7a, 7b Display switching signal 10 Color key register 11 Color key comparator 12 Decoder 13 Counter 14 Window register 16 Video image data reading Timing generator 18 Key signal 19 Selection signal

Continued on the front page (51) Int.Cl. ⁶ identification code FI H04N 9/75 H04N 9/75 (58) Fields investigated (Int.Cl. ⁶ , DB name) G09G 5/36 G09G 5/14 G09G 5 / 00 G09G 5/18 H04N 5/265 H04N 9/75

Claims (3)

(57) [Claims] 1. A method for determining whether or not a predetermined portion of a first image data has a predetermined coloring, and outputting an image switching signal synchronized with a horizontal direction and a vertical direction of the first image data based on the determination. a comparator means for the storage means for storing second image data to be image compositing the first image data, synchronized to the image switching signal, and the image switching signal and image
A read timing signal generating means for outputting combined position detects the phase difference between the key signal for identifying the phase correction line Utotomoni, a timing signal for reading the second image data, said first image data Image synthesizing means for inputting the second image data and the image switching signal, synthesizing the second image data with the first image data, and outputting the synthesized image data; By the phase correction, the first image data and the second
An image synthesizing circuit for automatically adjusting the image synthesizing position with the image data. 2. The read timing signal generating means includes: a window register for specifying an image synthesis position and a size for synthesizing the second image data with the first image data; It operates the dot clock and horizontal synchronizing signal for displaying the synchronization, the window Les
A counter for outputting a plurality of windows key signal by register, said plurality of windows by the window register key
And a decoder for selecting one of the key signals to generate the key signal, determining a phase difference between the image switching signal and the key signal, and complementing a window key signal to be selected by the decoder.
2. The image processing apparatus according to claim 1, further comprising: a phase determining unit that outputs a positive selection signal; and an image data read timing generating unit that receives the dot clock and the output signal of the counter and outputs the timing signal.
Image synthesis circuit as described. 3. The apparatus according to claim 1, wherein said window register, said counter, and said decoder are each composed of a pair for a horizontal direction and a pair for a vertical direction for displaying said composite image. Image synthesis circuit.