JP3038725B2 - Time base collector - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time base collector, and more particularly to a time base collector for performing a time axis correction process on a video signal of a magnetic recording / reproducing apparatus, a television receiver, or the like.

[Prior Art] Conventionally, a configuration shown in FIG. 2 has been known as a time base collector for performing a time axis correction process on a video signal.

As shown in FIG. 2, this time base collector
The configuration is such that the write address from the write address counter 24 and the read address from the read address counter 25 are supplied to the memory 22, respectively. The input signal (video signal) input to the input terminal 21 is input to the memory 22. The write address counter 24 operates with a clock synchronized with the input signal, and generates and outputs a write address of the input signal to the memory 22. The read address counter 25 operates with a reference clock without time axis error,
A read address for reading data written in the memory 22 is generated and output. Therefore, even if the video signal written to the memory 22 has a time axis error, the output of the memory 22 is output from the output terminal 23 as a signal without a time axis error.

[Problems to be Solved by the Invention] However, the conventional time base collector described above writes an input signal with a clock synchronized with the input signal and reads data with a clock having no time axis error. If the value of the write address counter overtakes or separates the value of the read address counter, the difference between the value of the write address counter and the value of the read address counter becomes unstable. There is a problem that correct data cannot be read.

The present invention has been made in view of such a problem, and can prevent the difference between the value of the write address counter and the value of the read address counter from becoming unstable, and always read the correct data from the memory. The aim is to provide a time base collector that enables

Means for Solving the Problems A time base collector according to the present invention operates with a clock synchronized with an input signal and outputs a write address, and a read address counter which operates with a reference clock and outputs a read address When,
A memory that stores the input signal according to the write address from the write address counter, and that outputs the stored input signal according to the read address from the read address counter, and a vertical blanking signal that inputs a reference synchronization signal and A synchronization signal generating circuit for outputting a composite synchronization signal in a vertical blanking period; a synchronization processing circuit for adding the composite synchronization signal to an output signal from the memory; and a vertical blanking period for inputting the vertical blanking signal And an address correction circuit for correcting the value of the read address counter so that the difference between the value of the write address counter and the value of the read address counter becomes constant each time.

[Operation] In the present invention, the synchronization signal generating circuit outputs the vertical blanking signal and the composite synchronization signal during the vertical blanking period of the input signal. Then, the synchronization processing circuit adds the composite synchronization signal to the output signal from the memory. For this reason,
There is no need to read data from the memory during the vertical blanking period.

The address correction circuit compares the value of the write address counter with the value of the read address counter every time this vertical blanking period occurs, and corrects the value of the read address counter so that the difference becomes a predetermined value. This prevents the values of the write address counter and the read address counter from becoming unstable.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a time base collector according to an embodiment of the present invention. As shown in FIG. 1, the write address from the write address counter 15 and the read address from the read address counter 16 are given to the memory 12, respectively. On the other hand, the reference synchronizing signal is input to the synchronizing signal generating circuit 18, whereby the vertical blanking signal and the composite synchronizing signal output from the synchronizing signal generating circuit 18 are respectively converted to the address correcting circuit 17 and the synchronizing processing circuit.
13 are supplied. The address correction circuit 17 is provided for correcting the difference between the values of the write address counter 15 and the read address counter 16, and the synchronization processing circuit 13 is provided for adding a composite synchronization signal to the output signal from the memory 12. ing.

Next, the operation of the time base collector will be described.

A video signal input to the memory 12 from the input terminal 11 is written to the memory 12 according to a write address generated by a write address counter 15 that operates with a clock synchronized with the video signal. Then, the video signal written in the memory 12 is read according to the read address generated by the read address counter 16 that operates with a reference clock having no time axis error.

On the other hand, the synchronization signal generation circuit 18 generates a vertical blanking signal and a composite synchronization signal for the vertical blanking period based on the reference synchronization signal input from the reference synchronization signal terminal 19, and performs address correction on the vertical blanking signal. In addition to the output to the circuit 17, the composite synchronization signal is output to the synchronization processing circuit 13. The synchronization processing circuit 13 adds the composite synchronization signal to the video signal read from the memory 12. Therefore, there is no need to read data from the memory 12 during the vertical blanking period.

Therefore, upon receiving the vertical blanking signal, the address correction circuit 17 uses the vertical blanking period to set the read address so that the difference between the value of the write address counter 15 and the value of the read address counter 16 becomes a predetermined value. The value of the counter 16 is corrected. As described above, since the value of the write address counter and the value of the read address counter are corrected during the vertical blanking period, no error in the time axis direction is accumulated for one or more fields.
This prevents the reading from overtaking the writing and prevents the output signal 14 from becoming unstable.

[Effect of the Invention] As described above, according to the present invention, the difference between the value of the write address counter and the value of the read address counter is corrected during the vertical blanking period of the video signal, and the difference is maintained at a constant value. Therefore, it is possible to prevent the value of the write address counter from overtaking or separating from the value of the read address counter. Also, since the composite synchronization signal is added to the output signal from the memory by the synchronization processing circuit, even if there is a pixel skip in the output signal of the memory, the synchronization between the input signal and the signal output from the synchronization processing circuit is maintained. Can be secured. Therefore, correct data can always be output, and a stable video signal can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a time base collector according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional time base collector. 11, 21; input terminal, 12, 22; memory, 13; synchronization processing circuit, 14,
23; output terminal, 15, 24; write address counter, 16, 2
5; read address counter, 17; address correction circuit, 1
8; sync signal generator, 19; reference sync signal terminal

Claims (1)

(57) [Claims] 1. A write address counter which operates at a clock synchronized with an input signal and outputs a write address, a read address counter which operates at a reference clock and outputs a read address, and said input signal according to a write address from said write address counter. And a memory that outputs the stored input signal in accordance with the read address from the read address counter, and a synchronization that inputs a reference synchronization signal and outputs a vertical blanking signal and a composite synchronization signal of a vertical blanking period. A signal generation circuit, a synchronization processing circuit for adding the composite synchronization signal to an output signal from the memory, and a value of the write address counter and the readout for each vertical blanking period during which the vertical blanking signal is input. Address counter Time base corrector the difference between the value and having an address correction circuit for correcting the value of the read address counter to be constant values.