JP3225809B2 - Variable speed playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable speed reproducing apparatus capable of performing variable speed reproduction using a memory, particularly non-integer multiple speed very close to normal reproduction and high quality reproduction without noise.

[0002]

2. Description of the Related Art Conventionally, various methods have been proposed for a variable speed reproduction method using a memory.
What is described in -80873 is known.
FIG. 10 shows the configuration, in which a reproduced video signal is converted into a digital value by an AD converter 4 and then taken into a field memory 5. On the other hand, the reproduction output level is discriminated by the level discrimination 24, and a digital value is taken into the field memory 5 when the reproduction output level is equal to or higher than a specific level. Field memory 5
Thereafter, the video signal is read out according to the readout clock of the output of the readout pulse generator 10, and after being added with the pseudo-synchronous signal, it is converted by the DA converter 6 into an analog video signal.

[0003]

However, the above-mentioned conventional variable speed reproduction system has a configuration corresponding to integer multiple speed reproduction, which is sufficiently faster than 1x speed, that is, so-called cue review reproduction. This is a method in which the contents of the memory are updated one after another in a state of noise feed reproduction without synchronization. Therefore, since the synchronizing signal in the reproduced video signal may be violated by noise, it is necessary to always generate a pseudo synchronizing signal and add it to the video signal. For this reason, a slight shift occurs between the input video signal and the synchronizing signal, which appears as jitter on the screen.

[0004] Further, since the fetching into the memory is permitted or prohibited based on the mere level discrimination result, for example,
When switching heads for playback in field units, such as non-integer multiple speed playback, the effects of the DC level difference of the head amplifier before and after switching can be directly affected, and the video part to be captured cannot be captured, making it noiseless. Disappears.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a variable speed reproducing apparatus capable of high-quality noiseless reproduction even at non-integer multiple speed reproduction.

[0006]

Means for Solving the Problems] variable speed reproducing apparatus of the present invention to achieve this object, the magnetic recording tape transport speed
For a predetermined period depending on the degree,
Freeze control to prohibit writing of video signal to memory
Means and a non-integer multiple speed n (0 <n <
(2) a running means for running the tape, a head switching means having two pairs of heads having different azimuth angles and selecting and switching at least two heads in field units, a rotation phase detection signal of a cylinder, and a reproduction control and a phase control means for controlling the phase difference between the signals, position
Phase control means, in order to increase the one of the reproduced output of the even field or the odd field when performing variable speed reproduction at the speed n, the phase difference based on the comparison result of the sampling values of a particular three points reproduction envelope Fix
And the freeze control means outputs to the output of the head switching means.
From the reproduction output corrected by the phase control means,
Writing of video signals in fields with small playback output is prohibited.
It is configured to stop .

[0007] Thus, a completely noiseless reproduced image can be obtained without any flickering of the screen such as line flicker or slight shaking of the screen even at non-integer multiple speed reproduction.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION
An AD converter for converting a video signal reproduced from a magnetic recording tape into a digital value, a memory in which the digital value is written, a memory control means for controlling writing and reading to and from the memory, and an output read from the memory A digital-to-analog converter that converts a video signal into an analog value, freeze control means that prohibits writing of a video signal of a field having a small reproduction output to a memory for a predetermined period according to a transfer speed of a magnetic recording tape, Non-integer multiple speed n
(0 <n <2), a running means for running the tape, two head pairs having different azimuth angles from each other, a head switching means for selecting and switching four heads in field units, and a rotational speed of the cylinder. comprising detecting the rotation phase signal of said cylinder to the same extent as when schematic recording and a phase control means for controlling the phase difference between the reproduced control signal, the position
The phase control means corrects the phase difference based on a comparison result of sampling values of three specific points of a reproduction envelope so as to increase a reproduction output of a specific field when performing the variable speed reproduction at the speed n, and performs the freeze control. The means is
The phase control means based on the output of the head switching means
From the playback output corrected by
This feature is characterized by prohibiting the writing of the video signal of the field, obtaining the tracking information from the playback envelope before demodulation, and correcting the phase reference of the capstan based on this to automatically determine the optimal The tracking state can be set, and the S / N ratio of the video signal of the field to be frozen can be sufficiently ensured. Therefore, even when the tracking state is not known, such as when a compatible tape is reproduced, the control can be performed to the optimum tracking position. Also, there is no need to add a pseudo vertical synchronizing signal, and noiseless reproduction can be realized with a simple configuration.

According to a second aspect of the present invention, there is provided an AD converter for converting a video signal reproduced from a magnetic recording tape into a digital value, a memory in which the digital value is written, and an output read from the memory into an analog value. A digital-to-analog converter, memory control means for controlling writing and reading to and from the memory, freeze control means for controlling write inhibition of the video signal of either the even field or the odd field, and A running means for running the tape at different non-integer multiple speeds n (0 <n <2), and two head pairs having different azimuth angles from each other;
A head switching means for selecting and switching at least two heads in a field unit; and a phase control means for controlling a phase difference between a rotation phase detection signal of the cylinder and a reproduction control signal. In order to increase the playback output of either the even field or the odd field, a specific 3
The phase difference is corrected based on a comparison result of sampling values of points, and in addition to the effect of claim 1, furthermore, the freeze control means controls either one of an even field or an odd field. By performing the write inhibition control of the video signal, only the reproduction output of the same azimuth can be made effective, and the line flicker peculiar to the field-frame reproduction can be eliminated. As a result, it is possible to obtain a high-quality reproduction output without screen flicker.

According to a third aspect of the present invention, the magnetic recording tape is caused to run at a speed n (0 <n <2) that is a non-integer multiple different from that at the time of recording, and the rotational speed of the cylinder is substantially equal to that at the time of recording. Phase control means for controlling a first phase difference between a reproduction control signal and a rotation phase detection signal of the cylinder, and phase difference detection means for detecting a second phase difference between the rotation phase detection signal and a vertical synchronization signal during normal reproduction Signal generating means for generating a pseudo vertical synchronizing signal having a different delay amount for each field based on the second phase difference; inserting means for inserting the pseudo vertical synchronizing signal into a reproduced video signal; A / D converter, a memory to which a digital value is written, a D / A converter to convert an output read from the memory into an analog value, and writing / reading to / from the memory Memory control means for performing control, and freeze control means for performing video signal write-inhibition control in field units. When performing variable-speed reproduction at a speed n, the reproduction envelope is specified in order to increase the reproduction output of a specific field. The first phase difference is corrected based on the comparison result of the sampling values of the three points. The tracking information is obtained from the reproduction envelope before demodulation, and the phase of the capstan is obtained based on the tracking information. By correcting the reference, the optimum tracking state can be automatically set, and the S / N ratio of the video signal of the field to be frozen can be sufficiently ensured. Therefore,
Even when the tracking state is not known, such as when a compatible tape is reproduced, the control can be performed to the optimum tracking position. Further, a second phase difference between the rotation phase detection signal and the vertical synchronization signal is detected by the phase difference detection means during normal reproduction,
Since the phase of the pseudo-vertical synchronization signal is determined based on the detection result, the phase of the vertical synchronization signal and the pseudo-vertical synchronization signal in the playback video signal must be accurately matched even when using a compatible tape other than the master tape. The use of the pseudo-synchronous signal makes it possible to eliminate the slight fluctuation of the screen. Further, by using the pseudo vertical synchronizing signal, stable synchronization can be performed even when there is a field where the SN ratio of the reproduced video signal is poor.

According to a fourth aspect of the present invention, there is provided an AD converter for converting a video signal reproduced from a magnetic recording tape into a digital value, a memory in which the digital value is written, and an output read from the memory as an analog value. A digital-to-analog converter, memory control means for controlling writing and reading to and from memory, and freeze control means for controlling writing of video signals on a field basis; Non-integer multiple speed n (0 <n <
In step 2), the rotation speed of the cylinder is set to approximately the same as that at the time of recording, and the freeze control means predictively uses the change rate of the detection output of the reproduction envelope signal and the comparison result between the detection output and the reference value. The present invention is characterized in that the write inhibition control of the video signal is performed, and the phase control unit of the capstan control system is not required, so that the configuration can be extremely simplified. Furthermore, by performing write prohibition control in a field unit by the freeze control means in a predictive manner, noiseless reproduction can be easily achieved at any double speed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a variable speed reproducing apparatus according to Embodiment 1 of the present invention. FIG.
Numeral 1 is a cylinder mounted with four double azimuth heads for reproducing a video signal from a magnetic recording tape, 2 is a head switching circuit for selecting one of the reproduced outputs of the four heads, and 3 is an FM for outputting the output of the cylinder head. A demodulator for demodulation, an AD converter for converting a demodulated video signal into a digital value, a field memory for taking in an AD-converted output, and a conversion of an output read from the field memory into an analog value. , A synchronizing separation circuit for separating a synchronizing signal from the demodulated video signal, 8 a pulse generator for generating a write pulse synchronized with an output signal of the synchronizing separation circuit, and 9 an output of the pulse generator 8. and,
A memory control means for writing and reading control to the field memory 5 by an output of a read-only pulse generator 10 different from the above, a detection circuit 11 for detecting a reproduction envelope before demodulation, and a detection circuit 12 An AD converter 11 converts a DC voltage of an output into a digital value, 13 is a timing generating means for generating a timing for sampling by the AD converter 12, and 14 is an error calculator for calculating a tracking error from a plurality of outputs after the AD conversion. Means 15, a multiplier for multiplying the error by an appropriate multiplication coefficient k, 16 is a cylinder control means for controlling the rotation of the cylinder 1 and generating various timing signals, and 17 is a memory control means based on an output signal of the cylinder control means 16. A freeze control means for outputting a write inhibit control command to the cylinder 9; A capstan control means for rotation of the capstan 19 by the output of the phase multipliers 16.

A description will be given of the variable speed reproducing apparatus configured as described above, taking 1.33 times the speed of the standard reproducing mode as an example.
FIG. 2 shows a signal waveform and a head trace of each part of the block in FIG. In FIG. 2, signals (waveforms) A and B are head switching signals for head switching, and the outputs of the four heads of the cylinder 1 are selected by a combination of the logic of the signals A and B.
According to FIG. 2, the heads are Ra, La, Ra, Rb, L
b, Rb (Rb and Lb are standard mode reproducing heads, R
a, La are heads for long-time mode reproduction)
Head switching is repeatedly performed in a pattern that forms one sequence in the field. The selected reproduction envelope output C is detected by the detection circuit 11 and D in FIG.
The waveform shown in FIG. Further, the sampling timing signal E output from the timing generation means 14 is supplied to the AD converter 12, and the detection voltage D is sampled at a point p in the first field, a point q in the second field, and an r point in the third field. When the head is moved in the direction in which the phase is advanced in FIG. 2 (rightward in the figure), the area to be traced at the point p increases, and conversely, the area at the point r decreases. When the phase is delayed, the area to be traced at the point p decreases, and conversely, the area at the point r increases. Here, the reason why the detection voltage D is sampled at three points is to determine the current tracking state. For example, if the voltage at the point q is lower than the voltage at the points p and r, the tracking deviation amount becomes almost maximum. It can be seen that when the voltage at the point q is higher than the voltage at the points p and r, the tracking shift amount is small.

The error calculating means 14 takes in the sampling values at the points p, q and r, and after the above-mentioned state discrimination, when the tracking deviation amount is large, data corresponding to the maximum acceleration / deceleration is obtained. When the tracking error is small, the difference between the sampling value at the point p and the sampling value at the point r is calculated. In the multiplier 15, a constant k sufficiently smaller than 1 is output to the output of the error calculating means 14.
(K≪1), and the multiplication result corrects the reference phase of the capstan control means 18. The corrective action is p
The operation is performed until the voltages at the points r and r become substantially equal. When the voltages become equal, the tracking state becomes an optimum state as shown in FIG. 3, so that the output of the multiplier 15 becomes zero and the correction operation is completed.

FIG. 3 shows the phase control timing of the capstan 19, wherein A and B are head switching signals, G is a phase reference signal in normal reproduction synchronized with the signal A, and H is a 1.33x speed signal. A phase reference signal, J is a cylinder phase reference signal, and I is a control signal at 1.33 times speed. The capstan control means 18 controls the phase by inputting the control signal I and the reference phase J supplied from the cylinder control means 16 as in the case of the normal reproduction. On the other hand, since the capstan 19 feeds the tape at 1.33 times speed, the reference phase J and the cycle of the control signal I are different. Therefore, based on the phase reference G of the capstan at 1 × speed which is originally synchronized with the reference phase J, a new reference phase H for 1.33 × speed is provided in synchronization therewith, so that non-integer double speed playback is possible. Perform phase control.

The reference value in the reference phase H is set at a target time to which the control signal I is to be input. When a control is performed using a processor, a time base counter (see FIG. Not shown)
The reference value is successively determined based on the count value. First, the reference a can be set by using a 1 × speed reference, and the next reference b can be obtained by obtaining a time equivalent to one cycle of 1.33 × speed from the reference a. Further, the next criterion c is set by obtaining the time for one cycle from the criterion b. The next standard d is also the standard c.
Set from. The next criterion is again the 1x speed criterion a.
Is used. By repeating this, the phase reference H for the non-integer multiple speed can be created.

The capstan control means 18 compares the phase of the non-integer multiple speed phase reference H with the control signal I, and performs a control operation so that the control signal I comes to the center of the slope section of the phase reference H. Is done. On the other hand, in FIG.
M demodulation is performed, and the output is supplied to the AD converter 4. A
While the D-converted output is supplied to the field memory, a synchronization signal is separated from the demodulated signal, and a pulse synchronized in phase with the separated synchronization signal is supplied from the pulse generator 8 to the memory control means 9. .

The freeze control means 17 is supplied with head switching signals A and B from the cylinder control means 16, and outputs a freeze control signal F based on these two signals. The freeze control signal F is supplied to the memory control means 9, and the pulse supplied from the pulse generator 8 is inhibited while the signal F is at the “H” level. As a result, the video signal is stored in the field memory 5. Not written. On the other hand, a read pulse asynchronous with the write pulse is supplied from the pulse generator 10 to the memory control means 9, and the read control is performed on the field memory 5. The read output is output by the DA converter 6.
It is converted to an analog video signal. Therefore, as the finally output video signal, the output of the second field is frozen and the same video signal is output continuously for three field periods, and the output of the fifth field is frozen and output for three consecutive field periods. Will be output. As a result, the image is thinned out, but the level of appearance is almost uncomfortable, and there is no problem in practical use.

Next, a description will be given of an example of 0.75 times speed of the standard reproduction mode. FIG. 4 shows a signal waveform and a head trace of each part of the block in FIG. In FIG. 4, A
And B are head switching signals for head switching, and the outputs of the four heads of the cylinder 1 are selected by a combination of the logic of the signals A and B. FIG.
According to, the heads are Ra, La, Ra, La, Lb, R
The heads are repeatedly switched in the pattern of b, Lb, and Rb (Rb and Lb are standard mode reproducing heads, and Ra and La are long-time mode reproducing heads) in an order of one field in eight fields. The selected reproduction envelope output C is detected by the detection circuit 11 and
The waveform shown in D of FIG. Further, the sampling timing signal E output from the timing generation means 14 is supplied to the AD converter 12, and the p-point and the second
The detection voltage D is sampled at the point q in the field and at the point r in the fourth field. When the head is moved in the direction in which the phase is advanced in FIG. 4 (to the right in the figure), the area to be traced at the point p decreases, and conversely, the area at the point r increases. When the phase is delayed, the area to be traced at the point p increases, and conversely, the area at the point r decreases.
Here, the detection voltage D is sampled at three points.
This is for determining the current tracking state. For example, if the voltage at the point q is lower than the voltage at the points p and r, it can be understood that the tracking deviation amount is almost maximum, and the voltage at the point q is at the point p or If the voltage is higher than the voltage at the point r, it can be seen that the tracking deviation amount is small.

The error calculating means 14 takes in the sampling values at the points p, q, and r, and after the above-mentioned state discrimination, when the tracking deviation amount is large, data corresponding to the maximum acceleration / deceleration is obtained. When the tracking error is small, the difference between the sampling value at the point p and the sampling value at the point r is calculated. In the multiplier 15, a constant k sufficiently smaller than 1 is output to the output of the error calculating means 14.
And the capstan control means 1
Eight reference phases are modified. The correction operation is performed until the voltages at the points p and r become substantially equal, and when the voltages become equal, the tracking state becomes an optimal state as shown in FIG.
The output of the multiplier 15 becomes zero, and the correcting operation is completed.

FIG. 5 shows the capstan 1 at 0.75 × speed reproduction.
9 is a phase control timing, A and B are head switching signals, G is a phase reference signal for normal reproduction synchronized with the signal A, H is a phase reference signal for 0.75 times speed, and I is
A control signal at 0.75 times speed, J is a cylinder phase reference signal. The capstan control means 18 controls the phase by inputting the control signal I and the reference phase J supplied from the cylinder control means 16 as in the case of the normal reproduction. On the other hand, since the capstan 19 feeds the tape at 0.75 times speed, the reference phase J and the cycle of the control signal I are different. Then, based on the phase reference G of the capstan at 1 × speed which is originally synchronized with the reference phase J, a new reference phase H for 0.75 × speed synchronized with this is provided, so that non-integer double speed reproduction is performed. Perform phase control.

The reference value in the reference phase H is set at the target time at which the control signal I is to be input. As in the case of the 1.33 × speed, the reference a uses the 1 × speed reference. b can be set by obtaining a time equivalent to one cycle of 0.75 times speed from the reference a. Further, for the next criterion c, the time is set for one cycle from the criterion b.
As the next reference, the reference a at 1 × speed is used again. By repeating this, a phase reference for non-integer multiple speed can be created.

The capstan control means 18 compares the phase of the non-integer multiple-speed phase reference H with the control signal I, and performs a control operation so that the control signal I comes to the center of the slope section of the phase reference H. Is done. On the other hand, in FIG. 1, the reproduction envelope signal C is FM-demodulated by the demodulator 3, and the output is supplied to the AD converter 4.
The AD-converted output is supplied to the field memory, while the synchronization signal is separated from the demodulated signal, and a pulse synchronized with the separated synchronization signal is supplied from the pulse generator 8 to the memory control means 9. .

The freeze control means 17 is supplied with head switching signals A and B from the cylinder control means 16, and outputs a freeze control signal F based on these two signals. The freeze control signal F is supplied to the memory control means 9, and the pulse supplied from the pulse generator 8 is inhibited while the signal F is at the “H” level. As a result, the video signal is stored in the field memory 5. Not written. On the other hand, a read pulse asynchronous with the write pulse is supplied from the pulse generator 10 to the memory control means 9, and the read control is performed on the field memory 5. The read output is output by the DA converter 6.
It is converted to an analog video signal. Therefore, as a video signal to be finally output, the output of the third field is frozen and the output of the third field is frozen.
The same video signal is continuously output in the field, the output in the sixth field is kept as it is, the output in the seventh field is frozen, and the same video signal is output continuously for three fields. As a result, the image is thinned out, but the level of appearance is almost uncomfortable, and there is no problem in practical use.

(Embodiment 2) FIG. 6 is a block diagram showing a variable speed reproducing apparatus according to Embodiment 2 of the present invention. In FIG. 6, a chroma rotation signal J is supplied to the memory control means 9 from the cylinder control means 16. The variable speed playback device configured as described above will be described by taking 1.33 times the speed of the standard playback mode as an example. FIG. 2 shows the signal waveforms of the respective blocks in FIG. 6 as in the first embodiment.

Although omitted in FIG. 1, the chroma rotation signal J is conventionally supplied from the cylinder control means 16 to the demodulator 3 in order to perform rotary control of chroma. With this signal, an even field and an odd field can be distinguished. By using this for the freeze control of the field memory 5, the configuration can be simplified. For example, as shown in FIG. 2, when freezing fields (second and fifth fields) reproduced in L azimuth, the chroma rotation signal J is output as a freeze control signal F as it is. The freeze control signal F is supplied to the memory control means 9, and the pulse supplied from the pulse generator 8 is prohibited while the freeze control signal F is at the “H” level. No signal is written. On the other hand, a read pulse asynchronous with the write pulse is supplied from the pulse generator 10 to the memory control means 9, and the read control is performed on the field memory 5. The read output is converted by the DA converter 6 into an analog video signal. Therefore, as the finally output video signal, the output of the second field is frozen and the same video signal is continuously output for three fields, and the fifth video signal is output.
The output of the field is frozen and output is made for three consecutive fields. As a result, the image is thinned out, but the level of appearance is almost uncomfortable, and there is no problem in practical use.

Next, a description will be given of an example of 0.75 times speed of the standard reproduction mode. FIG. 7 shows a signal waveform and a head trace of each part of the block in FIG. In FIG. 7, the heads are Ra, La, Ra, La, Lb, Rb, Lb, R
b (Rb and Lb are standard mode reproducing heads, Ra and La
Is a long-time mode reproducing head), and head switching is repeatedly performed in a pattern of one sequence in eight fields. The selected reproduction envelope output C is detected by the detection circuit 11, and the waveform shown in FIG. 7D is obtained. Further, the sampling timing signal E output from the timing generation means 14 is supplied to the AD converter 12, and the p-point of the first field, the second field q
The detection voltage D is sampled at the point r in the third field.

The three sampling points are selected such that the reproduction output of the field in which the video signal is frozen is sufficiently large. FIG. 7 shows a case where the reproduction output of the second field, the fifth field, and the seventh field is increased. On the other hand, in FIG. 6, the reproduction envelope signal is FM-demodulated by the demodulator 3 and its output is
It is supplied to the converter 4. While the AD-converted output is supplied to the field memory 5, the synchronization signal is separated from the demodulated signal, and the pulse synchronized with the separated synchronization signal is supplied from the pulse generator 8 to the memory control unit 9. You.

A chroma rotation signal J is supplied from the cylinder control means 16, and this signal is output as a freeze control signal F. The freeze control signal F is supplied to the memory control means 9, and the pulse supplied from the pulse generator 8 is prohibited while the freeze control signal F is at the “H” level. Video signal is not written. On the other hand, a read pulse asynchronous with the write pulse is supplied from the pulse generator 10 to the memory control means 9, and the read control is performed on the field memory 5. The read output is converted by the DA converter 6 into an analog video signal. Therefore, as the finally output video signal, the output of the second field is frozen and the same video signal is continuously output for three fields, and the output of the fifth field is frozen and continuously output for two fields. As a result, the same video signal is output, and the output of the seventh field is frozen, so that the same video signal is output continuously for three fields. Therefore, by performing freeze control using the chroma rotation signal, only a video signal reproduced in L azimuth can be output as a reproduction output.

Although FIG. 7 shows a configuration in which the reproduction output of L azimuth is made effective, the sampling points of the reproduction envelope D are set to the second field, the third field, and the fourth field, and the freeze control signal F is used for the chroma rotation. By making the signal inverted, it is possible to make the reproduction output in R azimuth effective. As a result, the image is thinned out, but the level of appearance is almost uncomfortable, and there is no problem in practical use.

(Embodiment 3) FIG. 8 is a block diagram showing a variable speed reproducing apparatus according to the present invention. 8, reference numeral 20 denotes a sync separation circuit for separating a vertical sync signal from a video signal after FM demodulation, 21 denotes a phase difference detecting means for detecting a phase difference between the vertical sync signal and the head switching signal A, 22
Is a pseudo synchronizing signal generating means for generating a pseudo synchronizing signal at the time of non-integer multiple speed reproduction, and 23 is an inserting means for mixing the pseudo synchronizing signal into the video signal. Phase difference detection means 2
Reference numeral 1 denotes an interrupt circuit that is interrupted at the edge of an input signal, an input capture register that stores the time when the interrupt was generated as a count value, and first and second memories that store the count value. I have.

The variable speed playback apparatus having the above-described configuration will be described by taking 1.33 times the speed of the standard playback mode as an example.
First, when normal reproduction is performed, the phase difference between the vertical synchronization signal and the head switching signal A is detected by the phase difference detection means 21. When the head switching signal A is input, an interrupt occurs at the rising edge, and the time at that time is stored in the input capture register as a counter value. The stored value is read out and moved to the first memory. Next, the rising edge of the vertical sync signal is input,
The interrupt is again applied, and the time at that time is stored in the input capture register as a counter value. The stored value is read out and moved to the second memory. When the counter is a down counter, the value of the second memory is subtracted from the value of the first memory, and the phase difference between the two signals is calculated. The calculation result is sent to the pseudo synchronization signal generating means 22 as reference phase data. The pseudo synchronizing signal generator 22 calculates phase data in each of the six fields based on the reference phase.

When the reference phase in normal reproduction (the phase of the head switching signal A and the vertical synchronization signal) is 6.5H (H is the cycle of one horizontal synchronization), the first to sixth fields at 1.33 times speed are used. The reference phase is 4.5H, 5H, 5.5 respectively
H, 6.5H, 7H, and 7.5H. For example, if the detection value of the phase difference detection means 21 is 7H, the first field to the sixth field
The phases up to the field are 5H, 5.5H, 6H, 7H, 7.
It is understood that 5H and 8H should be set.

In the pseudo synchronizing signal generating means 22, first, the input reference phase data is taken into the first memory.
Next, data corresponding to 6.5H is subtracted from the first memory.
At this point, the offset value from 6.5H is stored in the first memory. Then, corresponding to each field, for example, in the case of the first field, data corresponding to 4.5H is added to the first memory, and the phase of the vertical synchronization signal at 1.33 times speed is calculated.

Thereafter, the pseudo vertical synchronizing signal K calculated for each field is output. A clock is supplied to the pseudo synchronizing signal generating means 22 from the synchronizing separation circuit 7, and the output timing of the pseudo vertical synchronizing signal K is normalized by this clock. Therefore, the pseudo synchronizing signal K can be generated at an accurate timing. The pseudo synchronizing signal K is supplied to the inserting means 23, and the original signal of the vertical synchronizing signal in the video signal after the FM demodulation is replaced with the pseudo synchronizing signal K. Therefore, a stable video output can be obtained without the vertical synchronization signal being corrupted by noise in any tracking state.

Next, a description will be given of an example of 0.75 times speed of the standard reproduction mode. The pseudo synchronizing signal generating means 22 calculates phase data for each of the eight fields based on the reference phase. When the reference phase in the normal reproduction is 6.5H, the phases from the first field to the eighth field at 0.75 × speed are 4.5H, 4.125H, 3.75H, 3.375H, 3.375H, 6.5H, 6.125H,
5.75H and 5.375H, for example, if the detection value of the phase difference detecting means 21 is 7H, the phases from the first field to the sixth field are 5H, 5.625H, 4.25H, and 3.875, respectively.
It can be seen that H, 7H, 6.625H, 6.25H, and 5.875H should be set.

In the pseudo synchronizing signal generating means 22, first, the input reference phase data is taken into the first memory.
Next, data corresponding to 6.5H is subtracted from the first memory.
At this point, the offset value from 6.5H is stored in the first memory. Then, corresponding to each field, for example, in the case of the first field, data corresponding to 4.5H is added to the first memory, and the phase of the vertical synchronizing signal at 0.75 times speed is calculated.

Thereafter, the pseudo vertical synchronizing signal K calculated for each field is output. A clock is supplied to the pseudo synchronizing signal generating means 22 from the synchronizing separation circuit 7, and the output timing of the pseudo vertical synchronizing signal K is normalized by this clock. Therefore, the pseudo synchronizing signal K can be generated at an accurate timing. The pseudo synchronizing signal K is supplied to the inserting means 23, and the original signal of the vertical synchronizing signal in the video signal after the FM demodulation is replaced with the pseudo synchronizing signal K. Therefore, a stable video output can be obtained without the vertical synchronization signal being corrupted by noise in any tracking state.

(Embodiment 4) FIG. 9 is a block diagram showing a variable speed reproducing apparatus according to Embodiment 4 of the present invention. In FIG. 9, 13 is a timing generating means for generating a sampling timing at a fixed period, 24 is a change rate calculating means for calculating a change rate of the detection output D of the reproduction envelope, and 25 is a comparator for comparing the detection output D with a reference value. The comparing means 26 for outputting the result is a judging means for judging the freeze timing from the detection output D and the comparison result.

No control signal is input to the capstan control means 18 in FIG. Accordingly, the capstan control circuit 18 does not perform the phase control, and does not perform the synchronous control of the cylinder 1 and the capstan 19. The capstan control circuit 18 simply controls the speed based on the speed command and the speed detection signal, and controls only the tape feed speed. At this time, the waveform of the reproduction envelope signal C changes every moment without being synchronized with the head switching signal A.

The timing generating means 13 generates a sampling pulse E at every predetermined time t from the edge of the head switching signal A. For example, if the broadcast system of the reproduced video signal is the NTSC system, the period of the head switching signal A is about 33 ms, so that the fixed time t is 3.3 ms intervals if ten points are sampled. When the broadcasting system is the PAL system, the cycle of the head switching signal A is 4
Since it is 0 ms, if 10 points are sampled, 4
ms interval. The sampling pulse E is supplied to the AD converter 12 at this timing, and the detection output D of the reproduced video signal before demodulation is sampled. The sampled data is sent to the change rate calculating means 24 and the comparing means 2
5 is supplied. The rate-of-change calculating means 24 has two consecutive
Sampling data s and t of the point are supplied, and a difference value u between s and t is calculated. For example, if the difference value u is negative, it can be seen that the reproduced envelope waveform at the present time has a rising tendency and the envelope output is in a direction of increasing. If the difference value u is positive, it can be seen that the reproduced envelope waveform at the present time has a downward trend, and the envelope output is in the direction of decreasing. Also, if the difference value u is close to zero, it can be understood that the reproduced envelope waveform at the present time is almost at the maximum. These three states are output to the next determination means 26. Note that the sampling data is also supplied from the AD converter 12 to the comparing means 25. Comparison means 25
Then, successive comparisons between sampling data input one after another and a reference value are performed. As the reference value, for example, a value that is a half of the maximum value of the reproduction output is set by the user. As a result of the comparison, an “H” level signal is output to the determination means 26 only when the input data exceeds the reference value. The determination means 26 determines from both the input of the result of the change rate calculation means 24 and the input of the output of the comparison means 25, and sends a freeze control signal to the freeze control means 17. While the output of the comparing means 25 is at the "L" level, an "L" level signal is unconditionally output from the discriminating means.
Is not supplied with a write pulse. As a result, no video signal is taken into the field memory 5. When the difference value u is positive and abnormally large even when the output of the comparing means 25 is at the “H” level, the signal of the “L” level is output from the discriminating means, and the field memory 5 Video signal is not captured. When the output of the comparison means 25 is at the “H” level and the difference value u is other than the above, a signal of the “H” level is output from the determination means, a write pulse is supplied to the memory control means 9 and the field memory 5 is Video signals are captured.

The tape speed at this time is set to 17/1 in order to minimize the freeze period.
It is needless to say that a non-integer multiple speed such as double speed is preferable, and that if the denominator is increased, the number of fields in one sequence can be increased.

[0043]

As described above, the first aspect of the present invention obtains tracking information from the reproduction envelope before demodulation, and corrects the phase reference of the capstan based on the tracking information to automatically obtain the optimum tracking state. And the S / N ratio of the video signal of the field to be frozen can be sufficiently ensured. Therefore, even when the tracking state is not known, such as during reproduction of a compatible tape, control can be performed to the optimum tracking position. Also, there is no need to add a pseudo vertical synchronizing signal, and noiseless reproduction can be realized with a simple configuration.

According to the second aspect of the present invention, the freeze control is performed by the existing chroma rotation signal, and the video signal of only the field of the specific azimuth is made effective. it can. There is no need to create a more complicated freeze control signal, and the configuration is simplified.

According to the third aspect of the present invention, a stable video can be obtained without loss of synchronization even when the tracking state is poor, by inserting a pseudo vertical synchronization signal into the video signal of the original signal. It is possible to prevent the occurrence of synchronization disorder or the like. Furthermore, the number of freezes of an image can be reduced, and unnatural motion remains even in a panned video.

According to the fourth aspect of the present invention, the image quality and the number of freezes, which are in a trade-off relationship with each other, can be arbitrarily set by changing the reference value of the comparison means by the user. In addition, the phase control of the capstan is unnecessary, and the configuration of the control system is extremely simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a variable speed playback device according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each unit at 1.33 speed reproduction of the same device.

FIG. 3 is a timing chart of phase control in 1.33 × speed reproduction of the apparatus.

FIG. 4 is a signal waveform diagram of each unit at 0.75 × speed reproduction of the apparatus.

FIG. 5 is a phase control timing chart of the apparatus at 0.75 × speed reproduction.

FIG. 6 is a block diagram of a variable-speed playback device according to a second embodiment of the present invention.

FIG. 7 is a signal waveform diagram of each part at 0.75 × speed reproduction of the same device.

FIG. 8 is a block diagram of a variable-speed playback device according to a third embodiment of the present invention.

FIG. 9 is a block diagram of a variable speed playback device according to a fourth embodiment of the present invention.

FIG. 10 is a block diagram of a conventional variable speed playback device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 13 Timing generation means 14 Error calculation means 15 Multiplier 17 Freeze control means 20 Synchronization separation circuit 21 Phase difference detection means 22 Pseudo synchronization signal generation means 23 Insertion means 24 Change rate calculation means 25 Comparison means 26 Judgment means

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor ▲ Yoshi ▼ Akira 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-4-67456 (JP, A) JP-A-59-117381 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5 / 782-5/783 G11B 5/027 G11B 15/467 H04N 5/91-5/956

Claims (4)

(57) [Claims] An A / D converter that converts a video signal reproduced from a magnetic recording tape into a digital value; a memory in which the digital value is written; a memory control unit that controls writing and reading to and from the memory; freeze prohibiting the DA converter for converting the output read from the memory into an analog value, a predetermined time period in accordance with the transport speed of the magnetic recording tape, writing to the memory of the video signal of a small field of reproduction output Control means; running means for running the tape at a speed n (0 <n <2) which is a non-integer multiple different from the time of recording; and two sets of head pairs having different azimuth angles from each other. A head switching means for selecting and switching the head, the rotational speed of the cylinder being substantially equal to that at the time of recording, and a rotational phase detection signal of the cylinder And a phase control means for controlling the phase difference between the raw control signal, the phase control unit, in order to increase the reproduced output of a particular field when performing variable speed reproduction at the speed n, the particular three points reproduction envelope The freeze control means corrects the phase difference based on the comparison result of the sampling values of
The reproduction output corrected by the phase control means based on the force
Writing a video signal in a field with a small playback output
Variable-speed playback device characterized in that the playback is prohibited . 2. An A / D converter for converting a video signal reproduced from a magnetic recording tape into a digital value, a memory in which the digital value is written, and a D / A converter for converting an output read from the memory into an analog value. A memory control means for controlling writing and reading to and from the memory; a freeze control means for controlling writing inhibition of a video signal of either one of the even field and the odd field; Running means for running the tape at an integer multiple of speed n (0 <n <2); head switching means for selecting and switching at least two heads in field units having two pairs of heads having mutually different azimuth angles And phase control means for controlling a phase difference between the cylinder rotation phase detection signal and the reproduction control signal. When performing variable speed reproduction at a speed n, the phase difference is corrected based on a comparison result of sampling values of three specific points of the reproduction envelope so as to increase the reproduction output of either the even field or the odd field. Variable speed playback device. 3. A magnetic recording tape is run at a speed n (0 <n <2) which is a non-integer multiple different from that at the time of recording, and the rotational speed of the cylinder is substantially equal to that at the time of recording. With the rotation phase detection signal
Phase control means for controlling a phase difference; phase difference detection means for detecting a second phase difference between the rotation phase detection signal and the vertical synchronization signal during normal reproduction; and a delay amount for each field based on the second phase difference. Signal generating means for generating a different pseudo-vertical synchronization signal; insertion means for inserting the pseudo-vertical synchronization signal into the reproduced video signal; an AD converter for converting an output of the insertion means into a digital value; A memory to be written, a DA converter that converts an output read from the memory into an analog value, a memory control unit that performs writing and reading control to the memory, and a write inhibition control of a video signal in a field unit Freeze control means for performing variable-speed playback at the speed n so as to increase the playback output of a specific field. Variable speed reproduction apparatus, wherein the first phase difference based on the comparison result of the sampling values of a particular three ropes are modified. 4. An A / D converter for converting a video signal reproduced from a magnetic recording tape into a digital value, a memory in which the digital value is written, and a D / A converter for converting an output read from the memory into an analog value. , A memory control means for controlling writing and reading to and from the memory, and a freeze control means for controlling writing inhibition of a video signal on a field basis. Speed n
(0 <n <2), the rotation speed of the cylinder is set to be substantially the same as that at the time of recording, and the freeze control is performed based on the change rate of the detection output of the reproduction envelope signal and the comparison result between the detection output and a reference value. A variable-speed reproducing apparatus for predictively performing write-inhibition control of the video signal by means.