JP3230537B2 - Video recording device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video recording apparatus, and more particularly to a video recording apparatus capable of high-speed recording. 2. Description of the Related Art FIG. 8 shows a configuration example of a conventional video recording and reproducing apparatus such as a still picture camera. In FIG. 8, an image signal obtained from the CCD imager 51 is subjected to predetermined imaging processing by an imaging circuit 52 to obtain image data. The obtained image data is recorded on a recording medium 54 such as a semiconductor memory through the operation of the recording circuit 53. The image data read from the recording medium 54 is subjected to predetermined reproduction processing in a reproduction circuit 55, and a reproduced video signal is output. The operation timing of the CCD imager 51, the imaging circuit 52, and the reproduction circuit 55 is controlled by a synchronization signal generated from a synchronization signal generation circuit 56. The operation timing of the apparatus shown in FIG. 8 will be described with reference to FIG. 9. The period in which the electronic shutter pulse of the CCD imager 51 exists corresponds to the exposure period, and electric charges are accumulated in the photodiode of the CCD during this period. After the charges are held, the stored charges are read out at a predetermined timing. The reading of the stored charge is performed by the vertical synchronization signal V
This is performed at the timing of the even field signal and the odd field signal that occur alternately in synchronization with D. The recording in FIG. 9 shows the field data recording, and is designed so that a CCD output signal is obtained as a video signal from a CCD imager by an odd field signal at the time of arrival of the second vertical synchronization signal in FIG. It is an example. Then, data corresponding to the effective pixels of the CCD output video signal is obtained by the frame memory write gate. When the field-recorded data is reproduced as interlaced data of a frame, an interpolation process is performed as shown in FIG. FIG. 9A shows a case where the recording data is odd field data as shown in FIG. 9, and in order to obtain the frame data, the odd field data A read from the recording medium is obtained.
Even field data indicated by a dotted line is interpolated by using, for example, averaging processing using 1, A2, and A3. The interpolation data is (A1 + A2) / 2 using A1 and A2, and A2 and A
3 and (A2 + A3) / 2. When the timing is designed so that the recording data is an even field, B0, B1, B2,
Using B3, odd-numbered field data (B0 + B1) / 2, (B1 + B2) /
2, (B2 + B3) / 2 is obtained by interpolation. In this case, the data will start from the H / 2 part. FIG. 11 is a block diagram showing a configuration of a reproducing unit of a still image camera for performing an analog recording process. Recording medium 61
Has field data recorded thereon, and the field data read from the recording medium 61 is stored in a demodulation unit 62.
After being demodulated by the A / D converter 63 and converted into a digital signal by the A / D converter 63, the signal is delayed by 1H in the 1H delay unit (1HDL) 64. The interpolation data creation unit 65 creates interpolation data by the averaging process using the output from the A / D converter 63 and the output from the 1H delay unit 64. On the other hand, since it is necessary to determine whether the field data read from the recording medium 61 is even field data or odd field data, the field data is determined based on the vertical synchronization signal VD separated from the recording data. That is, the synchronization separation unit 68
The vertical synchronization signal is separated from the image data read from the recording medium 61, and the field determination unit 69 determines a field from the separated vertical synchronization signal. The reproduction field selection unit 70 receives the field index signal sent from the SSG unit 75, determines whether the field data to be reproduced is even field data or odd field data,
The changeover switch 71 is controlled to be switched based on the field discrimination result obtained from the field discrimination section 69 to determine whether the field is for reproducing the interpolation data from the interpolation data creation section 65 or the field for reproducing the output data from the 1H delay section 64. select. The color difference data from the A / D converter 63 is subjected to a synchronization process by a color difference synchronization unit 66 and modulated by a modulation unit 67. The Y / C mixing section 72 mixes the Y data from the changeover switch 71 and the color difference data from the modulation section 67 and outputs the result to the D / A converter 73. The signal converted into an analog signal by the D / A converter 73 is output to the synchronization mixing unit 74 by the synchronization signal S supplied from the SSG unit 75.
Mixed with YNC to get video output. [0007] The conventional video recording apparatus as described above, when recording video signals by thinning them out, for example, when performing field recording as shown in FIG.
After the electronic shutter is released, in the even field by the vertical synchronization signal VD arriving immediately after, the CCD output is always obtained in the odd field, so that no reading is performed, and the charge holding period extends over one field or more.
There is a time lag between when the electronic shutter is released and when image data is obtained , and high-speed recording cannot be performed.
There is a problem. This is a problem that occurs when a semiconductor memory is used as a recording medium.
As shown in FIG. 11, the write area of the semiconductor memory is defined, and the vertical synchronization signal is not recorded in the hatched portion serving as the vertical synchronization portion. Therefore, the read image data does not include the vertical synchronization signal. This is because, unlike the example of the analog recording process, it is not possible to determine whether the image data is an even field or an odd field, and thus it is necessary to determine a field of data output from the CCD when recording in advance. To record at high speed, reduce the video signal
Selected the line signal and the electronic shutter was released
Later, the timing immediately after the immediately following vertical synchronization signal VD
Should be recorded in a log. However, thinning out the video signal
When the signal of the specified line is selected by
The vertical sync signal is generated between the signal and the signals on the other lines.
Because the timing at which the video signal is obtained from the raw
The video signal to be obtained is also different. Therefore, the present invention solves the above-mentioned problems and provides an imaging method.
Select the signal of the specified line by thinning out the imaged video signal
In this case, the obtained video signal is
High-speed recording regardless of the difference from other line signals
The purpose is to provide a video recording device capable of recording.
You. [0009] [Means for Solving the Problems] To solve the above problems, a video recording apparatus according to the present invention, the captured image signal
First step for selecting a signal of a predetermined line by thinning out
And a signal of a predetermined line is selected by the first means and the first means.
When the signal of the predetermined line and the signal of the other line
The image excluding the difference part of the video signal caused by the difference
The image signal is recorded on the recording medium at the timing immediately after the vertical synchronization signal.
Be characterized by comprising a second means for recording the
You. According to the present invention, the image signal is thinned out and the
When the signal of the specified line is selected, the signal of the specified line
Caused by the difference between the signals on the other lines
The video signal excluding the difference part of the signal is
By recording on the recording medium at the timing immediately after,
High-speed recording is possible. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of a video recording apparatus according to the present invention. An image signal from the CCD imager 1 is subjected to a predetermined imaging process in an imaging circuit 2, converted into a Y signal and a color difference line-sequential signal, and further converted into digital signals by A / D converters 3 and 4, respectively. The Y signal digital data from the A / D converter 3 is recorded in the field memory 5, and the color-difference line-sequential signal digital data from the A / D converter 4 is subjected to synchronization processing by the synchronization unit 6 and recorded in the field memory 7. You. The control of writing to the field memories 5 and 7 is performed by a control signal from the memory control unit 8 through processing described later. According to the present embodiment, it is possible to write without discriminating even fields and odd fields, so that it is not necessary to limit the fields of the CCD output during recording to either the even fields or the odd fields.
Time lag during recording can be minimized. FIG. 2 is a block diagram showing an embodiment of a video reproducing apparatus according to the present invention. Field memory 5
The Y signal and the color-difference line-sequential signal are read out from the memory control unit 8 in the control mode described later. The image data read from the field memory 5 is 1H
The signal is supplied to the delay unit 9, delayed by 1H, and output to the interpolation data creation unit 10. The interpolation data generator 10 obtains interpolation data from the image data read from the field memory 5 and the 1H delay data from the 1H delay unit 9 by, for example, an averaging process. On the other hand, the color difference line-sequential signal read from the field memory 7 is modulated by the modulator 12 and output. The changeover switch 11 selects and outputs the interpolation data from the interpolation data creation unit 10 and the delayed video data from the 1H delay unit 9 for each field by a field index signal. The selection by the field index is performed in such a manner that the video data is reproduced according to a predetermined specification such that the video data is output in an odd field and the interpolation data is output in an even field because the field distinction is deleted at the time of recording. The Y data from the changeover switch 11 and the color-difference line-sequential data from the modulator 12 are Y
The signal is mixed by the C mixing unit 13 to obtain an NTSC signal.
The obtained NTSC signal is converted into an analog signal by the D / A converter 14 and then mixed by the synchronization mixing unit 15 to be output as a video signal. According to this embodiment, the field memories 5 and 7 store even fields,
Since data is recorded in the same manner irrespective of the odd field, image data is read in the same manner as in the related art without discriminating the recording field. The present invention may have a device configuration having both the recording device function and the reproducing device function shown in FIGS. 1 and 2, or may be an individual device. In this embodiment, since the dynamic range can be expanded by the amount of the synchronization signal, the D / A converter 14
Is disposed before the synchronous mixing section 15, but there is no problem if it is disposed after the synchronous mixing section 15. FIG. 3 shows an example of the configuration of the memory control unit 8 and shows a vertical address control unit. The line address counter 81 receives the horizontal synchronizing signal HD, counts addresses of write lines, and sends a predetermined output signal to the output enable control unit 83 and the write enable control unit 84 based on the count result. The line address counter 81 outputs a count result as a field memory address. The reset circuit 82 receives the vertical synchronization signal VD and the horizontal synchronization signal HD, and supplies a reset signal to the line address counter 81 based on the output value of the line address counter 81. The output enable control unit 83 receives a signal from the line address counter 81 and outputs a field memory output enable signal at the time of reproduction. Further, the write enable control unit 84 receives the trigger signal and the output from the line address counter 81, and outputs a field memory write enable signal as recording timing at the time of recording. In this embodiment, at the time of recording, a write enable signal is output within a field period following a vertical synchronization signal immediately after the arrival of a video signal of one field to start recording, and there is a difference between an odd field and an even field. The video signal excluding the video signal portion is recorded. During reproduction, a field video signal obtained by reading out the video signal recorded as described above and an interpolated video signal of this video signal are switched and output in synchronization with a field index signal at its own timing. FIG. 5 is a timing chart of a recording operation without a time lag according to the above embodiment. Electric charges are accumulated in the photodiode of the CCD during the exposure period by the electronic shutter operation, and the video signal is read out from the CCD imager in response to the vertical synchronization signal VD that comes immediately after. When field recording CCD output,
It must be recorded and reproduced regardless of whether it is an odd field or an even field. The CCD output is written to the frame memory by the frame memory write gate signal, and at this timing, the video signal portion which is different due to the odd field and the even field is simultaneously excluded. FIG. 6 is a timing chart for a specific example of the odd field data recording of the recording operation described above. A field index signal FID and a vertical synchronization signal VD are generated in synchronization with the horizontal synchronization signal HD. Recording timing pulse R indicating recording timing
Write enable gate signal RECG determined by ECT
(Corresponding to the signal REC-WE) is generated. The VD is reset by the VD reset signal delayed by the HD, and the line address of the memory control 8 starts counting in response to the HD signal. In a predetermined line (in this example, "10"), the line address is reset again by the V address reset signal, and data is recorded from line address 0. The end timing of the RECG signal is determined by the line address, and has an address value “240” in this example. The CCD data is obtained as an addition output of two lines, and is subjected to blanking processing and the like.
, 241, 242, 24 as outputs
3 corresponding data as B, R, B, R,
... is obtained. These output signals are recorded in the field memory. In this embodiment, the data corresponding to the first 1H Y output "1" of each output, the color difference output "B", and the final 0.5H Y output “24
3 "corresponding data and" B "corresponding data,
Data for 5H is deleted and recorded as field memory data. FIG. 4 shows an example of an interlaced color difference signal in the case of reproducing without discriminating a field from data recorded according to the present embodiment. In the figure, a solid line indicates readout video data, and a broken line indicates interpolation data. If the read video data is always read in the odd field and the interpolation data is always output in the even field, the data recorded as shown in FIGS. 6 and 7 is a line determined as shown in FIG. Therefore, the field determination is not required for the color difference processing. FIG. 7 shows a timing chart similar to FIG. 6, and shows an example of even field data recording. In this example, the VD signal is generated at a timing 1 / 2H earlier than the odd field. So, VD
Is delayed by HD, a VD reset signal is generated at the rising edge of HD as in the example of the odd field. The CCD data is obtained as an additional output that is different from the odd field, and is subjected to blanking processing and the like, and the data corresponding to the imaging Y outputs 0 to 242 and the imaging color difference outputs R, B, R,
, B, R are obtained. The data to be written into the field memory has the first 1.
Data corresponding to address “0” and “1” for 5H and “R”
And "B" corresponding data are deleted and recorded. As described above, for the odd field, the front 1H data and the rear 0.5H data are deleted, and for the even field, the front 1.5H data is deleted and recorded in the field memory. It is recorded as field data in the same state irrespective of the field, and does not require field discrimination at the time of reading. As described above, according to the present invention ,
A signal of a predetermined line is selected by thinning out the imaged video signal.
When selected, the obtained video signal is
High speed regardless of the difference between the signal on the other lines
Recording becomes possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a basic configuration block diagram showing an embodiment of a video recording apparatus according to the present invention. FIG. 2 is a basic configuration block diagram showing one embodiment of a video reproducing apparatus according to the present invention. FIG. 3 is a block diagram showing a configuration of a memory control unit in the embodiment shown in FIGS. 1 and 2; FIG. 4 is a diagram showing an example of field writing in an embodiment of the present invention. FIG. 5 is a timing chart of a field write operation in the embodiment of the present invention. FIG. 6 is a timing chart of an odd field write operation in the embodiment of the present invention. FIG. 7 is a timing chart of an even field write operation in the embodiment of the present invention. FIG. 8 is a configuration block diagram of a conventional still image camera. FIG. 9 is a timing chart of a conventional field write operation. FIG. 10 is a diagram illustrating a conventional process of reproducing as interlaced data of a frame by interpolation. FIG. 11 is a configuration block diagram of a conventional still image camera using analog recording. FIG. 12 is a diagram showing a writing area to a semiconductor memory; [Description of Signs] 1 CCD 2 imaging circuit 3, 4 A / D converter 5, 7 field memory 6 synchronization unit 8 memory control unit 9 1H delay unit 10 interpolation data creation unit 11 switch 12 modulation unit 13 Y / C mixing Part 14 D /
A converter 15 Synchronous mixing section 81 Line address counter 82 Reset circuit 83 Output enable control section 84 Write enable control section

Claims (1)

(57) [Claims]Select the signal of a predetermined line by thinning out the imaged video signal.
First means for selecting When a signal of a predetermined line is selected by the first means,
Difference between the signal of a given line and the signal of other lines
Video signal excluding the difference in video signal caused by
Signal on the recording medium at the timing immediately after the vertical synchronization signal.
A second means for recording; A video recording device comprising: