JPS63179682A - Information reproducing device - Google Patents

Abstract

PURPOSE:To reproduce a still picture with excellent picture quality by providing a variable delay means varying a signal delay time in response to the frequency of a control input so as to correct the time base and a memory storing a video signal subjected to time base correction. CONSTITUTION:The variable delay circuit 10 applying base time correction while the signal delay time is varied in response to the frequency of the control input and the memory 12 storing the video signal subjected to time base correction are provided. In case of the still picture reproduction, for example, the video signal read from the memory 12 is fed to the variable delay circuit 10 and the signal of a prescribed frequency is fed to the variable delay circuit 10 as the control signal to apply the correction processing of the video signal read from the memory 12 by using the video signal retarded by a prescribed time obtained from the variable delay circuit 10. Thus, the single variable delay circuit 10 is used in common for the time base correction and the picture quality correction. Thus, the still picture with excellent picture quality is reproduced with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for reproducing video information recorded on a recording medium of a recording disk cap.

11. A conventional information reproducing device is shown in FIG. In the figure, an R1 (high frequency) signal containing video information read from a recording disk 2 by a pickup 1 is supplied to a demodulation circuit 3 comprising an FM demodulator or the like. The video signal is demodulated by the demodulation circuit 3 and supplied to the UA/D converter 4 and the synchronization separation circuit 5. A synchronization separation circuit 5 separates horizontal and vertical synchronization signals in the video signal. The horizontal synchronization signal output from the synchronization separation circuit 5 is supplied to a phase comparison circuit 6 and an old clock generation circuit 9. In the phase comparison circuit 6, a phase comparison is made between the horizontal synchronization signal and a reference signal r of the device frequency composed of a crystal oscillator (not shown), etc., and a phase difference detection signal is generated according to the phase difference between both signals. be done. This phase difference detection signal is supplied as a spindle error signal to a spindle motor 8 that rotationally drives the recording disk 2 via a servo amplifier 7, and the rotational speed of the recording disk 2 is controlled. Further, the write clock generation circuit 9 is configured to generate a write clock pulse synchronized with the horizontal synchronization signal.

The output pulse of the write clock generation circuit 9 is A/I')
It is supplied to the converter 4 as a sampling pulse, and at the same time, it is supplied to the variable delay circuit 10 as a write command signal. The video signal is sampled in the A/D converter 4 using the write clock pulse, and a digital signal is generated according to the obtained sample value.

The output data of this A/D converter 4 is supplied to a variable delay circuit 10. A read clock pulse of a predetermined frequency outputted from a read clock generation circuit 11 is supplied to the variable delay circuit 10 as a read command signal. The variable delay circuit 10 is composed of, for example, a first-in, first-out memory, and is configured to sequentially write input data in response to a write command signal, and not to read out the written data sequentially in the order in which it was written in accordance with a read command signal. In the variable delay circuit 10, the signal delay time of the input signal F-N changes according to the time axis error, and the time axis error is corrected.

Output data of variable delay circuit 10 is supplied to memory 12. Address data and mode control signals are supplied to the memory 12 from a memory controller 13. The memory controller 13 is supplied with a continuous clock pulse and a still image reproduction command signal a output from an operation section (not shown). In the memory controller 13, when there is no still image reproduction command signal a, data is sequentially written into the memory 12 by a read clock, and the written data is sequentially read out in the order in which it was written. When a exists, the mode control signal and address data are output so that the data written in the memory 12 is read out sequentially in accordance with the read clock.

Data read from memory 12 is supplied to D/A converter 14. In the D/A converter 14, the data read from the memory 12 is sequentially converted into an analog signal by a read clock pulse and output as a reproduced video signal.

In the above configuration, when there is no still image reproduction command signal output from the operation unit (not shown), the video signal output from the demodulation circuit 3 passes through the A/D converter 4 and the variable delay circuit 10. After being written to the memory 12, the information is sequentially read out in the order in which it was written, and the recorded information on the recording disk 2 is sequentially reproduced in the order in which it is read. However, when a still image reproduction command signal is present, the data stored in the memory 12 is repeatedly read out without being rewritten, and the still image becomes 1'? It will be done.

If the storage capacity of the memory 12 is set to a value that can store data corresponding to one frame of video signals, the cost will increase, and at the same time, one frame of video signals corresponding to moving images will be stored. When data corresponding to is written,
Since blurring occurs in still images obtained by repeatedly reading out this written data, the storage capacity of the memory 12 must be set to a value that can store data corresponding to one field of video signals. There is.

For this reason, in a conventional information reproducing device, when reproducing a still image for the first time, in the corresponding portions of the area along the scanning line of the first field and the area along the scanning line of the second field on the reproduction screen, Since the brightness etc. will be the same,
The luminance of a portion α that intersects with a predetermined vertical line on a region along a plurality of scanning lines in the first field, and the luminance of a portion β that intersects with the predetermined vertical line on a region along a plurality of scanning lines of the second field. As shown in FIG. 6, the center C of the image formed in the first field is different from the center d of the image formed in the second field, resulting in line flicker. In addition, in the conventional information reproducing apparatus, the video signal read from the recording disk 2 causes the first
When the brightness of a part γ of the area along the scanning line of the field and a part δ of the area along the scanning line of the second field, as shown by the broken line, are different from other parts and a diagonal line is formed,
There is also a drawback that the reproduced image based on the video signal output from the D/A converter 14 due to the still image reproduction operation becomes as shown in FIG.

Therefore, an IHff extension line is provided that delays the data read from the memory 12 by 1H (one horizontal scanning period), and the data obtained by calculating the average of the instantaneous values of the input and output of this IHI extension line is It has been considered to supply the data to the D/A converter 14 instead of the data read from the memory 12 every other field. However, then 1
Since the llii wire extension is expensive, a problem arises in that the manufacturing cost is high.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an inexpensive information reproducing device that can reproduce still images with good image quality.

The information reproducing device according to the present invention changes the signal delay time according to the frequency of the control input to perform time axis correction, and uses a variable delay means and a memory for storing the video signal subjected to the time axis correction, For example, when playing a still image, a video signal read from the memory is supplied to the variable delay means, and at the same time a signal of a predetermined frequency is supplied as a control signal to the variable delay means, whereby the video signal is delayed by a predetermined time obtained from the variable delay means. The configuration is such that correction processing is performed on the video signal read out from the memory using the video signal.

Support 1 Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4.

In FIG. 1, a pickup 1, a recording disk 2, a demodulation circuit 3, an A/D converter 4, a synchronous separation circuit 5, a phase comparison circuit 6, a servo amplifier 7, a spindle motor 8, a write clock generation circuit 9, a memory 12, The memory controller 13- is connected in the same way as the device of FIG.

However, in this example, the output data of the A/D converter 4 is supplied to one input terminal of the changeover switch 20. Data read from the memory 12 is supplied to the other input terminal of the changeover switch 20. A still image reproduction command signal a is supplied to a control input terminal of the changeover switch 20 from an operation section (not shown). The changeover switch 20 selects the memory 1 when the still image reproduction command signal a is present.
The data read out from A/D converter 2 is selectively outputted, and the output of A/D converter 4 is selectively outputted when still image reproduction command signal a is not present. The output data of this changeover switch 20 is supplied to the variable delay circuit 10.

At the same time, the output data of the changeover switch 20 is supplied to the Kawaguchi circuit 21 and added to the output data of the variable delay circuit 10. The output data of Kawaguchi circuit 21 is
It is supplied to the multiplication circuit 22 and multiplied by 1/2. The output data of the itching circuit 22 is supplied to one input terminal of the changeover switch 23. Data read from the memory 12 is supplied to the other input terminal of the changeover switch 23.

The changeover control circuit 24 is connected to the control input terminal of the changeover switch 23.
A switching command signal is supplied from. The changeover switch 23 is
It is configured to selectively output the output of the boarding gate circuit 22 when the switching command signal is present, and to selectively output the data read from the memory 12 when the switching command signal is absent. The switching control circuit 24 is configured such that a pulse generated each time data for one field is read from the memory 12 in the memory controller 13 is supplied to a clock input terminal and outputted from an operation section (not shown). It consists of a T-type flip-flop whose reset input terminal is supplied with an image reproduction command signal @a. This switching control circuit 2
4, when the still image reproduction command signal a is present, the output of the switching command signal 6i1 is alternately started and stopped every time the time corresponding to the cycle in which data for one field is read from the memory 12 passes. It will be done.

Further, the write clock pulse which is the output of the write clock generation circuit 9 is supplied to one input terminal of the changeover switch 25 at the same time as being supplied to the A/D converter 4. The other input terminal of the changeover switch 25 is supplied with a read clock pulse. A still image reproduction command signal a output from an operation section (not shown) is supplied to a control input terminal of the changeover switch 25. Changeover switch 2
5 is configured to selectively output a read clock pulse when the still image reproduction command signal a is present, and to selectively output a write clock pulse when the still image reproduction command signal a is absent. The output pulse of this changeover switch 25 is supplied to the variable delay circuit 10 as a write command signal.

In the above configuration, when the still image reproduction command signal a is not present, the video signal output from the demodulation circuit 3 passes through the A/D converter 4 and the variable delay circuit 10, and then is stored in the memory 12, similar to the device shown in FIG. Data stored in the memory 12 is sequentially written to rewrite the data stored in the memory 12.Data stored in the memory 12 is sequentially read out in the order in which it was written to the D/A converter 14.
It is output after passing through. Next, when a still single image reproduction command signal a is generated by, for example, a key operation on the operating section, the data stored in the memory 12 is repeatedly read out without being rewritten. Data read from memory 12 is selectively supplied to variable delay circuit 10. At the same time, a read clock pulse is supplied to the variable delay circuit 10 as a write command signal instead of the intervening clock pulse, so that the signal delay time in the variable delay circuit 10 becomes constant.

Therefore, if the signal delay time in the variable delay circuit 10 is set to 1H at this time, the output data of the multiplier circuit 22 will be delayed by 1H between the data read from the memory 12 and this data. It is equal to the average value of the data obtained by Since the output data of the input circuit 22 is supplied to the D/A converter 14 every other field, the corresponding portions α and β of the area along the scanning line of the first and second fields on the playback screen. As shown in FIG. 2, the center C of the image formed in the first field coincides with the center d of the image formed in the second field, and no line flicker occurs. At the same time, the video signal read from the recording disk 2 causes the first
If the luminance of a part γ of the area along the scanning line of the field and a part δ of the area along the scanning line of the second field as shown by a broken line are different from other parts, and a diagonal line 1) is formed, The reproduced image according to the video signal outputted from the D/A converter 14 by the still image reproduction operation becomes as shown in FIG.

FIG. 4 is a block diagram showing another embodiment of the invention. In the figure, a pickup 1, a recording disk 2, a demodulation circuit 3, an A/D converter 4, and a 111J separation circuit 5 are shown.
, phase comparison circuit 6, servo amplifier 7, spindle motor 8, aggressive clock generation circuit 9, variable delay circuit 10, read clock generation circuit 11, memory 12, memory controller 13, D/A converter 14, changeover switch 20
．． 23, 25 and the adder circuit 21 are connected in the same way as in the device of FIG. However, in this example, the output of the changeover switch 20 and the output of the variable delay circuit 10 are supplied to the Kawaguchi circuit 21 and at the same time, are supplied to the reduction-n circuit 26. The output data of the adder circuit 21 is supplied to a noise reduction circuit 27.

The noise reduction circuit 27 is composed of, for example, a digital filter having a high frequency removal filter configuration. This noise reduction circuit 27 removes noise components. The output of the noise reduction circuit 27 is sent to the adder circuit 2.
B and is added to the output data of the subtraction circuit 26. The output data of this addition circuit 28 is transferred to the changeover switch 23
is supplied to one input terminal of the Further, a still image reproduction command signal a is supplied to a control input terminal of this changeover switch 23. The changeover switch 23 selectively outputs the output data of the adder circuit 28 when the still image reproduction command signal a is present, and outputs the output data of the adder circuit 28 selectively when the still image reproduction command signal a is absent.
The device is configured to selectively output data read from the memory.

In the above configuration, when the still image reproduction command signal a is not present, the video signal output from the demodulation circuit 3 passes through the A/D converter 4 and the variable delay circuit 10, and then is stored in the memory 12, similar to the device shown in FIG. The data stored in the memory 12 is rewritten by being written sequentially. The data stored in the memory 12 is sequentially read out in the order in which it was written, and the data is read out to the D/A converter 14.
It is output after passing through. Next, when a still image reproduction command signal is generated by, for example, a key operation on the operating section, the data stored in the memory 12 is repeatedly read out without being rewritten. Data read from this memory 12 is selectively supplied to the variable R detour path 10. At the same time, a read clock pulse is supplied to the variable delay circuit 10 as a write command signal instead of a write clock pulse, so that the signal delay time 1 in the variable delay circuit 10 is constant.

Therefore, if the signal delay time in the variable delay circuit 10 is set to 1H at this time, the variable delay circuit 10, the Kawaguchi circuit 21, and the subtraction circuit 26 act as a comb filter, and the luminance signal is separated from the addition circuit 21. The subtraction circuit 26 separates and outputs the color signal. The luminance signal is supplied to a noise reduction circuit 27 to remove noise components. The luminance signal from which the noise component has been removed is supplied to the adder circuit 28, where it is combined with the chrominance signal to generate data corresponding to the video signal.

Since the output data of the adder circuit 28 is selectively outputted from the changeover switch 23 and supplied to the D/A converter 14, a good still image without noise is reproduced.

In the above embodiment, the variable delay circuit 10 is made up of a digital circuit, but the variable delay circuit 10
It is also possible to use an analog delay circuit such as a COD.

As described in detail above, the information reproducing apparatus according to the present invention includes a variable delay means for correcting the time axis by changing the signal delay time according to the frequency of the control input, and a video signal on which the time axis has been corrected. For example, when playing back a still image, a video signal read from the memory is supplied to the variable delay means, and at the same time a signal of a predetermined frequency is supplied to the variable delay means as a control signal. Since the structure is such that the video signal read out from the memory is corrected using the obtained video signal delayed by a predetermined time, a single variable delay means can be used for both time axis correction and image quality correction. This makes it possible to reproduce still images with good image quality with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 shows mutual correspondence in areas along each scanning line in the first and second fields of a still image obtained by the system B in FIG. FIG. 3 is a diagram showing the brightness of the shaded part of the still image obtained by the apparatus of FIG.
FIG. 4 is a block diagram showing an embodiment of the present invention;
The figure does not show a block diagram of a conventional information reproducing device, and FIG. 6 shows corresponding portions in areas along each scanning line in the first and second fields of the still image obtained by Hrlt in FIG. A diagram showing brightness, FIG. 7, is a diagram showing the brightness of a shaded area of a still image obtained by the apparatus of FIG. 5. Explanation of symbols of main parts 1...Pickup 2...Recording disk 9...Write clock generation circuit 10...
・Variable delay circuit 11... Read D-tock generation circuit 12...
··memory

Claims (1)

[Claims] An information reproducing device that reads and reproduces video information recorded on a recording medium, comprising timing signal generating means that generates a timing signal having a frequency according to a time axis error of a video signal obtained from the recording medium; variable delay means for delaying an input signal by a time corresponding to a frequency of a control input; a memory for storing an output of the variable delay means in accordance with a command; and a signal read from the memory and a signal read from the recording medium. first signal selection means for selectively supplying one of the video signals to the variable delay means in response to the command; a second signal selection means for supplying the variable delay means as the control input; and a second signal selection means for processing the signal read out from the memory by the output of the variable delay means in response to the command so that the signal is read out from the memory. 1. An information reproducing apparatus comprising: a correction means for performing image quality correction processing on a signal.