JP2832902B2 - Video signal playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reproducing a video signal recorded on a recording medium, and more particularly to an apparatus having a function of reproducing at high speed. 2. Description of the Related Art When a so-called high-speed playback is performed in a rotary head type video playback device such as a video tape recorder (VTR), a playback head straddles a plurality of recording tracks formed obliquely on a magnetic tape. Scan. In this case, for example, in the case where a guard band is formed between tracks, or in the case where tilt azimuth recording in which the recording azimuth is made different between adjacent tracks is performed, the envelope of the modulated video signal obtained from the reproduction head is periodically changed. A weak signal portion. That is, the output of the reproduced video signal becomes extremely small when scanning between tracks or a track having an azimuth opposite to the reproducing head. Therefore, as one method for improving the image quality at the time of high-speed reproduction, the level of a modulated video signal reproduced from a recording tape is monitored, and a portion having a large level is stored in a memory.
In a low-level portion, there is a method of reading data from the memory and using the data instead. This method reduces noise
An image without bars can be obtained. [Problems to be Solved by the Invention] However, as in these conventional examples, in a section in which a normal reproduction signal cannot be obtained from the rotary head, the information is replaced with information of a substantially equivalent section one field before, which is read from the memory. In the method of obtaining a reproduction screen without noise bars, the phase of the horizontal synchronization signal before and after the transition from writing to reading to the memory and from reading to writing are relatively shifted. In some cases, the phase shift causes a skew on the reproduction screen. In particular, the above-described high-speed reproduction method is applied to a magnetic recording / reproducing apparatus in which the recording position of the horizontal synchronizing signal is shifted between adjacent tracks on the recording medium and a recording pattern in which so-called H arrangement is not performed, for example, a standard mode of 8 mm VTR. When applied, a large skew occurs. An object of the present invention is to solve such a problem and to provide a video signal reproducing apparatus capable of obtaining a high-speed reproduction screen without skew. [Means for Solving the Problems] A video signal reproducing device according to the present invention is a device for reproducing a video signal by a rotating head, and a memory capable of storing a video signal reproduced by the rotating head; Address generation means for generating a memory read address; a first state for outputting a video signal reproduced by the rotary head and written to the memory; and a second state for outputting a video signal read from the memory. Switching means for switching the state of the apparatus between the first state and the second state; a horizontal synchronization signal in a video signal written to the memory before switching from the first state to the second state by the switching means; Detecting means for detecting a phase difference from a horizontal synchronizing signal in the video signal read from the memory after the switching; and Control means for stopping the advance of the read address by the address generation means in accordance with the detected phase difference. [Operation] By the above means, the phase between the horizontal synchronization signal of the video signal written to the memory and the horizontal synchronization signal read from the memory can be adjusted before and after the memory shifts from the writing state to the reading state. . As a result, a high-speed reproduced image without skew can be obtained. Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a block diagram of one embodiment. In this embodiment, the present invention is applied to a known two-head helical scanning VTR. In FIG. 1, a reproduced composite color video signal obtained by demodulating a modulated video signal from a reproducing head (not shown) reproduced at a high speed at an even multiple of the recording speed is input to an input terminal 10. This reproduced composite color video signal is
The signal is supplied to an A / D converter 14 via a pass filter (LPF) 12. The A / D converter 14 converts an input analog video signal into a digital video signal and supplies the digital video signal to the timing sequencer 16. The timing sequencer 16 exchanges this digital video signal with the field memory 18 in accordance with the set operation mode, and also converts the digital video signal via a skew correction circuit 20 which will be described in detail later. It is supplied to the A converter 22. That is, the timing sequencer 16 controls the A /
The digital video signal from the D converter 14 is transmitted to the D / A converter 22 via the field memory 18 and the skew correction circuit 20.
When reading the memory, the field memory 18
Is transferred to the D / A converter 22 via the skew correction circuit 20. The D / A converter 22 converts the digital video signal into an analog composite color video signal, and supplies it to the output terminal 26 via the LPF 24. A known television device or the like is connected to the output terminal 26. The burst gate 28 extracts a color burst signal from the reproduced composite color video signal at the input terminal 10 and supplies it to the clock reproducing circuit 30. The clock generation circuit 30 generates a clock synchronized with the color burst signal and having a frequency multiplied by the subcarrier frequency of the chroma signal, and outputs the clock to the A / D converter 14, the timing sequencer 16,
It is applied to the skew correction circuit 20 and the D / A converter 22. The timing sequencer 16 uses this clock to send a RAS (row address strobe) signal, CAS (column address
Strobe) signal, WE (write enable) signal, OE
An (output enable) signal is supplied to the field memory 18 and an address clock signal is supplied to the address signal generating circuit 32 via the AND circuit 34.
The address signal generating circuit 32 generates an address signal for the field memory 18. In general, in a two-head VTR, a head switching signal having the same period as the rotation period of the rotary head is formed by detecting the rotation phase of the rotary head, and the head to be used for reproduction is switched based on the head switching signal. This head switching signal is supplied to another input terminal 36,
The multiplying circuit 38 supplies a multiplied signal of the head switching signal to the skew correction circuit 20, and the skew correction circuit 20 outputs a write / read instruction signal of the memory 18 from the output terminal 20G in accordance with the received signal. Apply to 16. The timing sequencer 18 controls writing to and reading from the field memory 20 by the write / read instruction signal. Also, the skew correction circuit 20 and the AND circuit 34
A binary signal is input to the address generator, thereby controlling the supply of an address clock signal from the timing sequencer 16 to the address generator 32. The multiplication circuit 38 comprises a so-called phase locked loop (PLL),
On the output side, a multiplied signal in phase with the head switching signal of the input terminal 36 is output. The present invention is characterized in particular by the operation of the skew correction circuit 20 and the AND circuit 34 for address / clock control. The skew correction circuit 20 will be described in detail below. FIG. 2 shows an embodiment of the skew correction circuit 20. A digital video signal is applied from the timing sequencer 16 to the input terminal 20B of the skew correction circuit 20. The sync separation circuit 40 of the skew correction circuit 20 separates and outputs a horizontal sync signal portion in the digital video signal. The control signal input from the multiplication circuit 38 to the input terminal 20C of the skew correction circuit 20 is a D flip-flop (D-FF) 42
Is applied to the data input terminal. The output of the sync separation circuit 40 is applied to the clock input terminal of the D-FF 42,
The FF 42 holds and outputs the signal state of the data input terminal according to the output of the sync separation circuit 40. The output of the D-FF 42 is connected to a monostable multivibrator (MM) 44, a data input terminal and a reset input terminal of the D-FF 46, and a reset pulse generation circuit 48. The output of MM44 is connected to the clock input terminal of D-FF46. Although the reason will be described later, the width of the output pulse of the MM 44 is set to be longer than the output pulse width of the sync separation circuit 40. Q output of D-FF46 is output terminal
Connect to 20. The reset pulse generating circuit 48 generates a reset pulse which becomes L when the output of the D-FF 42 rises. This reset pulse is applied to one input of the AND circuit 50, and the output of the AND circuit 50 is connected to the reset terminal of the 1H counter 52. A clock signal is applied to the clock input terminal of the counter 52 from the clock generation circuit 30 via the input terminal 20D. The counter 52 is set to H during the counting operation.
A signal is output, and an L signal is output during operation stop or after counting 1H. The output of the counter 52 is connected to one input of an AND circuit 54, and the output of the D-FF 46 is connected to the other input of the AND circuit 54. The output of the AND circuit 54 is connected to one input of the AND circuit 56, and the other input of the AND circuit 56 is connected to the output of the sync separation circuit 40. AND circuit 56
This is a circuit for detecting the phase of the read signal with respect to the write signal when writing from 18 to reading is started. The output of the AND circuit 56 is applied to the AND circuit 34 via the inverter 58 and the output terminal 20F. The output of the AND circuit 56 is also connected to the clock input terminal of the D-FF 60, and the power supply V _CC is connected to the data input terminal thereof.
The output of the reset pulse generating circuit 48 is connected to the reset input terminal. The output of the D-FF 60 is connected to one input of an OR circuit 62, and the other input of the OR circuit 62 is connected to a counter 52.
Output is connected. The output of the OR circuit 62 is connected to the other input of the AND circuit 50. The output of counter 52 is also connected to the control input of multiplexer 64. The input terminal 20B is directly connected to one input of the multiplexer 64, and is connected to the multiplexer 64 via a memory 66 having a capacity of two horizontal synchronization signal cycle periods (2H).
Connect to another input of. The multiplexer 64 outputs a signal from the memory 66 when the control input is H, and outputs a signal from the input terminal 20B during the L period. Multiplexer 6
The output of 4 is applied to the D / A converter 22 via the output terminal 20E. The output of the multiplexer 64 is also supplied to a sync separation circuit 68, where the separated horizontal sync signal is supplied to a reset pulse generation circuit 70. Reset pulse generation circuit 70
Is connected to the reset terminal of the memory 66 and used as an address reset signal. The clock terminal of the memory 66 is connected to the clock generation circuit 3 via the input terminal 20A.
A clock signal is supplied from 0, and the memory 66 updates the address value by this clock signal, sequentially captures the input signal, and sequentially outputs a signal delayed by 2H. That is, the memory 66 is also a delay circuit that operates as a shift register. To continuously the phase of the chroma signal having the odd multiple of the carrier frequency of 1 / 2f _H, and sets the delay amount to 2H. Next, the operation of the illustrated embodiment will be described. FIG. 3 shows a timing chart when the phase of the read signal is earlier than that of the write signal, and FIG. 4 shows the reverse case. FIG. 3A shows a digital video signal output from the A / D converter 14, which is a signal which is written to the memory 18 as necessary. However, for ease of understanding, only the luminance signal component is shown as if it were an analog video signal. Such a video signal is used as a timing sequencer.
When the signal is applied from 16 to the input terminal 20B of the skew correction circuit 20, the synchronization separation circuit 40 of the skew correction circuit 20 extracts only the horizontal synchronization signal portion from the signal, and as shown in FIG. A signal whose portion becomes H is output. In addition, it is assumed that a signal for writing and reading timing control of the memory 18 as shown in, for example, FIG. 3 (e) is input from the multiplication circuit 38 to the input terminal 20C of the skew correction circuit 20. The D-FF 42 synchronizes the control signal from the multiplying circuit 38 with the timing of the horizontal synchronizing signal according to the rise of the horizontal synchronizing signal output of the synchronizing separation circuit 40, as shown in FIG. 3 (f). In response to the output signal of the D-FF 42, the MM 44 outputs a negative pulse (FIG. 3 (g)) which becomes L for a certain period from the rise of this signal. As a result, the D-FF 46 outputs the third pulse.
As shown in FIG. 7H, the output signal of D-FF42 is
A signal delayed by the set pulse width of MM44 is output at the rising portion. This output signal from the D-FF 46 is sent from the output terminal 20G to the timing sequencer 16 as a read / write switching signal for the memory 18. The timing sequencer 16 writes the output of the A / D converter 14 into the memory 18 when this signal is L, and reads out the stored signal from the memory 18 and sends it to the skew correction circuit 20 when this signal is H. As shown in FIG. 3 (i), the reset pulse generating circuit 48 resets the reset pulse in response to the rising edge of the output of the DPFF 42.
Pulse, and this reset pulse
(FIG. 3 (p)), and the counter 52 is reset. Thereby, the counter 52 starts counting the clock signal at the clock input terminal, and as shown in FIG.
The output is set to H for one horizontal synchronization signal period. The AND circuit 54 outputs, as shown in FIG. 3 (k), a signal whose output signal from the counter 52 has been delayed by the rising edge of the output pulse width of the MM 44. Now, it is assumed that the read / write switching signal output from the output terminal 20G to the timing sequencer 16 changes from L to H, and the state shifts from writing to reading. Then, it is assumed that the phase of the write signal is advanced for some reason, and the read signal from the memory 18 has the phase shown in FIG. 3B. In this situation, the signal shown in FIG. 3C is input to the input terminal 20B.
Although the read signal from the memory 18 and the signal at the input terminal 20B are actually digital signals, FIGS. 3 (b) and 3 (c) show them as analog signals for easy understanding. If the phase of the read signal is earlier than that of the write signal, the horizontal synchronizing signal enters during the period when the output of the AND circuit 54 is at H, and the output of the sync separation circuit 40 becomes H. Therefore, the AND circuit 56 can detect whether the phase of the read signal is earlier than the phase of the write signal. In order to avoid the influence of the horizontal synchronization signal (FIG. 3 (d)) at the start of counting by the counter 52, D
-The output of FF42 is delayed by MM44. Therefore MM44
Is wider than the pulse width of the horizontal synchronization signal. When the horizontal synchronizing signal is inputted to the input terminal 20B, the output of the AND circuit 56 becomes H by the output of the synchronizing separation circuit 40, it is inverted by the inverter 58 to become L, and one of the AND circuit 34 is outputted from the output terminal 20F. It is supplied to the input terminal. As a result, the AND circuit 34 is closed, and the address clock signal from the timing sequencer 16 is not input to the address generation circuit 32. Therefore, the AND circuit
When the horizontal synchronizing signal is read from the memory 18 while the output of 54 is H, the address value of the memory 18 does not change there, and during that time, only the leading edge of the horizontal synchronizing signal is repeatedly read. . When the output of the counter 52 goes low, the outputs of the AND circuits 54 and 56 also go low, the output of the inverter 58 goes high, and the AND circuit 34 outputs the address clock signal from the timing sequencer 16 to the address generating circuit 32. To supply. Thereby, the address of the memory 18 advances, and the stored data of the memory 18 is sequentially read. That is, the address of the memory 18 is stopped for a period corresponding to the phase difference between the write signal to the memory 18 and the read signal from the memory 18. D-FF 60 is the rising edge of the output signal of the AND circuit 56. And outputs a signal which becomes H in synchronization with. Further, since the output signal of the reset pulse generating circuit 48 is applied to the reset input terminal of the D-FF 60, the output signal of the D-FF 60 eventually becomes as shown in FIG. That is, the D-FF60 is connected to the input terminal 20C.
L in synchronization with the horizontal synchronization signal immediately after the rise of the signal
And becomes H in synchronization with the horizontal synchronization signal read from the memory 18 during about one horizontal synchronization signal period thereafter. Since the output of the D-FF 60 is H in the OR circuit 62, the output remains unchanged at H as shown in FIG. 3 (o). Accordingly, the output of the AND circuit 50 becomes as shown in FIG. 3 (p), and thereafter, the reset pulse is not input to the counter 52. In this case, the counter 52 does not operate continuously. While the output signal of the counter 52 is at the H level, the multiplexer 64 selects a video signal that has passed through the memory 66 and supplies it to the output terminal 20E. As a result, the delay signal by the memory 66 is used before and after the transition from the writing to the reading of the memory 18, and the skew accompanying the transition from the writing to the reading does not occur in the reproduced video. The signal at the output terminal 20E at that time is shown in FIG. 3 (q). The signal at the output terminal 20E is originally a digital signal, but is shown as an analog signal in FIG. 3 (q) for convenience of explanation. Fig. 3 (q)
As can be understood from FIG. 7, a video signal having a continuous phase is output to the output terminal 20E. By using the signal 2H before by the memory 66, the phase of the chroma signal also becomes continuous. Next, the operation when the phase of the read signal is delayed with respect to the write signal will be described with reference to FIG. Each signal in FIG. 4 corresponds to the signal of the same symbol in FIG. In this case, the horizontal synchronizing signal is not input to the terminal 20B during the period when the output of the AND circuit 54 (FIG. 4 (k)) is H.
The output of the inverter 6 becomes L and the output of the inverter 58 becomes H.
The address value of 8 is sequentially updated and read out. However, when the counter 52 counts for 1H period and its output becomes L, the output of the D-FF 60 remains L, the outputs of the OR circuit 62 and the AND circuit 50 become L, and the counter 52 is reset. . By this reset, the counter 52 operates again, and the output becomes H. Since the horizontal synchronizing signal is present in the read signal from the memory 18 during the 1H period in which the output of the counter 52 is at H, thereafter, the phase of the read signal with respect to the write signal described above is changed. It works as if it were early. By the continuous operation of the counter 52, a signal for two horizontal synchronization signal cycle periods is supplied from the memory 66 to the output terminal 20E. The same operation is performed even when the horizontal synchronization signal is not input to the input terminal 20B due to a dropout or the like. Next, a case where the reading of the memory 18 is switched to the writing will be described. When the switching timing control signal input to the input terminal 20C changes from H to L, the output of the D-FF 42 changes from H to L in synchronization with the horizontal synchronization signal immediately thereafter. At this time, the reset pulse generating circuit 48 does not respond and the output remains at H, so that the counter 52 does not start the counting operation. Although the signal of the clock input terminal to the D-FF 46 does not change, the output of the D-FF 46 changes from H to L because the output of the D-FF 42 is applied to the reset terminal. This is supplied to the timing sequencer 16 via the output terminal 20G, and the memory 18 changes from reading to writing. Since the counter 52 does not operate, no other circuits operate, and the signal at the input terminal 20B is supplied from the output terminal 20E to the D / A converter 22 without passing through the memory 66. Therefore, D / A
A signal switched from reading to writing in the memory 18 is input to the converter 22 in synchronization with the horizontal and yellow signal in the read signal, and skew correction is not performed. However, if there is no phase difference between the write signal and the read signal when transitioning from writing to reading to the memory 18, the time between the horizontal synchronizing signals between the write signal and the read signal is substantially constant. Therefore, even when the read operation of the memory 18 is shifted to the write operation, no phase difference occurs between the horizontal synchronizing signal of the read signal and the horizontal synchronizing signal of the write signal, and the phase difference is very small. As described above, by switching the operation in the horizontal synchronization signal portion, the screen can be easily viewed. In the above-described embodiment, the head switching signal is input to the input terminal 36 and the multiplied signal is formed by the multiplying circuit 38 to be used as a signal for controlling the timing of switching between writing and reading of the memory 18. As the signal, a signal formed by detecting the level of a reproduced modulation video signal may be used, and in this case, the same effect as in the above embodiment can be obtained. In the preferred embodiment shown, noise in the playback screen
Bars can be completely prevented. [Effects of the Invention] As can be easily understood from the above description, according to the present invention, a high-speed playback screen without skew can be obtained,
In particular, a great effect can be obtained when the present invention is applied to a recording / reproducing method using a recording track pattern without H arrangement.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a main part of a video signal reproducing apparatus according to the present invention, and FIG. 2 is a skew correction circuit 20 of FIG.
FIG. 3 and FIG. 4 are timing charts for explaining the operation. 10, 36 ... input terminal, 12 ... LPF, 14 ... A / D converter, 16
…… Timing sequencer, 18 …… Field memory, 20 …… Skew correction circuit, 22 …… D / A converter, 24…
… LPF, 26 …… Output terminal, 28 …… Burst gate, 30
…… Clock generation circuit, 32 …… Address generation circuit, 38…
… Multiplier circuit, 40,68… Sync separation circuit, 42,46,60… D
-FF, 44 ... MM, 48,70 ... Reset pulse generation circuit, 50,54,56 ... And circuit, 52 ... Counter, 58 ...
Inverter, 62… OR circuit, 64… Mux,
66 …… Memory

Claims (1)

(57) [Claims] An apparatus for reproducing a video signal by a rotating head, a memory capable of storing a video signal reproduced by the rotating head, address generating means for generating a read address of the memory, Switching means for switching the state of the device between a first state for outputting a video signal written to a memory and a second state for outputting a video signal read from the memory; A phase difference between a horizontal synchronization signal in a video signal written to the memory before switching from the first state to the second state and a horizontal synchronization signal in a video signal read from the memory after the switching. Detecting means for detecting the phase difference, and reading by the address generating means according to the phase difference detected by the detecting means. Video signal reproducing apparatus characterized by a control means for stopping the progress of the address.