JPH01183282A - Signal conversion system - Google Patents

Abstract

PURPOSE:To effectively use a storage medium by storing different kinds of information in the main memory area of the storage medium corresponding to an available picture area and a sub-memory area other thin said area. CONSTITUTION:An area corresponding to the available picture area in a video signal is extracted and processed by an image pickup part 3, a process part 4 and a storage part 5 as a principal information converting means, and is supplied to the range of the main memory area 21 of a card memory 2. Besides, auxiliary information signal other than the video signal, i.e., an imager discriminate signal, a count signal and a character signal are obtained by an auxiliary information converting means 7, and are supplied to the sub-memory area 22 of the card memory 2. Consequently, because all of the main memory area 21 and the sub-memory area 22 of the card memory 2 are used by the video signal (luminance signal and color difference signal) and the auxiliary information signal, the card memory 2 can be used effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention can be configured, for example, integrally with a video camera, electronic still camera, or other device that generates an image signal, or separately from those devices. The present invention relates to a signal conversion system that is inserted into a signal transmission path between a device and a storage medium (for example, a solid-state memory such as a card memory) that can be removably loaded into the main body of the device.

[Prior Art] A system that converts image information into digital image data using an A/D conversion means and stores this in an image memory is known as T.
The present applicant has already proposed a TV image data input device for use in V-image computer processing (Japanese Patent Laid-Open No. 59-94164, Japanese Patent Laid-open No. 80-20287).
In this regard, various known systems have been realized. These systems generally sample a composite video signal generated from a TV right camera at a predetermined rate, perform A/D conversion to convert it into digital data, and access this digital data to memory using a predetermined address signal. By doing so, the data is stored in the memory.

On the other hand, in recent years, there has been progress in the development of systems for converting image information into a storage medium such as a so-called card memory that can be removably loaded into a device body having a signal conversion function. It's coming. This type of system converts image information into digital data on a storage medium (
This system has already been proposed by the applicant as a signal conversion system (Japanese Patent Application No. 1983).
-213500). This signal conversion system A/D converts a composite video signal (a signal in which a color signal C is superimposed on a luminance signal Y) from a TV right camera, and extracts this signal to correspond to an effective screen of a TV image. A section that mainly includes a signal portion is extracted and the signal is stored in the card memory. According to this signal conversion system, only the effective screen stored in the card memory mentioned above is extracted (No. 8), so the capacity of the card memory is small and the card memory can be used effectively.

[Problems to be Solved by the Invention] The conventional system as described above has the following problems. In the patent application No. 82-213580, one horizontal scanning period (lH) is 910CLK.
And what is the video signal period corresponding to the effective screen? (ioc
It is LK. Further, l vertical scanning period IV is 2B2.
5H, and the video signal period is 242H.

Therefore, the memory area required to store the effective screen for one field is the memory area obtained by multiplying the horizontal scanning period 700CLK by the vertical scanning period 242H. However, since the memory area is generally determined based on a binary digital signal, a memory having a 788 CLK x 256 H memory area is used as the memory capable of storing an effective screen. In other words, the memory area of the storage medium actually used is larger than the memory area necessary and sufficient for the effective screen. For this reason, the difference between both memory areas was wasted without being used for any other purpose.

In other words, there is a problem in that the storage medium cannot be used effectively.

An object of the present invention is to store separate information in a main memory area corresponding to an effective screen in a storage medium and a sub memory area other than the main memory area corresponding to this effective screen,
An object of the present invention is to provide a signal conversion system that can fully utilize a storage medium.

[Means for Solving the Problems] The present invention takes the following measures to solve the above problems and achieve the objects. That is, a main information signal for extracting and processing the effective screen corresponding part of the video signal so as to fit within the range of at least one main area set for the applied storage medium and supplying it to the main area. a conversion means, and obtains a sub information signal other than the 1-2 video signal to fit within the range of at least one trial 11 area set for a portion of the storage medium other than the main area, and transfers it to the sub area. and sub-information conversion means for supplying the information.

[Effects] By taking such measures, the following effects are achieved. The main information signal conversion means extracts a portion of the video signal that corresponds to the effective screen, and supplies the extracted portion to the main area of the storage medium. Further, a sub information signal other than the above video signal is obtained by the sub information converting means and supplied to the sub area of the storage medium.

As a result, the main area and sub-area of the storage medium are fully utilized by the video signal and the sub-information signal, so that the blind utilization rate of the storage medium can be increased compared to the past.

[Embodiment] FIG. 1 is a diagram showing an embodiment in which the present invention is applied to an electronic still camera. This electronic still camera consists of an electronic still camera main body l as a main body of the device, and a storage medium or card memory 2 that is removably loaded into the electronic still camera main body l. is an imaging section 3 that photoelectrically converts an image of a subject, a processing section 4 that inputs a signal from this imaging section 3 and separates it into a luminance signal and a color signal, and this processing section 4.
The storage unit 5 stores separated signals from...

The imaging section 3 is configured as follows. 31 is a source oscillator that generates a clock signal, and the clock signal generated by this source oscillator 31 is used as a synchronization signal generation S (S, S
, G) 32, this synchronization signal generator 32
generates synchronization signals and sampling pulses, and connects the imager driver 33 and sampling hold circuit (S/
H) Supply to 35. The imager driver 33 generates a drive signal from the clock signal and drives the imager 34. The sampling and holding circuit 35 receives the sampling pulse from the synchronizing signal generator 32, samples the image signal supplied from the imager 34, and holds the value.

The process section 4 is set to Hi as follows. Reference numeral 41 denotes a low-pass filter (LPF) that performs low-pass filtering on the signal from the imaging section 3, and the passed signal is input to the YC separator 42. This YC separator 42 separates a signal consisting of a luminance signal Y corresponding to the brightness of the subject and a color signal C corresponding to the hue superimposed on this luminance signal into a luminance signal Y and two color difference signals R-Y, Separate into B-Y component signals. The separated color difference signals R-Y, B
-Y is a white balance circuit (W B ) 43a, 4
After the white signal is properly adjusted by 3b, the γhli positive device 44a.

44b, the error is appropriately corrected. Also YC minute M
The luminance signal Y separated by S42 is sent to the γ corrector 44c.
After the error is appropriately corrected by the white clipper 45, the amplitude of the white signal is limited by the white clipper 45.

The storage unit 5 is configured as follows. Reference numeral 51 denotes a line sequential device that converts the color difference signals outputted from the γ correctors 44a and 44b of the process section 4 into a line sequential mode. A clock generator 52 generates a first rate clock signal 1'l corresponding to the luminance signal Y and a second rate clock signal r2 corresponding to the color signal C.

The first A/D converter 53 receives the first rate clock signal f'l from the -2 clock generator 52, samples the luminance signal, and performs analog/digital conversion. The second A/D converter 54 receives the second rate clock signal r2 from the clock generator 52, and the line sequential unit 51. The output signal is sampled and analog/digital conversion is performed. The above first and second A
The outputs of the /D converters 53 and 54 are sequentially stored in a first memory area 55a for storing luminance signals and a second memory area 55b for storing color signals of the main memory 55, respectively. The rate converter 2g5B reads out the signals stored in the main memory 55 at a third rate that commonly corresponds to the luminance signal Y and the color signal C as signals in a series manner by time-series combination, and converts the signals stored in the main memory 55 into the card memory as a storage medium. Output to 2. The memory controller 57 controls the operation of the clock generator 52 so as to extract a signal portion corresponding to an effective screen from among the component signals inputted to the first and second A/D converters 53 and 54. ing. Also, the memory controller 57 is the main memory 55
and controls the storage of the card memory 2.

Note that the clock signal "l" corresponding to the luminance signal Y supplied from the lock generator 52 to the first A/D converter 53 is
The color signal C is a clock signal with a frequency of 10.7 MHz, which is slightly higher than twice the band of 4.2 MHz of the luminance signal Y, and is supplied to the second converter 54; (i: This is a clock signal with a much higher frequency of 3.58 MHz than twice the frequency band of C.
The operation of extracting the q video screen, that is, the main area, will be explained with reference to the drawings.

FIG. 2(a) shows the first and second A/D converters 53, 5.
FIG. 4 is a diagram showing signals in one horizontal scanning period (1H) manually inputted in FIG. This one horizontal scanning period (IH) consists of a horizontal blanking period (HBL) during which a horizontal synchronizing signal and a burst signal are inserted, and a video signal period corresponding to the above-mentioned effective screen.

If the sampling frequency is 14.3MHz here,
One horizontal scanning period (IH) is 91ocLK (clock), and the video signal period corresponding to the above effective screen is 760C.
Becomes LK. In addition, FIG. 2(b) shows one vertical scanning period (1v
) That is, it is a diagram showing a signal for one field.

As shown in the figure, one vertical scanning period 1v is 262°5H,
The video signal period is 242H. Thus, Figure 2 (C)
As shown in the figure, the memory area required to store one field's worth of effective screen is a memory area obtained by multiplying the horizontal scanning period 760CLK by the vertical scanning period 242H, that is, the main area P. However, the area of commonly used memory is determined based on binary digital signals, so
The memory that can store the above blind video screen is 7HCLKx
A memory with a 250H memory area will be used.

In order to extract the above-mentioned blind video screen (main area P), the memory controller 57 generates a control signal having the timing shown in FIG. 3 to control the operation of the clock generator 52.

That is, the memory controller 57 detects the horizontal synchronizing signal B from the horizontal scanning signal A, and the rising time t! of this horizontal synchronizing signal B! Control signals C and D are sent out at time t2, which is delayed by 150 CLK, and at time t3, which is further delayed by 760 CLK from this time. Therefore, the clock generator 52 uses the control signal C
. 54.

FIG. 4 is a diagram showing a specific configuration of the rate converter 5G. Reference numerals 59a and 59b are IH memories that store the effective screen of one horizontal scanning period, the input terminals of which are commonly connected to the luminance signal line 58 that inputs the luminance signal Y read from the first memory area 55a; Its output end is Y
It is connected to the C multiplex switch 60. Same < 62a
, 82b is an IH that stores a video screen of one horizontal scanning period.
A memory whose input terminal is connected to the second memory area 55.
Color signal line 6 for manually inputting the color signal read from b
1 in common, and the output ends are respectively connected to a YC multiplex switch 60. Here, the IH memory 59a,
59b is a first rate) (10,7 MHz) which is alternately controlled for writing by a clock signal 1'l, and read by a 4/3 times compressed third rate (14,3 MHz) clock signal r3, It is output to the YC multiplex switch 80. In addition, writing to the IH memory [i2a, 62b is alternately controlled by a clock signal r2 of a second rate (3, 58 MHz), and read is controlled by a clock signal r3 of a third rate (14, 3 MHz) compressed by 4 times. ,
It is output to the YC multiplex switch 60.

The YC multiplex switch 60 outputs the third rate (14.3MHz) luminance signal from the IH memories 59a and 59b and the IH
The third rate color signals from the memories 62a and 62b are multiplexed and output as an IH serial signal. Here, the contents of the IH memory 59a and the IH memory 82a are multiplexed in series at the third rate to form an IH YC multiplexed signal, and an IH
YC multiplexes the contents of the memory 59b and the IH memory 62b into a series at a third rate and creates an IH.
The multiplexed signal is alternately switched and output.

The sub information signal converter 7 is configured as follows. 71
is a shutter trigger switch for operating the shutter provided on the camera body l.

A trigger operation counter 72 counts the number of times the shutter trigger switch 71 is turned on. This trigger operation counter 72 is linked to the shutter, and normally a 5-bit counter is used.

Therefore, this trigger operation counter 72 counts information on the number of times of shutter operation using 5 bits, that is, up to 32 times at the maximum, and outputs the information as a count signal.

The imager identification signal 73 is a PAL system or a SECAM system.

The image is output from an image 134 that identifies different types of the NTSC system. The character generator operation section 74 is, for example, a title.

It is used to input information such as characters and symbols such as dates. The character generator 75 generates character signals such as mouthpieces by operating the character generator operating section 74. This character signal, the imager identification signal and the count signal are mixed and input to the multiplexing circuit 7B as a mixed signal. The output signal of the character generator 75 is timing-controlled by a control signal from the memory controller 57, and is output only for a certain period of time. This timing control is similar to the timing control in the effective screen area P described above, and will be explained based on FIG. 2.

In FIG. 2(C), the memory area of card memory 2 for the effective screen for 1 field is 768 CL K
256H - 198608 bytes. From this memory area to the effective screen area P (780X242-18392
The area after subtracting 0 bytes) is 788CLK x 14H (
10752 bytes) and 8CLK x 242H
(1936 bytes).

That is, in order to effectively utilize the area Q and area R as the sub-storage areas, the character signal.

An imager identification signal and a count signal are inserted into these areas Q and R. The insertion timing of these three signals is 14H period before the video signal period in one vertical period as shown in FIG. 2(b) for area Q. Therefore, the aforementioned three signals are outputted to the multiplexing circuit 76 in response to the control signal from the memory controller 57 only during the 14H period before the video signal period. Regarding region R, as shown in FIG. 2(a), the period is 8 CLK before the video signal period in <1 horizontal period. Therefore, the above three signals are transmitted to the multiplexing circuit 76 in response to the control signal from the memory controller 57 only during the 8CLK period before the video signal period in one horizontal period.
This is what will be output.

The multiplexing circuit 76 multiplexes the video signal from the rate converter 56 and the above-mentioned mixed signal and outputs it to the card memory 2. The card memory 2 consists of a main memory area 21 and a sub memory area 22.
1 stores video signals of main area P corresponding to two series of effective screens, and sub memory area 22 stores area Q for sub information signals.
and the total sum of area R is stored.

Next, the operation of the electronic still camera of this embodiment configured as described above will be explained. First, in the imaging section 3, a synchronization signal is generated from a synchronization signal generator 32 based on a clock signal generated from an original oscillator 31, and an imager 34 is driven by an imager driver 33 that responds to this signal. The captured image of the limb is photoelectrically converted into an image signal, and this image signal is output to the sampling and holding circuit 35. In the sampling and holding circuit 35, the image signal is sampled and held and outputted to the processing unit 4.

In the process section 4, the image signal is low-pass filtered by a low-pass filter 41, and then a YC separator 42 produces a luminance signal Y and two color difference signals R-Y, B.
-Y, that is, separated into component signals. The luminance signal Y is γ-corrected by the γ-corrector 7Q 44 c, and the amplitude of the white signal is limited by the white clipper 45 before being output to the storage unit 5. Also, the color difference signal R-Y
and the color difference signal B-Y are each sent to a white balance circuit 43a.

After the white balance is adjusted by 43b and γ correction is performed by γ correctors 44a and 44b, the signals are output to the storage unit 5.

In the storage unit 5, the clock generator 52 operates in response to a control signal (C, D in FIG. 3) instructing image extraction from the memory controller 57, and the first and second A/D converters 53, 54 control the operation. Therefore, the luminance signal Y is the first
The clock signal f of the first rate (to, 7 MHz) from the clock generator 52 is input to the A/D converter 53 of
Only the area corresponding to the effective screen is sampled with l,
After being converted into a digital signal, it is written into the first memory area 55a of the main memory 55. In addition, the color signal is sampled only in the area corresponding to the effective screen by the second rate (3.58 MHz) clock signal r2 from the clock signal generator 52 in the second A/D converter 54, and converted into a digital signal. After that, it is written into the second memory area 55b of the main memory 55.

Next, the luminance signal Y stored in the first memory area 55a of the main memory 55 is sequentially read out using a 10.7 MHz clock signal and inputted to the rate converter 56.

The luminance signal input to the rate converter 5B is stored in the IH memory 59a as shown in F in FIG.
Then, the luminance signal Y2 is sequentially and alternately written to the IH memory 59b at the first rate (10.7 MHz) for each IH. Furthermore, the color signal stored in the second memory area 55b of the main memo 1J55 has a frequency of 3.58MHz.
The data is read out at the rate and input to the rate converter 5B. The color signal input to the rate converter 5B is 6 in FIG.
As shown in the figure, the color signal (R-Y) is stored in the IH memory 62a.
1. The color signal (B-Y) 2 is sequentially written into the IH memory 62b at the second frequency (3, 58 MHz).

Next, the luminance signal Yl written in the IH memory 59a and the luminance signal Y2 written in the IH memory 59b are as shown in J of FIG.
The signals are sequentially and alternately read out at a third rate (14.3 MHz) compressed three times. Also, the color signal (RY) 1. written in the IH memory 62a. The color signal (R-Y) 2 written in the IH memory 82b is the second color signal (R-Y) as shown in K in FIG.
The first rate (3.58 MHz) is sequentially and alternately read out at a third rate (14.3 MHz) which is compressed four times.

Then, the luminance signal Yl and color signal (R-Y)l read from the IH memories 59a and 62a are set to the same level by the yc multiplier switch 60 as shown in FIG.
3MHz) IH series signal. Similarly, the luminance signal Y read out from the IH memories 59b and 82b
2 and color signal (B-Y) 2 are YC multiplex switch 60
As a result, the signals are multiplexed into a series signal as shown at the bottom of FIG. These selectively switched and multiplexed signals are Yl
, (RY) 1.

Y2. (B-Y)2... is transferred to the multiplexing circuit 7B as a series signal.

On the other hand, in the sub information signal converter 7, the imager 34 generates an imager identification signal 73 of different types such as PAL system, NTSC system, etc., and the shutter trigger switch 71 is turned on, and the trigger operation counter 72 indicates the number of shutter operations. is counted and output as a count signal. Furthermore, the character generator operation section 74
When character information such as a kiss, a title, etc. is inputted, a character signal is generated by the character generator 75. The character signal, the imager identification signal, and the count signal are mixed, and these three signals together receive a control signal from the memory controller 57. The mixed signal is output to the multiplexing circuit 76 only during the 14H period before the video period of the l vertical scanning period shown. Regarding the region R shown in FIG. 2(C), the mixed signal is output to the multiplexing circuit 7G only during the 8 CLK period before the video signal period in the 1 horizontal scanning period shown in FIG. 2(a). Therefore, the video signal from the rate converter 56 and the character signal,
A mixed signal consisting of an imager identification signal and a count signal is multiplexed by a multiplexing circuit 7G and transferred to the card memory 2. Then, under the control of the memory controller 57,
The video signal corresponding to the effective screen is written into the main memory area 21 of the card memory 2, and the character signal, count signal, and imager identification signal, which are the sub information signals, are written into the sub memory area 22.

As described above, according to this embodiment, the imaging unit 3. Process section 4. The storage unit 5 extracts and processes the area P corresponding to the effective screen from the video signal, and supplies it to the range of the main memory area 21 of the card memory 2 . Further, the sub information converting means 7 obtains sub information signals other than the video signal, that is, an imager identification signal, a count signal, and a character signal, and supplies them to the sub memory area 22 of the card memory 2. As a result, the main memory area 21 and the sub memory area 22 of the card memory 2 are fully used by the video signal (luminance signal and color difference signal) and the sub information signal, so that the card memory 2 can be used more efficiently. .

Note that the present invention is not limited to the embodiments described above. For example, in the embodiment described above, three signals, the imager identification signal, the count signal, and the character signal, are used as the sub information signals, but it is also possible to use only the character signal, for example. It goes without saying that various other modifications can be made without departing from the spirit of the present invention.

[Effects of the Invention] According to the present invention, the a video screen corresponding portion of the video signal is extracted and processed so as to fit within the range of at least one main area set for the applied storage medium. main information signal converting means for supplying the main information signal to the main area; and converting a sub information signal other than the video signal to fit within the range of at least one sub area set for a portion of the storage medium other than the main area. and a sub-information conversion means for supplying this to the sub-area, so that the main memory area corresponding to the effective screen in the storage medium and the sub-memory area other than the memory area corresponding to this effective screen are , it is possible to provide a signal conversion system that can store different pieces of information and can fully utilize the storage medium in nine ways.

[Brief explanation of the drawing]

1 to 5 are diagrams showing an embodiment in which the present invention is applied to an electronic still camera. FIG. 1 is a schematic configuration diagram of the electronic still camera, and FIGS. Explanatory diagram of effective screen extraction means and means for multiplexing sub information signals, third
The figure is a diagram showing the timing of the extraction operation of the same valid screen.
The figure is a schematic configuration diagram of the rate converter, and FIG. 5 is a diagram showing the operation timing of the rate converter. ■...Electronic still camera body, 2...Card memory, 3...Imaging section, 4...Processing section, 5...Storage section, 7...Sub-information signal conversion section, 21. ...Main memory area, 22...Sub memory area, 31...Original oscillator, 3
2... Synchronization signal generator (S, S, G), 33...
Imager driver, 34... Imager, 35...
・Sampling hold circuit (S/H), 41...
Low pass filter (LPF), 42... YC separator, 43
a, 43b... White balance circuit (W B
), 44a, 44b, 44cm7 corrector, 4
5 - White clip device, 51... Line sequential device, 5
2... Clock generator, 53... First A/D converter, 54... Second A/D converter, 55... Main memory, 55a... First memory area , 55b...
Second memory area, 58... Rate converter, 57...
・Memory controller, 58... Brightness signal line, 59a
, 59b, 82a, 82b-IH memory, 60...YC multiplex switch, 61...color signal line, 63...signal line, 71...shutter trigger switch, 72...trigger operation counter , 73... Imager identification signal, 74... Character generator operation section, 75... Character generator, 76...
Multiplexing circuit. Applicant's agent Patent attorney Jun Tsuboi Figure 4 Figure 5

Claims (1)

[Claims] main information signal converting means for extracting and processing an effective screen corresponding part of the video signal so as to fit within the range of at least one main area set for the applied storage medium and supplying it to the main area; and a sub-information signal other than the video signal to fit within the range of at least one sub-area set for a portion of the storage medium other than the main area, and to supply the sub-information signal to the sub-area. A signal conversion system comprising: information conversion means.