JP2002258814A - Liquid crystal drive device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease a circuit scale to the utmost and to drive a liquid crystal display panel, without causing disorder of the color balance of an image. SOLUTION: This device is equipped with a parallel/serial conversion circuit 34, which performs the pixel-by-pixel parallel/serial conversion of digital image data, circuits 35 and 36 which process the image data obtained by the parallel/ serial converting circuit 34 by γ-correction and A/D conversion, and a serial/ parallel conversion circuit composed of sample and hold circuits 37 to 39, which performs the serial/parallel conversion of the image data processed by those circuits and AND circuits 41 to 43.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device suitable for a circuit for producing display data from digital image data with a digital camera and displaying the data on a liquid crystal finder.

[0002]

2. Description of the Related Art For example, display data is created from digital data of an image obtained by imaging with a digital camera or digital data of an image read from a recording medium, and a TF is created.
FIG. 8 shows a general configuration of a video encoder circuit mainly for displaying on a liquid crystal finder constituted by a T liquid crystal display panel.

In FIG. 1, reference numeral 10 denotes a video encoder circuit, and luminance / color difference type image data (YUV) is 4: 2: 2.
After the chrominance signal (U, V) is interpolated by the / 4: 4: 4 interpolation circuit 11 to have the same information amount as the luminance signal (Y),
While being sent to the YUV / RGB conversion circuit 12, each component is also sent to low-pass filters (LPF) 13a to 13c.

[0004] The low-pass filter 13a limits the bandwidth of the luminance signal to 4.2 [MHz] and outputs the same.
After being added to the horizontal synchronizing signal from No. 5, the signal is sent to the adder 16.

The low-pass filter 13b restricts the bandwidth of the wideband color difference signal (U) to 1.5 [MHz] and outputs the same.
Are superimposed on the chrominance subcarrier signal from the chrominance subcarrier (Fsc) oscillator 18 and sent to the adder 19.

The low-pass filter 13c limits the bandwidth of the narrow-band chrominance signal (V) to 0.5 [MHz] and outputs the narrow-band chrominance signal (V).
Are superimposed on the chrominance subcarrier signal from the chrominance subcarrier oscillator 18 and sent to the adder 19.

[0007] The carrier chrominance signal, which is the addition output of the adder 19, is superimposed on the color burst signal from the burst oscillator 22 by the multiplier 21 and then sent to the adder 16.

An adder 16 outputs a video signal of a predetermined television system (in this case, NTSC system) by adding a luminance signal on which a horizontal synchronizing signal is superimposed and a carrier chrominance signal on which a color burst signal is superimposed. I do.

The video signal output from the adder 16 is converted into an analog signal by the D / A converter 23 to obtain an analog video signal, which is output from an external connection terminal (not shown) outside the video encoder circuit 10.

On the other hand, the YUV / RGB conversion circuit 12
Converts the 4: 4: 4 luminance / color difference image data (YUV) into primary color image data (RGB) by a matrix operation.

The image data thus obtained is subjected to gamma correction corresponding to the gamma characteristic of a TFT liquid crystal panel as a display element by gamma correction circuits 24a to 24c for each color component, and then to a D / A converter 25a to 25c, the analog T
It is sent to the FT interface (I / F) 26.

It should be noted that 27 in the video encoder circuit 10
Is a video timing signal oscillator, and a composite synchronization signal C
SYNC and a reference clock CLK are provided, and a timing signal necessary for each circuit in the video encoder circuit 10 is generated.

The analog TFT interface 26 receives an analog image signal RG from the video encoder circuit 10.
Based on B, a signal electrode and a scanning electrode of a TFT liquid crystal panel (not shown) are driven to display an image.

FIG. 9 shows signals input and output by the video encoder circuit 10 and the analog TFT interface 26. As described above, the video encoder circuit 10 is provided with the luminance / color difference image data YUV, the composite synchronization signal CSYNC, and the reference clock CLK, thereby generating and outputting an analog video signal and an image signal RGB.

The analog TFT interface 26 receives the image signal RGB and a frame rate pulse FR based on the frame rate of the TFT liquid crystal panel to be driven.
The display data RGB is generated by P and transmitted to the TFT liquid crystal panel.

As a pixel configuration of a TFT liquid crystal panel to be driven, for example, as shown in FIG. 10, pixels are arranged in a matrix in a vertical and horizontal direction, and the color components RGB of each pixel are vertical. As shown in FIG. 11, pixels having a stripe pattern common to the lines, pixels are arranged with a shift of a half pixel for each horizontal line, and three pixels For example, there is a delta pattern in which one pixel RGB is arranged in a triangular shape, and the analog TFT interface 26 supplies display data RGB to its signal electrode corresponding to the pixel arrangement of the TFT liquid crystal panel.

Therefore, an analog TF for supplying display data to a TFT liquid crystal panel having such a pixel configuration is provided.
The T interface 26 has D / A converters 25a to 25c.
Image signals RGB are input at the same timing in a temporally dense state, whereas it is not necessary to output the display data RGB to the TFT liquid crystal panel at the same timing, and each color component R, G, B may be sequentially selected and output in a time-sharing manner.
Will fall.

[0018]

In the configuration shown in FIG. 8, the gamma correction circuits 24a to 24c and the D / A converter 25
a to 25c, three identical circuit configurations are required according to the image data RGB.
This is one factor in alienating the reduction of the circuit scale to zero.

In addition, the D / A converters 25a to 25c, which convert digital data into analog data, may have slightly different analog signal levels due to individual differences. The level of the signal may vary, and the color balance of the image displayed on the subsequent TFT liquid crystal panel may be lost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to drive a liquid crystal display panel without reducing the circuit scale as much as possible and maintaining the color balance of an image. It is an object of the present invention to provide a liquid crystal driving device capable of performing the above.

[0021]

According to the first aspect of the present invention,
What is claimed is: 1. A liquid crystal driving device for generating display data for driving a liquid crystal display panel from parallel image data provided in parallel, comprising: a parallel / serial conversion means for converting the parallel image data into serial image data; It is characterized by comprising processing means for performing predetermined processing on the serial image data obtained by the conversion means, and serial / parallel conversion means for converting the serial image data processed by the processing means into parallel image data.

With this configuration, the processing means can be configured by one system, which can contribute to a reduction in circuit scale.

According to a second aspect of the present invention, there is provided a liquid crystal driving apparatus for generating display data for driving a liquid crystal display panel from parallel image data given in parallel, wherein the parallel image data is defined as an original transfer rate. Transfer rate conversion means for converting data having different transfer rates, parallel / serial conversion means for converting parallel image data obtained by the transfer rate data into serial image data, and serial image data obtained by the parallel / serial conversion means Serial / parallel conversion means for converting data into parallel image data.

With this configuration, the sampling frequency of the input image data is converted into a required value, then converted into serial data, and then converted back to parallel, thereby simplifying the timing control of each circuit. And the number of input / output terminals can be reduced.

According to a third aspect of the present invention, there is provided a liquid crystal driving apparatus for generating display data for driving a liquid crystal display panel from parallel image data provided in parallel, wherein the parallel image data is converted into serial image data. Parallel / serial conversion means, serial / parallel conversion means for converting serial image data obtained by the parallel / serial conversion means into parallel image data, and an operation clock of the parallel / serial conversion means to the serial / parallel conversion means. 1 / N of frequency (N is a natural number)
Clock supply means for supplying an operation clock having the frequency of

With such a configuration, not only can the timing control of each circuit be simplified, but also the clock supply means can convert the number of pixels corresponding to the liquid crystal display panel and the liquid crystal display panel. Transfer rate conversion corresponding to the driving frequency can be easily realized.

According to a fourth aspect of the present invention, in the first aspect of the invention, the parallel image data is digital image data, and the processing means performs at least one of a gamma correction process and a digital / analog conversion process. It is characterized by the following.

With such a configuration, in addition to the operation of the first aspect of the present invention, the circuit scale required for at least one of the gamma correction processing and the digital / analog conversion processing can be reduced, and in particular, the digital / analog conversion can be performed. With a processing circuit that performs processing, the level of image data does not differ for each color component, and the liquid crystal display panel can be driven with a correct image color balance.

According to a fifth aspect of the present invention, in the first or third aspect of the present invention, the parallel image data is converted into data having a transfer rate different from the original transfer rate before the parallel / serial conversion means. And a transfer rate converting means.

With this configuration, in addition to the operation of the first or third aspect of the present invention, the sampling frequency of the input image data is converted into a required value and then converted into a serial value. By returning to parallel, the timing control of each circuit can be simplified.

According to a sixth aspect of the present invention, in the second or fifth aspect of the present invention, the transfer rate conversion means comprises:
The parallel image data is converted into data having a transfer rate corresponding to a drive frequency of a liquid crystal display panel to be driven.

With this configuration, in addition to the effect of the second or fifth aspect of the present invention, in particular, processing is performed on image data having a sampling frequency corresponding to the driving frequency of the liquid crystal display panel to be driven. Therefore, it is possible to contribute to a reduction in the scale of the encoder circuit without significantly changing the liquid crystal drive driver circuit.

According to a seventh aspect of the present invention, in the first aspect of the present invention, the serial / parallel conversion means operates with an operation clock corresponding to a driving frequency of a liquid crystal display panel to be driven. It is characterized by the following.

With such a configuration, in addition to the operation of the invention described in any one of claims 1 to 3, in particular, the serial / parallel conversion means near the liquid crystal display panel is operated using the same operation clock. Therefore, it is possible to contribute to a reduction in the scale of the encoder circuit without significantly changing the liquid crystal drive driver circuit.

According to an eighth aspect of the present invention, in the first aspect of the present invention, the serial / parallel conversion means is a sample and hold means.

With such a configuration, in addition to the operation of the invention described in any one of the first to third aspects, means for performing serial / parallel conversion can be realized with a simple circuit configuration, and the circuit scale as a whole can be realized. Can be reduced.

According to a ninth aspect of the present invention, in the second or fifth aspect, the transfer rate conversion means, the parallel / serial conversion means, and the serial / parallel conversion means are operated by operating clocks having the same frequency. It is characterized by.

With such a configuration, in addition to the operation of the invention described in claim 2 or 5, the timing control of the entire circuit of the device can be further simplified.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) The present invention will be described below.
A first embodiment in which the present invention is applied to a liquid crystal driving device that creates display data for a liquid crystal finder composed of a T liquid crystal display panel will be described with reference to the drawings.

FIG. 1 shows the circuit configuration, in which the input image data is, for example, 27 [MHz] or its 1/27.
2 is generated based on the 13.5 [MHz] operation clock, the operation clocks of the same frequency are output from the pixel number conversion circuit 31, the YUV / RGB conversion circuit 32,
And an operation clock of an arbitrary frequency corresponding to the driving frequency of the TFT liquid crystal display panel to be driven by this device, the sampling conversion circuit 33, the parallel / serial conversion circuit 34, the γ correction circuit 35, D / A converter 36, sample and hold circuits (SH) 37 to 39, analog TFT interface 4
0, and are provided to AND circuits 41 to 43.

This pixel number conversion circuit 31 converts the size (the number of constituent pixels) of the luminance / color difference image data YUV input to the device into a value corresponding to the TFT liquid crystal display panel to be driven, and converts the YUV / YUV data. Output to the RGB conversion circuit 32.

At this time, if the input image data YUV is 4: 2: 2, the pixel number conversion circuit 31
Is thinned out at twice the rate of the pixel data of the color difference signals U and V, thereby obtaining 4: 4: 4 image data corresponding to the size of the TFT liquid crystal display panel.

The YUV / RGB conversion circuit 32 converts the luminance and chrominance image data YUV into primary color image data RGB by a matrix operation and outputs the converted data to the sampling conversion circuit 33.

The sampling conversion circuit 33 has the function
27 [MH] based on one operation clock
z] or 1/2 of the image data RGB synchronized with the operation clock of 13.5 [MHz], the bit rate of the image data RGB is set so as to be synchronized with the operation clock of an arbitrary frequency (the driving frequency of the TFT liquid crystal display panel). Transfer rate).

Then, the image data RGB whose bit rate is converted for display by the sampling conversion circuit 33 is displayed.
Is converted into serial data continuous with R, G, B, R, G, B,... On a pixel basis in a time division manner by the parallel / serial conversion circuit 34 and output.

That is, since the parallel / serial conversion circuit 34 sequentially selects the image data RGB in a time-division manner in pixel units based on the operation clock of the liquid crystal driving frequency, as a result, the input image data amount is reduced. This means that it has been reduced to 1/3.

The pixel-unit (serial) image data output from the parallel / serial conversion circuit 34 is subjected to γ correction corresponding to the γ characteristic of the TFT liquid crystal display panel as a display element by the γ correction circuit 35. D / A converter 36
Are converted into analog signals by the sample hold circuits 37 to 39.
Sent to

The sample hold circuits 37 to 39
Sample and hold the analog image signal output from the D / A converter 36 in accordance with the gate signals from the AND circuits 41 to 43, and store the held content in the analog TF
Output to the T interface 40.

Here, the AND circuits 41 to 43 are sequentially turned on by the serial timing signals Sr, Sg, and Sb using the operation clock of the liquid crystal driving frequency as a reference clock, and apply gate signals to the sample and hold circuits 37 to 39. Are sent out. As a result, serial / hold circuits 37-39 and AND circuits 41-43
It constitutes a parallel conversion circuit.

The sample-and-hold circuit 37 converts the image signal of the pixel of the color component R into a sample-and-hold circuit 38.
Represents the image signal of the pixel of the color component G, and the sample and hold circuit 39 holds the image signal of the pixel of the color component B, and outputs the signals to the analog TFT interface 40. At this time, the serial timing signals Sr, Sg, The image data input to the analog TFT interface 40 by Sb is sequentially selected in a time division manner for each of the color components R, G, and B in pixel units.

Therefore, the analog TFT interface 40 receives the image signal RG sent in a time-sharing manner
B are sequentially acquired at the same timing as the selection, and the signal electrodes and the scanning electrodes of the TFT liquid crystal panel (not shown) are driven to display an image.
A configuration substantially similar to that of the FT interface 26 can be used.

With such a configuration, the γ correction circuit 35
And the processing circuit including the D / A converter 36 can be configured by one system, which can contribute to reduction in the scale of the entire circuit.

In addition, since the digital / analog conversion processing is one system and all the image data RGB are converted to analog only by the D / A converter 36 in a time-division manner, the obtained image signal RGB is subjected to D / A conversion. The TFT liquid crystal display panel at the subsequent stage can be driven with a correct image color balance without variation due to individual differences of the device 36.

In the above embodiment, for example, 27 [MHz] or 27 [MHz] corresponding to the processing frequency of the image data input as the operation clock to the pixel number conversion circuit 31, the YUV / RGB conversion circuit 32, and the sampling conversion circuit 33. A half of 13.5 [MHz] is supplied,
On the other hand, a sampling conversion circuit 33, a parallel / serial conversion circuit 34, a gamma correction circuit 35, a D / A converter 36, sample and hold circuits (SH) 37 to 39, an analog TFT
The interface 40 and the AND circuits 41 to 43 have been described as being supplied with an operation clock of an arbitrary frequency corresponding to the drive frequency of the TFT liquid crystal display panel to be driven by this device. If the device can be shared, the sampling conversion circuit 33 becomes unnecessary.

The pixel number conversion circuit 31 is provided for the case where the size (the number of constituent pixels) of the input image data YUV is indefinite, and is configured in advance of the constituent pixels of the TFT liquid crystal display panel to be driven. If the image data YUV corresponding to the number is input, the pixel number conversion circuit 31 is not required.

Although FIG. 1 has been described assuming that the analog image signals RGB are sequentially and selectively input to the analog TFT interface 40 in a time-division manner, they may be simultaneously input to the analog TFT interface 40. Good.

FIG. 2 shows another example of such a circuit configuration according to the present embodiment, which is basically the same as FIG. 1 described above. Omitted.

The sample and hold circuits 37, 3
8, sample and hold circuits 44 and 45 are provided between the analog TFT interface 40 and the subsequent stages.

The sample and hold circuits 44 and 45
The sample and hold circuits 37 and 38 simultaneously sample and hold the image signal of the analog value output and held by the sample and hold circuits 37 and 38 in the same manner as the sample and hold circuit 39 in the same manner as the above-mentioned sample and hold circuit 39.
Output to the interface 40.

With this configuration, the image signals of the pixels of the color components R and G which are held and output by the sample and hold circuits 37 and 38 are used as the sample and hold circuits 39 which hold the image signals of the pixels of the color component B. The image signals of the R, G, and B pixels of the sample and hold circuits 44, 45, and 39 are simultaneously output to the analog TFT interface 40.

Accordingly, the analog TFT interface 40 collectively acquires the image signals RGB sent at the same timing in this manner, and a T
The image signal is displayed by driving the signal electrode and the scanning electrode of the FT liquid crystal panel, and can be dealt with by the same configuration as the analog TFT interface 26 shown in FIG.

(Second Embodiment) The second embodiment in which the present invention is applied to a liquid crystal driving device for generating display data for a liquid crystal finder comprising a TFT liquid crystal display panel from digital image data in a digital camera will be described below. An embodiment will be described with reference to the drawings.

FIG. 3 shows the circuit configuration. The basic configuration of each circuit is the same as that shown in FIG. 1, and therefore, the same portions are denoted by the same reference characters and description thereof is omitted. I do.

Here, if the input image data is generated based on an operation clock of, for example, 27 [MHz], the operation clock of the same frequency is converted to the pixel number conversion circuit 31 by the YUV / RGB conversion. Circuit 32,
And to the parallel / serial conversion circuit 34,
27 [MHz], 13.5 [MHz], 6.75 [MH] corresponding to 1/1, 1/2, and 1/4 of the clock frequency.
z], the γ correction circuit 35 and the D / A
Converter 36, AND circuits 41 to 43, and analog TF
When supplied to the T interface 40, the TFT liquid crystal display panel to be driven is also driven by one of them.

In this case, if the image data of the original digital value is generated by the operation clock of 27 [MHz] as described above, the display time per pixel is adjusted according to the standard in the video display area. Is 52.06 [μse
c / pixel], so that 52.06 [μsec / pixel]
× 27 [MHz] = approximately 1406, but here, for convenience of the frequency, a description will be given based on 1408 pixels as a multiple of 4.

That is, when the number of horizontal pixels of the TFT liquid crystal display panel to be driven is within the range of 1408 to 705, the operation clock of 27 [MHz] is used and the number of horizontal pixels is within the range of 704 to 353. Sometimes 13.
An operation clock of 5 [MHz] and 6.75 [MH] when the number of horizontal pixels is within the range of 352 to 177.
z] is selected and used,
The operation can be performed by covering the difference in the number of horizontal pixels of the TFT liquid crystal display panel to be driven with operation clocks of three different frequencies.

As described above, in the first embodiment,
An operation clock of an arbitrary frequency corresponding to the drive frequency of the TFT liquid crystal display panel to be driven is supplied to each circuit subsequent to the sampling conversion circuit 33 and the parallel / serial conversion circuit 34 to operate. In the second embodiment, each circuit subsequent to the parallel / serial conversion circuit 34 is operated by an operation clock selected on the device side, which is an RGB encoder.

Therefore, the sampling conversion circuit 33 shown in FIG. 1 can be omitted, and the pixel number conversion circuit 31 can easily obtain image data necessary for display by thinning out pixels at a simple ratio. And the configuration can be simplified.

In this case, the pixels are inevitably thinned out because the operation clock of each circuit downstream of the parallel / serial conversion circuit 34 is slow rather than being thinned out by the pixel number conversion circuit 31. The transfer rate is also slow.

In addition, the timing of each circuit constituting the device can be easily controlled, and the number of operation clock terminals can be reduced even in the case where an LSI chip is considered.

In FIG. 3, the image signals RGB of the analog value are sequentially and selectively inputted to the analog TFT interface 40 in a time-division manner. However, these may be inputted to the analog TFT interface 40 at the same time. .

FIG. 4 shows another example of such a circuit configuration according to the present embodiment, which is basically the same as FIG. 3 described above. Omitted.

As in the case of FIG. 2, the sample hold circuits 44 and 45 are connected between the sample hold circuits 37 and 38 and the analog TFT interface 40 at the subsequent stages.
Is provided.

The sample and hold circuits 44 and 45
The sample and hold circuits 37 and 38 simultaneously sample and hold the image signal of the analog value output and held by the sample and hold circuits 37 and 38 in the same manner as the sample and hold circuit 39 in the same manner as the above-mentioned sample and hold circuit 39.
Output to the interface 40.

In addition, the analog TFT
The interface 40 is also operated by the gate signal output from the AND circuit 43.

With such a configuration, the image signals of the pixels of the color components R and G which are held and output by the sample and hold circuits 37 and 38 are converted into the sample and hold circuits 39 which hold the image signals of the pixels of the color component B. The image signals of the R, G, and B pixels of the sample and hold circuits 44, 45, and 39 are simultaneously output to the analog TFT interface 40.

Therefore, the analog TFT interface 40 collectively acquires the image signals RGB sent at the same timing in this manner, and a T (not shown)
The image signal is displayed by driving the signal electrode and the scanning electrode of the FT liquid crystal panel. Similar to the analog TFT interface 40 shown in FIG.

(Third Embodiment) The third embodiment in which the present invention is applied to a liquid crystal driving device for generating display data for a liquid crystal finder composed of a TFT liquid crystal display panel from digital image data in a digital camera will be described below. An embodiment will be described with reference to the drawings.

In the first and second embodiments, the driver of the TFT liquid crystal display panel to be driven is described as operating with an analog signal using the analog TFT interface 40. However, the third embodiment is not limited to this. In the embodiment, a case in which a digital operation driver is used will be described.

FIG. 5 exemplifies a configuration of a conventional liquid crystal driving device corresponding to a digital operation driver. In the figure, luminance / color difference image data YUV is input to a YUV / RGB conversion circuit 12.

The YUV / RGB conversion circuit 12 converts the input luminance / color difference image data YUV into primary color image data RGB by a matrix operation and outputs it.

The image data RGB output from the YUV / RGB conversion circuit 12 is converted into a γ correction circuit 24a for each color component.
After the γ correction corresponding to the γ characteristic of the TFT liquid crystal panel as the display element is performed at 〜24c, it is sent to the TFT digital interface (I / F) 51.

The TFT digital interface 51 has a γ
Based on the digital value image signals RGB sent from the correction circuits 24a to 24c, a signal electrode and a scanning electrode of a TFT liquid crystal panel (not shown) are driven to display an image.

The YUV / RGB conversion circuit 1
2. Each of the γ correction circuits 24a to 24c and the TFT digital interface 51 has, for example, 27 [MHz].
Alternatively, an operation clock of 13.5 [MHz] having a half frequency thereof is commonly supplied.

In such a circuit configuration, the image data RG
Three gamma correction circuits 24a that perform processing for each color component of B
~ 24c is required, and the circuit scale becomes complicated.

FIG. 6 shows a circuit configuration of a liquid crystal driving device according to the third embodiment of the present invention.
In the figure, the image data YUV of the luminance / color difference system is YUV / RGB.
It is input to the conversion circuit 32.

The YUV / RGB conversion circuit 32 converts the input luminance / color difference type image data YUV into primary color type image data RGB by matrix operation and outputs it to the parallel / serial conversion circuit 34.

The parallel / serial conversion circuit 34 converts the input image data RGB into R,
The data is converted into serial data continuous with G, B, R, G, B, ‥‥, and output to the gamma correction circuit 35.

The gamma correction circuit 35 performs gamma correction corresponding to the gamma characteristic of the TFT liquid crystal display panel, which is a display element, on the image data in pixel units output from the parallel / serial conversion circuit 34, and then performs a TFT digital interface. (I / F) 52.

The TFT digital interface 52 has a γ
The digital value image signal R sent from the correction circuit 35
A signal electrode and a scanning electrode of a TFT liquid crystal panel (not shown) are driven based on GB to display an image.

The YUV / RGB conversion circuit 3
2, parallel / serial conversion circuit 34, gamma correction circuit 3
5 and the TFT digital interface 52 are commonly supplied with an operation clock of, for example, 27 [MHz] or 13.5 [MHz], which is half the frequency thereof.

With such a configuration, the γ correction circuit 35
Can be configured by one system, which can contribute to a reduction in the scale of the entire circuit.

In the configuration of FIG. 6, the number of horizontal pixels of the TFT liquid crystal display panel to be driven is 1408-70.
5, the driving operation is performed using an operation clock of 27 [MHz] when the number of horizontal pixels is within a range of 704 to 353, and an operation clock of 13.5 [MHz] when the number of horizontal pixels is within a range of 704 to 353.

However, a TFT having an arbitrary number of horizontal pixels
When a liquid crystal display panel is to be driven, a liquid crystal driving device having a circuit configuration shown in FIG. 7 may be used instead of the circuit configuration shown in FIG.

In the figure, in addition to the circuit configuration shown in FIG. 6, a pixel number conversion circuit 31 is arranged at a stage preceding the YUV / RGB conversion circuit 32.

The pixel number conversion circuit 31 converts the size (the number of constituent pixels) of the luminance / color difference type image data YUV input to this device into a value corresponding to the TFT liquid crystal display panel to be driven, and then converts the size. YUV / RGB conversion circuit 32
Output to

In this case, if the driving frequency in the subsequent stage is set to 1/2 or 1/4, it cannot be said that the size of the pixel number conversion circuit 31 is converted to a size corresponding to the TFT liquid crystal display panel.

The pixel number conversion circuit 31, YUV /
An operation clock of 27 [MHz] or 13.5 [MHz] is supplied to the RGB conversion circuit 32 and the parallel / serial conversion circuit 34, and the γ correction circuit 35 and the TFT digital interface 52 are provided with 1/1, 1/2 thereof. , Or 1/4 [27 MHz] or 13.5 [MH]
z] or an operation clock of 6.75 [MHz] is supplied.

With such a configuration, the number of horizontal pixels of the TFT liquid crystal display panel to be driven is 1408 to 705.
When the number of horizontal pixels is within the range of 704 to 353, the operation clock of 13.5 [MHz] is used when the number of horizontal pixels is within the range of 704 to 353, and the number of horizontal pixels is 352. When it is within the range of 177 to 177, an operation clock of 6.75 [MHz] is selected and used by the gamma correction circuit 35 and the TFT digital interface 52. The pixel number conversion circuit 31, the YUV / RGB conversion circuit 32, and The parallel / serial conversion circuit 34 also selects and uses the operation clock corresponding to this, so that the difference in the number of horizontal pixels of the TFT liquid crystal display panel to be driven can be covered by the operation clocks of three different frequencies. Can be operated.

As described above, in the third embodiment,
Even if the driver of the TFT liquid crystal display panel operates by a digital signal, the same can be dealt with in the same manner as in the above-described FIG. 1 and the second embodiment.

In the first to third embodiments, it has been described that the liquid crystal display panel to be driven is an active matrix driven TFT liquid crystal, but the present invention is not limited to this. Of course, a liquid crystal display panel driven by a simple matrix such as an STN liquid crystal may be used.

In addition, the present invention is not limited to the above-described first to third embodiments, and can be variously modified and implemented without departing from the gist thereof.

Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features. For example, even if some components are deleted from all the components shown in the embodiments, at least one of the problems described in the column of the problem to be solved by the invention can be solved and the effects described in the column of the effect of the invention can be solved. In a case where at least one of the effects described above is obtained, a configuration in which this component is deleted can be extracted as an invention.

[0104]

According to the first aspect of the present invention, since the processing means can be constituted by one system, it is possible to contribute to a reduction in circuit scale.

According to the second aspect of the present invention, the sampling frequency of the input image data is converted to a required value, then converted to serial, and then returned to parallel, thereby simplifying the timing control of each circuit. And the number of input / output terminals can be reduced.

According to the third aspect of the present invention, not only the timing control of each circuit can be simplified, but also the clock supply means can convert the number of pixels corresponding to, for example, a liquid crystal display panel and the liquid crystal display. Transfer rate conversion corresponding to the panel driving frequency can be easily realized.

According to the fourth aspect of the invention, in addition to the effects of the first aspect of the invention, the circuit scale required for at least one of the gamma correction processing and the digital / analog conversion processing can be reduced. With a processing circuit that performs analog conversion processing, the level of image data does not differ for each color component, and the liquid crystal display panel can be driven with a correct image color balance.

According to the fifth aspect of the invention, in addition to the effects of the first or third aspect, the sampling frequency of the input image data is converted to a required value and then converted to serial. Thereafter, by returning to the parallel state, the timing control of each circuit can be simplified.

According to the sixth aspect of the present invention, in addition to the effects of the second or fifth aspect of the present invention, processing of image data having a sampling frequency corresponding to the driving frequency of the liquid crystal display panel to be driven is particularly performed. Since it can be performed, it is possible to contribute to a reduction in the scale of the encoder circuit without significantly changing the liquid crystal drive driver circuit.

According to the seventh aspect of the invention, in addition to the effects of the first to third aspects, in particular, the serial / parallel conversion means close to the liquid crystal display panel uses the same operation clock. To be able to work,
It is possible to contribute to a reduction in the scale of the encoder circuit without significantly changing the liquid crystal drive driver circuit.

According to the eighth aspect of the present invention, in addition to the effects of the first to third aspects, means for performing serial / parallel conversion with a simple circuit configuration can be realized. This can contribute by reducing the circuit scale.

According to the ninth aspect of the invention, in addition to the effects of the second or fifth aspect of the invention, the timing control of the entire circuit of the device can be further simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing another circuit configuration according to the embodiment;

FIG. 3 is a block diagram showing a circuit configuration according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing another circuit configuration according to the embodiment;

FIG. 5 is a block diagram illustrating a general configuration of a liquid crystal driving device using a TFT digital interface.

FIG. 6 is a block diagram showing a circuit configuration according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing another circuit configuration according to the embodiment;

FIG. 8 is a block diagram showing a configuration of a general video encoder circuit for a liquid crystal display panel and its peripheral circuits.

FIG. 9 is a diagram showing input / output states of signals to / from each circuit in FIG. 8;

FIG. 10 is a diagram illustrating a pixel configuration of a liquid crystal display panel to be driven by the circuits in FIGS. 8 and 9;

FIG. 11 is a diagram illustrating a pixel configuration of a liquid crystal display panel to be driven by the circuits in FIGS. 8 and 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Video encoder circuit 11 ... 4: 2: 2/4: 4: 4 interpolation circuit 12 ... YUV / RGB conversion circuit 13a-13c ... Low-pass filter 14 ... Adder 15 ... Synchronous signal oscillator 16 ... Adder 17 ... Multiplier Reference Signs List 18: Color subcarrier (Fsc) oscillator 19: Adder 20, 21, Multiplier 22: Burst signal oscillator 23: D / A converter 24a to 24c: γ correction circuit 25a to 25c: D / A converter 26: Analog TFT interface (I / F) 27 video timing signal oscillator 31 pixel number conversion circuit 32 YUV / RGB conversion circuit 33 sampling conversion circuit 34 parallel / serial conversion circuit 35 gamma correction circuit 36 D / A converter 37-39 sample hold circuit (SH) 40 analog TFT interface (I / F) 41-43 AND Circuits 51, 52 ... TFT digital interface (I / F)

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 633 G09G 3/20 633H 633P H04N 5/66 102 H04N 5/66 102B F term (Reference) 2H093 NA06 NA51 NA61 NC90 ND06 ND17 ND49 NG20 5C006 AA01 AA11 AA22 AC24 AF25 AF46 AF47 AF72 AF82 AF85 BB16 BC14 BC16 BF11 BF26 FA42 FA43 5C058 AA06 BA01 BA13 BB04 BB05 BB06 BB25 5C080 AA10 BB05 CC02 DD22 GG07 GG07 GG07 GG07 GG07 GG06 GG07 GG07 GG07

Claims (9)

[Claims] 1. A liquid crystal driving device for generating display data for driving a liquid crystal display panel from parallel image data provided in parallel, comprising: a parallel / serial conversion means for converting the parallel image data into serial image data; Processing means for performing predetermined processing on the serial image data obtained by the parallel / serial conversion means; and serial / parallel conversion means for converting the serial image data processed by the processing means into parallel image data. A liquid crystal driving device characterized by the above-mentioned. 2. A liquid crystal driving device for generating display data for driving a liquid crystal display panel from parallel image data provided in parallel, wherein said parallel image data is converted into data having a transfer rate different from an original transfer rate. Transfer rate conversion means for converting; parallel / serial conversion means for converting parallel image data obtained by the transfer rate conversion means into serial image data; serial image data obtained by the parallel / serial conversion means into parallel image data. A liquid crystal driving device comprising: a serial / parallel conversion means for performing conversion. 3. A liquid crystal driving device for generating display data for driving a liquid crystal display panel from parallel image data provided in parallel, comprising: a parallel / serial conversion means for converting the parallel image data into serial image data. A serial / parallel converter for converting serial image data obtained by the parallel / serial converter into parallel image data; and 1 / N (1 / N) of the operating clock frequency of the parallel / serial converter in the serial / parallel converter. A clock supply means for supplying an operation clock having a frequency of (N is a natural number). 4. The liquid crystal driving device according to claim 1, wherein said parallel image data is digital image data, and said processing means performs at least one of a gamma correction process and a digital / analog conversion process. 5. The apparatus according to claim 1, further comprising a transfer rate conversion means for converting the parallel image data into data having a transfer rate different from the original transfer rate, before the parallel / serial conversion means. Or the liquid crystal driving device according to 3. 6. The liquid crystal drive according to claim 2, wherein said transfer rate conversion means converts said parallel image data into data of a transfer rate corresponding to a drive frequency of a liquid crystal display panel to be driven. apparatus. 7. The liquid crystal driving device according to claim 1, wherein said serial / parallel conversion means operates with an operation clock corresponding to a driving frequency of a liquid crystal display panel to be driven. 8. The liquid crystal driving device according to claim 1, wherein said serial / parallel conversion means comprises a sample hold means. 9. The liquid crystal driving device according to claim 2, wherein said transfer rate conversion means, parallel / serial conversion means, and serial / parallel conversion means are operated by operating clocks having the same frequency.