JP2001520775A - 算術プロセッサ - Google Patents
算術プロセッサInfo
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- JP2001520775A JP2001520775A JP54461898A JP54461898A JP2001520775A JP 2001520775 A JP2001520775 A JP 2001520775A JP 54461898 A JP54461898 A JP 54461898A JP 54461898 A JP54461898 A JP 54461898A JP 2001520775 A JP2001520775 A JP 2001520775A
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/722—Modular multiplication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3812—Devices capable of handling different types of numbers
- G06F2207/382—Reconfigurable for different fixed word lengths
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
- G06F7/725—Finite field arithmetic over elliptic curves
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Computing Systems (AREA)
- Complex Calculations (AREA)
- Error Detection And Correction (AREA)
- Executing Machine-Instructions (AREA)
- Microcomputers (AREA)
- Advance Control (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.(a)有限体算術演算をパフォームする有限体算術回路とモジュラ整数算術演 算をパフォームするモジュラ整数算術回路を有する論理演算装置であって、オペ ランドデータを受信するオペランド入力データバスと前記算術演算の結果を戻す 結果データ出力バスとを有する論理演算装置と、 (b)前記オペランドデータバスおよび前記結果データバスに結合したレジス タファイルと、 (c)前記ALUおよび前記レジスタファイルに結合したコントローラであっ て、モード制御信号に応答して前記有限体演算または前記整数算術演算のいずれ かを選択し、前記レジスタファイルと前記ALUの間でのデータアクセスを制御 して、前記レジスタファイルが前記有限体算術回路および整数算術回路の両方に よって共用されるようにしたコントローラと を備えたことを特徴とする算術プロセッサ。 2.請求項1において、 前記レジスタファイルは汎用レジスタを含み、 前記ALUは前記オペランドバスのデータビット幅より広い処理ビット幅を有 すること を特徴とする算術プロセッサ。 3.請求項1において、前記コントローラは、前記論理演算装置により選択され た算術演算を制御する命令をプログラムしたことを特徴とする算術プロセッサ。 4.請求項1において、前記オペランドバスは、前記ALUの処理ビット幅およ び前記結果データバスのビット幅と同じビット幅を有することを特徴とする算術 プロセッサ。 5.請求項4において、前記オペランドデータバスは、第1および第2のオペラ ンドをそれぞれ前記ALUと結合する第1および第2のオペランドバスを含むこ とを特徴とする算術プロセッサ。 6.請求項5において、前記汎用レジスタは、 前記コントローラによって個別にアドレスすることができ、 前記ALUの前記処理ビット幅より大きな体サイズについて前記ALUで計算 するために、複数のレジスタ中のデータを組み合わせる ことができることを特徴とする算術プロセッサ。 7.請求項1において、前記コントローラが体サイズの制御に応答して、前記A LUが種々の体サイズに作用することができることを特徴とする算術プロセッサ 。 8.請求項1において、 前記ALUは、 前記算術演算で利用するオペランドを前記レジスタファイルから受信する複数 の特殊レジスタと、 前記特殊レジスタの1つ以上のビットを結合する組合せおよびロジック回路要 素を有する複数のサブALUと、 前記コントローラから受信した制御情報に応答する順序づけコントローラとを 含み、 前記順序づけコントローラ、ならびにその中のカウンタおよび検出回路は、前 記特殊レジスタおよび前記複数のサブALUに結合され、算術演算中の一連のス テップがパフォームされるようにその演算を制御する ことを特徴とする算術プロセッサ。 9.請求項8において、前記ALUは、有限体の乗算と、二乗と、加算と、減算 と、反転の前記算術演算をパフォームすることを特徴とする算術プロセッサ。 10.請求項8において、前記サブALUは、XORと、シフトと、シフトXO Rと、加算と、減算論理演算をパフォームすることを特徴とする算術プロセッサ 。 11.請求項1において、前記有限体算術回路は、 第1および第2のオペランドビットベクトルをそれぞれ受信するAレジスタお よびBレジスタと、モジュラスビットベクトルを受信するMレジスタと、前記オ ペランドの有限体の積を含むアキュムレータとを含む複数の特殊レジスタを有す る有限体乗算器回路と、 前記AおよびBレジスタの各セルから前記アキュムレータのセルへの接続を確 立するロジック回路と、 前記レジスタおよび前記ロジック回路に動作可能に接続され、前記有限体の積 を得る一連のステップを実施する順序づけコントローラと を含むことを特徴とする算術プロセッサ。 12.請求項11において、前記一連のステップは、 前記Aレジスタの内容と前記Bレジスタの連続ビットの部分積を計算するステ ップと、 前記部分積を前記アキュムレータにストアするステップと、 前記部分積のビットを試験するステップと、 前記テストしたビットがセットされた場合に前記部分積を前記モジュラスで簡 約するステップと、 前記Bレジスタの連続ビットについて前記ステップを繰り返すステップと を備えたことを特徴とする算術プロセッサ。 13.請求項12において、 前記左そろえのオペランドベクトルを前記Aレジスタおよび前記Bレジスタに それぞれストアするステップを含み、 前記テストビットは前記レジスタの前記左端のビットから得られる ことを特徴とする算術プロセッサ。 14.請求項12において、前記Bレジスタがシフトレジスタであることを特徴 とする算術プロセッサ。 15.請求項14において、前記ロジック回路は、 レジスタセルAiおよびアキュムレータCiから得られる入力を有し、レジスタ BのセルBN-1から得られた第1の加算制御信号に応答して第1の加算出力信号 を生成する第1の制御可能加算器と、 モジュラスレジスタセルMiおよび前記加算出力信号から得られる入力を有し 、前記アキュムレータのセルCN-1から得られた第2の加算制御信号に応答して アキュムレータセルCiに結合される出力を生成する第2の制御可能加算器と をそれぞれ含む、それぞれのレジスタセルに結合した複数の制御可能加算装置を 有することを特徴とする算術プロセッサ。 16.請求項15において、有限体加算器回路を含むことを特徴とする算術プロ セッサ。 17.請求項16において、前記有限体加算器は、レジスタBの前記セルBiか ら得られた入力を前記第1の加算器それぞれに結合する手段と、前記第2の加算 器の前記出力を前記セルCiに結合する手段とを含み、 前記順序づけコントローラが有限体加算制御信号に応答し、それにより前記有 限体加算演算が1クロックサイクルでパフォームされる ことを特徴とする算術プロセッサ。 18.請求項1において、前記有限体算術回路は有限体反転回路を含むことを特 徴とする算術プロセッサ。 19.請求項18において、前記有限体反転回路は、 第1および第2のオペランドビットベクトルをそれぞれ受信するAレジスタお よびBレジスタと、モジュラスビットベクトルを受信するMレジスタと、前記オ ペランドの有限体の積を含むアキュムレータとを含む複数の特殊レジスタを備え たことを特徴とする算術プロセッサ。 20.請求項1において、前記ALUは、 有限体乗算器回路と、 有限体反転回路と、 複数の特殊レジスタと、 前記特殊レジスタの各セルの間で接続を確立するロジック回路と、 前記レジスタおよび前記ロジック回路にアクション可能に接続され、有限体の 積または有限体の反転を計算するための一連のステップを実施し、それにより前 記特殊レジスタが前記有限体乗算器および前記有限体反転回路によって共用され るようにする、順序づけコントローラと を備えたことを特徴とする算術プロセッサ。 21.請求項20において、前記有限体反転回路は、拡張したユークリッドの互 除法を実施することを特徴とする算術プロセッサ。 22.請求項11において、整数算術乗算回路を含むことを特徴とする算術プロ セッサ。 23.請求項12において、前記整数算術乗算は、前記モード選択信号に応答し て前記mレジスタに桁上げをロードすることによって実装されることを特徴とす る算術プロセッサ。 24.請求項1において、暗号化システムで使用されることを特徴とする算術プ ロセッサ。 25.(a)一群の関連する算術演算をそれぞれパフォームする複数の算術回路を 有するALUであって、オペランドデータを受信するオペランド入力データバス と、前記算術演算の結果を戻す結果データ出力バスとを有するALUと、 (b)前記オペランドデータバスおよび前記結果データバスに結合したレジス タファイルと、 (c)前記ALUおよび前記レジスタファイルに結合したコントローラであっ て、算術演算を要求するモード制御信号に応答して前記複数の算術回路の1つを 選択し、かつ前記レジスタファイルと前記ALUの間でデータアクセスを制御し 、それにより前記レジスタファイルが前記算術回路によって共用されるようにす るコントローラと を備えたことを特徴とする算術プロセッサ。 26.請求項25において、前記算術回路は、有限体算術回路およびモジュラ整 数算術回路であることを特徴とする算術プロセッサ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9707861.2 | 1997-04-18 | ||
GBGB9707861.2A GB9707861D0 (en) | 1997-04-18 | 1997-04-18 | Arithmetic processor |
PCT/CA1998/000467 WO1998048345A1 (en) | 1997-04-18 | 1998-04-20 | Arithmetic processor |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007243107A Division JP4980834B2 (ja) | 1997-04-18 | 2007-09-19 | 算術プロセッサ |
Publications (2)
Publication Number | Publication Date |
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JP2001520775A true JP2001520775A (ja) | 2001-10-30 |
JP2001520775A5 JP2001520775A5 (ja) | 2006-01-05 |
Family
ID=10810977
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54461898A Withdrawn JP2001520775A (ja) | 1997-04-18 | 1998-04-20 | 算術プロセッサ |
JP2007243107A Expired - Lifetime JP4980834B2 (ja) | 1997-04-18 | 2007-09-19 | 算術プロセッサ |
JP2011049610A Withdrawn JP2011134346A (ja) | 1997-04-18 | 2011-03-07 | 算術プロセッサ |
JP2014139376A Expired - Lifetime JP5866128B2 (ja) | 1997-04-18 | 2014-07-07 | 算術プロセッサ |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007243107A Expired - Lifetime JP4980834B2 (ja) | 1997-04-18 | 2007-09-19 | 算術プロセッサ |
JP2011049610A Withdrawn JP2011134346A (ja) | 1997-04-18 | 2011-03-07 | 算術プロセッサ |
JP2014139376A Expired - Lifetime JP5866128B2 (ja) | 1997-04-18 | 2014-07-07 | 算術プロセッサ |
Country Status (8)
Country | Link |
---|---|
US (5) | US6266717B1 (ja) |
EP (2) | EP0976027B1 (ja) |
JP (4) | JP2001520775A (ja) |
AU (1) | AU7329198A (ja) |
CA (1) | CA2286647C (ja) |
DE (2) | DE69811877T2 (ja) |
GB (1) | GB9707861D0 (ja) |
WO (1) | WO1998048345A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001109376A (ja) * | 1999-10-04 | 2001-04-20 | Toyo Commun Equip Co Ltd | 演算回路および演算プロセッサ |
JP2006195563A (ja) * | 2005-01-11 | 2006-07-27 | Renesas Technology Corp | 演算処理装置 |
JP2008059595A (ja) * | 1997-04-18 | 2008-03-13 | Certicom Corp | 算術プロセッサ |
US7403614B2 (en) | 2002-08-22 | 2008-07-22 | Sony Corporation | Encryption apparatus |
Families Citing this family (79)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7483935B2 (en) * | 1995-08-16 | 2009-01-27 | Microunity Systems Engineering, Inc. | System and method to implement a matrix multiply unit of a broadband processor |
US7197625B1 (en) | 1997-10-09 | 2007-03-27 | Mips Technologies, Inc. | Alignment and ordering of vector elements for single instruction multiple data processing |
US5864703A (en) * | 1997-10-09 | 1999-01-26 | Mips Technologies, Inc. | Method for providing extended precision in SIMD vector arithmetic operations |
US6366940B1 (en) * | 1998-03-02 | 2002-04-02 | Matsushita Electric Industrial Co., Ltd. | High-speed modular multiplication apparatus achieved in small circuit |
US6199087B1 (en) * | 1998-06-25 | 2001-03-06 | Hewlett-Packard Company | Apparatus and method for efficient arithmetic in finite fields through alternative representation |
TW421756B (en) * | 1998-10-01 | 2001-02-11 | Wei Shiue Wen | Arithmetic operation circuit of finite field GF(2<m>) |
US6397241B1 (en) * | 1998-12-18 | 2002-05-28 | Motorola, Inc. | Multiplier cell and method of computing |
WO2000038047A1 (en) * | 1998-12-18 | 2000-06-29 | Motorola Inc. | Circuit and method of cryptographic multiplication |
FR2788616B1 (fr) * | 1999-01-15 | 2001-04-20 | St Microelectronics Sa | Circuit de multiplication dans un corps de galois |
US7277540B1 (en) * | 1999-01-20 | 2007-10-02 | Kabushiki Kaisha Toshiba | Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography |
US6701336B1 (en) * | 1999-11-12 | 2004-03-02 | Maxtor Corporation | Shared galois field multiplier |
AU5871201A (en) * | 2000-05-15 | 2001-11-26 | M-Systems Flash Disk Pioneers Ltd. | Extending the range of computational fields of integers |
US8176108B2 (en) * | 2000-06-20 | 2012-05-08 | International Business Machines Corporation | Method, apparatus and computer program product for network design and analysis |
US7069287B2 (en) * | 2000-09-19 | 2006-06-27 | Worcester Polytechnic Institute | Method for efficient computation of odd characteristic extension fields |
DE10061997A1 (de) * | 2000-12-13 | 2002-07-18 | Infineon Technologies Ag | Kryptographieprozessor |
FR2818847A1 (fr) * | 2000-12-26 | 2002-06-28 | St Microelectronics Sa | Circuit logique a polarite variable |
US7599981B2 (en) * | 2001-02-21 | 2009-10-06 | Mips Technologies, Inc. | Binary polynomial multiplier |
US7711763B2 (en) * | 2001-02-21 | 2010-05-04 | Mips Technologies, Inc. | Microprocessor instructions for performing polynomial arithmetic operations |
US7162621B2 (en) | 2001-02-21 | 2007-01-09 | Mips Technologies, Inc. | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration |
US7181484B2 (en) | 2001-02-21 | 2007-02-20 | Mips Technologies, Inc. | Extended-precision accumulation of multiplier output |
US7607165B2 (en) * | 2001-03-09 | 2009-10-20 | The Athena Group, Inc. | Method and apparatus for multiplication and/or modular reduction processing |
US7233998B2 (en) * | 2001-03-22 | 2007-06-19 | Sony Computer Entertainment Inc. | Computer architecture and software cells for broadband networks |
WO2003040911A2 (fr) * | 2001-06-13 | 2003-05-15 | Zencod S.A. | Carte d'acceleration de traitement cryptographique |
KR20030003435A (ko) * | 2001-06-30 | 2003-01-10 | 주식회사 시큐리티테크놀로지스 | 암호시스템에 사용하기 위한 최적의 역원을 구하기 위한방법 및 장치 |
WO2003021423A2 (en) | 2001-09-04 | 2003-03-13 | Microunity Systems Engineering, Inc. | System and method for performing multiplication |
US7206410B2 (en) * | 2001-10-10 | 2007-04-17 | Stmicroelectronics S.R.L. | Circuit for the inner or scalar product computation in Galois fields |
US7177891B2 (en) * | 2002-10-09 | 2007-02-13 | Analog Devices, Inc. | Compact Galois field multiplier engine |
US7082452B2 (en) * | 2001-11-30 | 2006-07-25 | Analog Devices, Inc. | Galois field multiply/multiply-add/multiply accumulate |
US7269615B2 (en) * | 2001-12-18 | 2007-09-11 | Analog Devices, Inc. | Reconfigurable input Galois field linear transformer system |
US7895253B2 (en) * | 2001-11-30 | 2011-02-22 | Analog Devices, Inc. | Compound Galois field engine and Galois field divider and square root engine and method |
US7283628B2 (en) | 2001-11-30 | 2007-10-16 | Analog Devices, Inc. | Programmable data encryption engine |
US6766345B2 (en) | 2001-11-30 | 2004-07-20 | Analog Devices, Inc. | Galois field multiplier system |
US7508937B2 (en) * | 2001-12-18 | 2009-03-24 | Analog Devices, Inc. | Programmable data encryption engine for advanced encryption standard algorithm |
DE10164416A1 (de) * | 2001-12-29 | 2003-07-10 | Philips Intellectual Property | Verfahren zum Multiplizieren zweier Faktoren aus dem Galois-Feld sowie Multiplizierer zum Durchführen des Verfahrens |
CA2369537C (en) * | 2001-12-31 | 2013-07-23 | Certicom Corp. | Method and apparatus for performing finite field calculations |
US7000090B2 (en) * | 2002-01-21 | 2006-02-14 | Analog Devices, Inc. | Center focused single instruction multiple data (SIMD) array system |
US6941446B2 (en) * | 2002-01-21 | 2005-09-06 | Analog Devices, Inc. | Single instruction multiple data array cell |
US6865661B2 (en) | 2002-01-21 | 2005-03-08 | Analog Devices, Inc. | Reconfigurable single instruction multiple data array |
JP2003244128A (ja) * | 2002-02-21 | 2003-08-29 | Hitachi Ltd | 暗号復号通信用半導体装置および記録再生機器 |
US7343389B2 (en) * | 2002-05-02 | 2008-03-11 | Intel Corporation | Apparatus and method for SIMD modular multiplication |
US7243292B1 (en) * | 2002-10-17 | 2007-07-10 | Telefonaktiebolaget Lm Ericsson (Publ) | Error correction using finite fields of odd characteristics on binary hardware |
US7197527B2 (en) * | 2002-10-17 | 2007-03-27 | Telefonaktiebolaget Lm Ericsson (Publ) | Efficient arithmetic in finite fields of odd characteristic on binary hardware |
US7028247B2 (en) * | 2002-12-25 | 2006-04-11 | Faraday Technology Corp. | Error correction code circuit with reduced hardware complexity |
US7139787B2 (en) * | 2003-01-30 | 2006-11-21 | Sun Microsystems, Inc. | Multiply execution unit for performing integer and XOR multiplication |
US7693928B2 (en) * | 2003-04-08 | 2010-04-06 | Analog Devices, Inc. | Galois field linear transformer trellis system |
CN100530157C (zh) * | 2003-04-08 | 2009-08-19 | 阿纳洛格装置公司 | 伽罗瓦域线性变换器格栅系统 |
US7139900B2 (en) * | 2003-06-23 | 2006-11-21 | Intel Corporation | Data packet arithmetic logic devices and methods |
US8194855B2 (en) * | 2003-06-30 | 2012-06-05 | Oracle America, Inc. | Method and apparatus for implementing processor instructions for accelerating public-key cryptography |
US7634666B2 (en) * | 2003-08-15 | 2009-12-15 | Cityu Research Limited | Crypto-engine for cryptographic processing of data |
US7421076B2 (en) * | 2003-09-17 | 2008-09-02 | Analog Devices, Inc. | Advanced encryption standard (AES) engine with real time S-box generation |
US7171544B2 (en) * | 2003-12-15 | 2007-01-30 | International Business Machines Corporation | Run-time parallelization of loops in computer programs by access patterns |
KR100574965B1 (ko) * | 2004-01-19 | 2006-05-02 | 삼성전자주식회사 | 유한체 곱셈기 |
DE102004013484B3 (de) * | 2004-03-18 | 2005-08-11 | Infineon Technologies Ag | Rechenwerk |
WO2005114802A2 (en) * | 2004-05-11 | 2005-12-01 | North Dakota State University | Optimal signed-digit recoding for elliptic curve cryptography |
US7512647B2 (en) * | 2004-11-22 | 2009-03-31 | Analog Devices, Inc. | Condensed Galois field computing system |
WO2006076800A1 (en) * | 2005-01-18 | 2006-07-27 | Certicom Corp. | Accelerated verification of digital signatures and public keys |
DE102005028662B4 (de) * | 2005-03-04 | 2022-06-02 | Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik | Verfahren und Vorrichtung zum Berechnen einer Polynom-Multiplikation, insbesondere für die elliptische Kurven-Kryptographie |
US7728744B2 (en) * | 2005-10-26 | 2010-06-01 | Analog Devices, Inc. | Variable length decoder system and method |
US8285972B2 (en) * | 2005-10-26 | 2012-10-09 | Analog Devices, Inc. | Lookup table addressing system and method |
US8024551B2 (en) | 2005-10-26 | 2011-09-20 | Analog Devices, Inc. | Pipelined digital signal processor |
US7634596B2 (en) * | 2006-06-02 | 2009-12-15 | Microchip Technology Incorporated | Dynamic peripheral function remapping to external input-output connections of an integrated circuit device |
US7664915B2 (en) * | 2006-12-19 | 2010-02-16 | Intel Corporation | High performance raid-6 system architecture with pattern matching |
DE102007007699A1 (de) * | 2007-02-09 | 2008-08-14 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Reduktion von Seiten-Kanal-Informationen durch interagierende Krypto-Blocks |
US8271570B2 (en) * | 2007-06-30 | 2012-09-18 | Intel Corporation | Unified integer/galois field (2m) multiplier architecture for elliptic-curve crytpography |
US7929707B1 (en) * | 2007-09-06 | 2011-04-19 | Elcomsoft Co. Ltd. | Use of graphics processors as parallel math co-processors for password recovery |
US8301990B2 (en) * | 2007-09-27 | 2012-10-30 | Analog Devices, Inc. | Programmable compute unit with internal register and bit FIFO for executing Viterbi code |
EP2208165A4 (en) * | 2007-11-02 | 2010-11-24 | Certicom Corp | MONTGOMERY ARITHMETIC SIGNED |
US8359479B2 (en) * | 2008-07-17 | 2013-01-22 | Lsi Corporation | High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks |
CN101478785B (zh) * | 2009-01-21 | 2010-08-04 | 华为技术有限公司 | 资源池管理系统及信号处理方法 |
US9747105B2 (en) | 2009-12-17 | 2017-08-29 | Intel Corporation | Method and apparatus for performing a shift and exclusive or operation in a single instruction |
US8626811B2 (en) | 2010-04-30 | 2014-01-07 | Certicom Corp. | Method and apparatus for providing flexible bit-length moduli on a block Montgomery machine |
US9965387B1 (en) * | 2010-07-09 | 2018-05-08 | Cypress Semiconductor Corporation | Memory devices having embedded hardware acceleration and corresponding methods |
EP2700256B1 (en) | 2011-05-20 | 2017-11-29 | BlackBerry Limited | Verifying passwords on a mobile device |
EP2715968A4 (en) | 2011-05-26 | 2015-08-12 | Certicom Corp | RANDOM FOR ENCRYPTION OPERATIONS |
EP2718844B1 (en) | 2011-06-06 | 2019-08-07 | Certicom Corp. | Squaring binary finite field elements |
CN102981801B (zh) * | 2012-11-07 | 2015-10-28 | 迈普通信技术股份有限公司 | 一种本地总线数据位宽的转换方法及装置 |
US9619207B1 (en) * | 2014-10-27 | 2017-04-11 | Altera Corporation | Circuitry and methods for implementing Galois-field reduction |
US11010166B2 (en) | 2016-03-31 | 2021-05-18 | Intel Corporation | Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuits |
CN109710308B (zh) * | 2017-10-25 | 2023-03-31 | 阿里巴巴集团控股有限公司 | 任务的处理方法、装置和系统 |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4216531A (en) * | 1978-11-17 | 1980-08-05 | Control Data Corporation | Finite field multiplier |
JPS60120439A (ja) * | 1983-12-05 | 1985-06-27 | Nec Corp | 演算処理装置 |
WO1985003371A1 (en) * | 1984-01-21 | 1985-08-01 | Sony Corporation | Circuit for calculating finite fields |
DE3631992A1 (de) † | 1986-03-05 | 1987-11-05 | Holger Sedlak | Kryptographie-verfahren und kryptographie-prozessor zur durchfuehrung des verfahrens |
JPS6382513A (ja) | 1986-09-26 | 1988-04-13 | Toshiba Corp | バレルシフタ |
FR2605818B1 (fr) * | 1986-10-27 | 1992-09-18 | Thomson Csf | Codeur-decodeur algebrique de codes en blocs reed solomon et bch, applicable aux telecommunications numeriques |
US5268584A (en) | 1988-11-28 | 1993-12-07 | The United States Of America As Represented By The Department Of Energy | Strong liquid-crystalline polymeric compositions |
US5077793A (en) | 1989-09-29 | 1991-12-31 | The Boeing Company | Residue number encryption and decryption system |
US5268854A (en) * | 1990-11-13 | 1993-12-07 | Kabushiki Kaisha Toshiba | Microprocessor with a function for three-dimensional graphic processing |
DE69231110T2 (de) | 1991-03-05 | 2000-11-16 | Canon Kk | Rechengerät und Verfahren zum Verschlüsseln/Entschlüsseln von Kommunikationsdaten unter Verwendung desselben |
JP3406914B2 (ja) | 1991-09-05 | 2003-05-19 | キヤノン株式会社 | 演算装置及びこれを備えた暗号化装置、復号装置 |
US5235614A (en) * | 1991-03-13 | 1993-08-10 | Motorola, Inc. | Method and apparatus for accommodating a variable number of communication channels in a spread spectrum communication system |
KR940001147B1 (ko) | 1991-03-20 | 1994-02-14 | 삼성전자 주식회사 | 부분체 GF(2^m/2)을 이용한 GF(2^m)상의 연산방법 및 장치 |
JP2693651B2 (ja) * | 1991-04-30 | 1997-12-24 | 株式会社東芝 | 並列プロセッサー |
WO1994015423A1 (en) | 1992-12-22 | 1994-07-07 | Telstra Corporation Limited | A cryptographic method |
JPH06268530A (ja) | 1993-03-16 | 1994-09-22 | Hitachi Ltd | 誤りパターン演算回路 |
DE69428627T2 (de) * | 1993-06-10 | 2002-08-08 | Koninkl Philips Electronics Nv | Dekodierer für Wörter variabler Länge mit hohem Durchfluss und Vorrichtung mit einem solchen Dekodierer |
US5497423A (en) | 1993-06-18 | 1996-03-05 | Matsushita Electric Industrial Co., Ltd. | Method of implementing elliptic curve cryptosystems in digital signatures or verification and privacy communication |
JPH09507110A (ja) * | 1993-11-04 | 1997-07-15 | シーラス ロジック, インコーポレイテッド | 有限体反転 |
US5555516A (en) | 1993-11-04 | 1996-09-10 | Cirrus Logic, Inc. | Multipurpose error correction calculation circuit |
JPH07175664A (ja) * | 1993-12-16 | 1995-07-14 | Dainippon Printing Co Ltd | コンパイラ装置 |
US5459681A (en) * | 1993-12-20 | 1995-10-17 | Motorola, Inc. | Special functions arithmetic logic unit method and apparatus |
JP3702475B2 (ja) | 1994-07-25 | 2005-10-05 | ソニー株式会社 | 回路自動生成装置 |
US5577069A (en) * | 1994-08-02 | 1996-11-19 | National Semiconductor Corporation | Signalling method and structure suitable for out-of-band information transfer in communication network |
FR2723455B1 (fr) * | 1994-08-05 | 1996-10-31 | Sgs Thomson Microelectronics | Circuit d'inversion d'elements d'un corps de galois |
GB9506574D0 (en) | 1995-03-30 | 1995-05-17 | Cryptech Systems Inc | Multiple bit multiplier |
US5627855A (en) * | 1995-05-25 | 1997-05-06 | Golden Bridge Technology, Inc. | Programmable two-part matched filter for spread spectrum |
US5778009A (en) * | 1995-06-14 | 1998-07-07 | Quantum Corporation | Dedicated ALU architecture for 10-bit Reed-Solomon error correction module |
US5737424A (en) | 1996-06-04 | 1998-04-07 | Software Security, Inc. | Method and system for secure distribution of protected data using elliptic curve systems |
JP2846860B2 (ja) * | 1996-10-01 | 1999-01-13 | ユニデン株式会社 | スペクトル拡散通信方式を用いた送信機、受信機、通信システム及び通信方法 |
GB9627069D0 (en) * | 1996-12-30 | 1997-02-19 | Certicom Corp | A method and apparatus for finite field multiplication |
GB9707861D0 (en) | 1997-04-18 | 1997-06-04 | Certicom Corp | Arithmetic processor |
US5854759A (en) * | 1997-05-05 | 1998-12-29 | Rsa Data Security, Inc. | Methods and apparatus for efficient finite field basis conversion |
US5982895A (en) | 1997-12-24 | 1999-11-09 | Motorola, Inc. | Finite field inverse circuit for use in an elliptic curve processor |
US6003057A (en) | 1997-12-24 | 1999-12-14 | Motorola, Inc. | Galois field arithmetic logic unit circuit |
US6199086B1 (en) | 1997-12-24 | 2001-03-06 | Motorola, Inc. | Circuit and method for decompressing compressed elliptic curve points |
US6009450A (en) * | 1997-12-24 | 1999-12-28 | Motorola, Inc. | Finite field inverse circuit |
US5999959A (en) * | 1998-02-18 | 1999-12-07 | Quantum Corporation | Galois field multiplier |
US6088800A (en) | 1998-02-27 | 2000-07-11 | Mosaid Technologies, Incorporated | Encryption processor with shared memory interconnect |
-
1997
- 1997-04-18 GB GBGB9707861.2A patent/GB9707861D0/en active Pending
- 1997-12-24 US US08/997,964 patent/US6266717B1/en not_active Expired - Lifetime
- 1997-12-24 US US08/997,960 patent/US6230179B1/en not_active Expired - Lifetime
-
1998
- 1998-04-20 EP EP98920431A patent/EP0976027B1/en not_active Expired - Lifetime
- 1998-04-20 EP EP02027872.7A patent/EP1293891B2/en not_active Expired - Lifetime
- 1998-04-20 JP JP54461898A patent/JP2001520775A/ja not_active Withdrawn
- 1998-04-20 DE DE69811877T patent/DE69811877T2/de not_active Expired - Lifetime
- 1998-04-20 AU AU73291/98A patent/AU7329198A/en not_active Abandoned
- 1998-04-20 CA CA2286647A patent/CA2286647C/en not_active Expired - Lifetime
- 1998-04-20 DE DE69841492T patent/DE69841492D1/de not_active Expired - Lifetime
- 1998-04-20 WO PCT/CA1998/000467 patent/WO1998048345A1/en active IP Right Grant
-
1999
- 1999-10-14 US US09/418,217 patent/US6349318B1/en not_active Expired - Lifetime
-
2001
- 2001-12-21 US US10/023,934 patent/US6735611B2/en not_active Expired - Lifetime
-
2004
- 2004-05-04 US US10/837,749 patent/US7424504B2/en not_active Expired - Fee Related
-
2007
- 2007-09-19 JP JP2007243107A patent/JP4980834B2/ja not_active Expired - Lifetime
-
2011
- 2011-03-07 JP JP2011049610A patent/JP2011134346A/ja not_active Withdrawn
-
2014
- 2014-07-07 JP JP2014139376A patent/JP5866128B2/ja not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008059595A (ja) * | 1997-04-18 | 2008-03-13 | Certicom Corp | 算術プロセッサ |
JP2001109376A (ja) * | 1999-10-04 | 2001-04-20 | Toyo Commun Equip Co Ltd | 演算回路および演算プロセッサ |
US7403614B2 (en) | 2002-08-22 | 2008-07-22 | Sony Corporation | Encryption apparatus |
JP2006195563A (ja) * | 2005-01-11 | 2006-07-27 | Renesas Technology Corp | 演算処理装置 |
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US6735611B2 (en) | 2004-05-11 |
AU7329198A (en) | 1998-11-13 |
US20050044124A1 (en) | 2005-02-24 |
US6230179B1 (en) | 2001-05-08 |
JP5866128B2 (ja) | 2016-02-17 |
DE69811877T2 (de) | 2003-12-18 |
CA2286647C (en) | 2015-01-13 |
EP1293891B1 (en) | 2010-02-03 |
EP0976027B1 (en) | 2003-03-05 |
JP2011134346A (ja) | 2011-07-07 |
DE69841492D1 (de) | 2010-03-25 |
GB9707861D0 (en) | 1997-06-04 |
EP0976027A1 (en) | 2000-02-02 |
JP2008059595A (ja) | 2008-03-13 |
US20020136402A1 (en) | 2002-09-26 |
EP1293891A2 (en) | 2003-03-19 |
EP1293891A3 (en) | 2004-09-08 |
WO1998048345A1 (en) | 1998-10-29 |
JP2014219994A (ja) | 2014-11-20 |
DE69811877D1 (de) | 2003-04-10 |
US6266717B1 (en) | 2001-07-24 |
US7424504B2 (en) | 2008-09-09 |
US6349318B1 (en) | 2002-02-19 |
CA2286647A1 (en) | 1998-10-29 |
EP1293891B2 (en) | 2017-04-12 |
EP1293891B8 (en) | 2010-04-14 |
JP4980834B2 (ja) | 2012-07-18 |
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