CN112104366A

CN112104366A - Four-channel high-speed synchronous FMC acquisition device

Info

Publication number: CN112104366A
Application number: CN202010891068.9A
Authority: CN
Inventors: 刘盛利; 侯红英; 张艳如; 刘宇
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: CETC 10 Research Institute; Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2020-08-30
Filing date: 2020-08-30
Publication date: 2020-12-18

Abstract

The invention discloses a four-channel high-speed synchronous FMC acquisition device, and relates to acquisition devices in the fields of measurement and control, communication and the like. The invention is realized by the following technical scheme: the AD acquisition circuit converts a single-end signal into a differential signal which can be received by an AD chip through 4 paths of input signals respectively through a two-stage transformer, the clock shunt circuit outputs a sampling clock and a sampling synchronous signal which are required by an analog-to-digital converter AD through frequency multiplication and frequency division respectively, simultaneously sends two groups of AD sampling clocks and AD sampling synchronous signals to the corresponding AD chip respectively, sends synchronous data to an FMC connector, and sends a data processing clock to a signal processing carrier plate; the FMC connector configures a value required by the work of an AD chip register through a Serial Peripheral Interface (SPI), two groups of synchronous signals transmitted by the AD are respectively provided for the corresponding AD, after the AD normally works, 4 output channel data are sent to the carrier plate through an FMC connector plug, and 4 paths of intermediate frequency data synchronous sampling and transmission are completed.

Description

Four-channel high-speed synchronous FMC acquisition device

Technical Field

The invention relates to a high-speed four-channel synchronous data acquisition device in the fields of measurement and control, communication and the like.

Background

The FMC acquisition board card integrating the fixed network and the mobile network is a universal board card module, and aims to provide the standard sandwich board size, a connector and a module interface for fpga on a base board (a carrier card), and the i/o interface is separated from the fpga in such a way. In a measurement and control and communication system, the sampling frequency, the synchronism and the transmission rate of data acquisition have great influence on sampling, so that the positioning precision and accuracy are influenced. Most of the existing acquisition card interfaces are PCI bus, ISA bus, 1394 bus and the like, the cost is high, and the development is not easy. And the existing FMC acquisition board card has fewer analog input channels, low acquisition precision, higher overall delay of a system after being connected to fpga, and can not effectively support an on-board programmable sampling clock and an external reference clock. The existing acquisition devices used in the fields of measurement and control, communication and the like are large in size, multiple in connection, low in sampling speed, long in design period, incapable of being multiplexed and difficult to expand, insufficient in reliability verification and completely asynchronous in data, multiple AD (analog-to-digital) devices in an FMC acquisition board have no synchronization function, especially multiple acquisition devices cannot be synchronized, the data acquisition time from different directions is different, and inconvenience is brought to rear-end signal processing. Especially for data collected between different plates. In order to break through the limitation of a structural design scheme and take the use requirements of platforms such as an airborne platform, a ship-borne platform and an aircraft-borne platform into consideration, the acquisition device can be flexibly and widely applied to different fields such as radar, guard and communication, a data chain and the like, the volume power consumption of the data acquisition device needs to be reduced by improving the integration level, and the barrier of the generalization of multiple platforms is broken through the compatibility design.

Disclosure of Invention

Aiming at the problems, the invention provides a four-channel high-speed synchronous FMC acquisition device which is small in size, few in connecting lines, easy to expand, high in sampling speed and completely synchronous in data, and aims to solve the problems that a traditional acquisition board is low in sampling speed, many in connecting lines, asynchronous in data, long in design period, incapable of being multiplexed, incapable of expanding, insufficient in reliability verification and the like.

The above object of the present invention can be achieved by the following measures, a four-channel high-speed synchronous FMC acquisition device, comprising an AD acquisition circuit, a clock shunt circuit and a power conversion circuit, characterized in that: the AD acquisition circuit converts a single-end signal into a differential signal which can be received by an AD chip through 4 paths of input signals respectively through a two-stage transformer, the clock shunt circuit outputs a sampling clock and a sampling synchronous signal which are required by an analog-to-digital converter AD through frequency multiplication and frequency division respectively, simultaneously, two groups of AD sampling clocks and two groups of AD sampling synchronous signals are respectively sent to corresponding 2 AD chips, the 2 AD chips synchronously acquire two groups of output channels respectively through four-channel data, the synchronous data are sent to an FMC connector, and a data processing clock is sent to a signal processing carrier plate through the FMC connector; the FMC connector configures a value required by the work of an AD chip register through a Serial Peripheral Interface (SPI), two groups of synchronous signals of analog-digital (AD) transmission numbers are respectively provided for 2 corresponding ADs, and after the AD normally works, 4 output channel data are sent to the carrier plate through an FMC connector plug, so that 4 paths of intermediate frequency data synchronous sampling and transmission are completed.

Compared with the prior art, the invention has the beneficial effects that:

small volume, few connecting lines and easy expansion. The invention adopts the AD acquisition circuit, the clock shunt circuit and the power conversion circuit to form a standard FMC card, and the size is small and is only 87.5mmx69 mm. The number of connecting wires is small, the AD acquisition circuit converts a single-end signal into a differential signal which can be received by an AD chip by 4 paths of input signals through two stages of transformers respectively, data is transmitted in a JESD240B bus mode, and 4 paths of data can be transmitted only by 8 pairs of high-speed differential lines. Meanwhile, the signal processing carrier board can be used on signal processing carrier boards of different models meeting VITA57.1 standard. The extension is easy, and a plurality of devices can be used in the same signal processing carrier plate in an extension mode.

High sampling speed and complete data synchronization. The invention adopts a clock splitter, respectively outputs a sampling clock and a sampling synchronous signal required by an analog-to-digital converter AD through frequency multiplication and frequency division, simultaneously respectively sends two groups of AD sampling clocks and AD sampling synchronous signals to 2 corresponding AD chips, the 2 AD chips respectively synchronously acquire through four channels of data, respectively outputs two groups of channels, sends the synchronous data to an FMC connector, and sends a data processing clock to a signal processing carrier plate through the FMC connector; the method has strong real-time processing capability, and the sampling speed range is 300-1000 MSPS through AD high-precision analog-to-digital conversion and high-speed sampling speed, the sampling bit number is 14 bits, and the sampling rate can reach 1000 MSPS. The data without phase difference is completely synchronous after 4 paths of sampling, and the phase consistency of the 4 paths of data is within +/-1 degree. Meanwhile, multiple paths of data of the same devices can be completely synchronized by the synchronous input signals of the clock splitter.

The invention has the beneficial effects that: the invention provides a standard high-speed synchronous FMC acquisition device which is low in power consumption, small in size, high in reliability, expandable and adaptable to different signal processing platforms. The performance is reliable: most of peripheral devices are manufactured in a chip by the digital signal processor with high integration level, so that the number of the peripheral devices is reduced, and the failure rate is reduced. And (4) prevention of safety measures in design, such as adding a resistance-capacitance filter at an A/D signal input end and the like. Therefore, on one hand, high-frequency noise in the input signal can be suppressed, and meanwhile, the input current when the signal is too strong can be limited, so that the data acquisition unit is protected from being damaged.

The invention can synchronize a plurality of FMC acquisition devices through the synchronous signal of the input clock splitter. The method is particularly suitable for signal acquisition and processing with high precision and wide dynamic range.

Drawings

The patent is further described below with reference to the drawings and examples.

FIG. 1 is an AD acquisition schematic block diagram of a four-channel high-speed synchronous FMC acquisition device of the present invention.

Fig. 2 is a schematic block diagram of a clock divider circuit for the AD sample clock and the AD sample sync signals required in fig. 1.

Fig. 3 is a schematic block diagram of the power conversion circuit of the present invention.

FIG. 4 is a schematic block diagram of the FMC collection device voltage and temperature detection of the present invention.

FIG. 5 is a schematic diagram of the FMC collection device of the present invention in use.

Detailed Description

The technical scheme of the invention is further described in detail in the following with reference to the attached drawings.

Refer to fig. 1 and 2. In the preferred embodiment described below, a four-channel high-speed synchronous FMC acquisition device includes an AD acquisition circuit, a clock splitting circuit and a power conversion circuit. Wherein: the AD acquisition circuit is responsible for completing the functions of sampling and outputting input data and the like. The clock shunt circuit receives a reference clock, converts the reference clock into a clock required by AD sampling through frequency multiplication and frequency division, synchronizes signals and a clock for carrying out data processing by the carrier plate, and can receive input synchronized signals; the power conversion circuit provides the voltage needed by other chips. The AD acquisition circuit converts a single-end signal into a differential signal which can be received by an AD chip through 4 paths of input signals respectively through a two-stage transformer, a clock splitter outputs a sampling clock and a sampling synchronous signal which are required by an analog-to-digital converter AD through frequency multiplication and frequency division respectively, simultaneously, two groups of AD sampling clocks and two groups of AD sampling synchronous signals are respectively sent to corresponding 2 AD chips, the 2 AD chips synchronously acquire two groups of output channels through four channels of data respectively, synchronous data are sent to an FMC connector, and simultaneously, a data processing clock is sent to a signal processing carrier plate through the FMC connector; the FMC connector configures a value required by the work of an AD chip register through a Serial Peripheral Interface (SPI), two groups of synchronous signals of analog-digital (AD) transmission numbers are respectively provided for 2 corresponding ADs, and after the AD normally works, 4 output channel data are sent to the carrier plate through an FMC connector plug, so that 4 paths of intermediate frequency data synchronous sampling and transmission are completed.

The input reference clock of the clock splitter HMC7044 can be configured into various AD sampling rates through the clock splitter, the highest sampling rate is 1GSPS, and various AD sampling rates can be switched among 2 AD chips according to the same time and different sampling rate requirements.

The device can be loaded into a general signal processing module with FMC standard interface for subsequent data processing.

As shown in fig. 3. The power conversion circuit comprises a power DC-DC chip LTM4622 and an LDO chip SM74401 which are connected through two FMC daughter cards at the output end of the FMC connector plug, and 12V and 3.3V power sources input by the FMC daughter cards on the FMC connector plug. 12V input by the FMC daughter card is output to two SM74401 through the output end of a power supply DC-DC chip LTM4622, 5V is output to 1 path, then the two SM74401 are respectively converted into analog and digital 3.3V required by an AD chip ADS4449 and a clock splitter HMC7044, and the other path of output is output to 1.8V to the other SM74401 to be converted into digital 1.25V required by an AD chip AD 9680. The 3.3V power supply output by the FMC daughter card is converted into analog 2.5V and analog 1.25V required by the AD chip AD9680 through two SM 74401.

Preferably, as shown in fig. 4. Temperature and voltage detection detects FMC daughter card temperature, 12V voltage, 3.3V voltage and 1.8V voltage through sensor ADT7411, and then reports a signal processing carrier plate through an FMC connector by using an I2C bus.

Preferably, as shown in fig. 5. The FMC acquisition device comprises an acquisition device, an FMC connector plug, an FMC connector socket and a signal processing carrier board. The acquisition device is buckled on the signal processing carrier plate through a plug and a socket of the FMC connector.

While the foregoing is directed to the preferred embodiment for implementing a four channel high speed synchronous FMC acquisition device, it is to be understood that the invention is not limited to the form disclosed herein, but is not intended to be exhaustive of other embodiments and may be used in various other combinations, modifications, and environments and is capable of changes within the scope of the teaching described herein or of being practiced or carried out by those skilled in the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. The utility model provides a high-speed synchronous FMC collection system of four-channel, includes AD acquisition circuit, clock shunt circuit and power conversion circuit, its characterized in that: the AD acquisition circuit converts a single-end signal into a differential signal which can be received by an AD chip through 4 paths of input signals respectively through a two-stage transformer, the clock shunt circuit outputs a sampling clock and a sampling synchronous signal which are required by an analog-to-digital converter AD through frequency multiplication and frequency division respectively, simultaneously, two groups of AD sampling clocks and two groups of AD sampling synchronous signals are respectively sent to corresponding 2 AD chips, the 2 AD chips synchronously acquire two groups of output channels respectively through four-channel data, the synchronous data are sent to an FMC connector, and a data processing clock is sent to a signal processing carrier plate through the FMC connector; the FMC connector configures a value required by the work of an AD chip register through a Serial Peripheral Interface (SPI), two groups of synchronous signals of analog-digital (AD) transmission numbers are respectively provided for 2 corresponding ADs, and after the AD normally works, 4 output channel data are sent to the carrier plate through an FMC connector plug, so that 4 paths of intermediate frequency data synchronous sampling and transmission are completed.

2. A four-channel high-speed synchronous FMC acquisition device as in claim 1, wherein: and the AD acquisition circuit finishes input data sampling and output.

3. A four-channel high-speed synchronous FMC acquisition device as in claim 1, wherein: the clock shunt circuit receives a reference clock, converts the reference clock into a clock required by AD sampling through frequency multiplication and frequency division, and receives an input synchronous signal simultaneously, wherein the clock is a clock for data processing of the synchronous signal and the carrier plate.

4. A four-channel high-speed synchronous FMC acquisition device as in claim 1, wherein: the input reference clock of the clock splitter HMC7044 is configured into a plurality of AD sampling rates through the clock splitter, and the AD sampling rates are switched among 2 AD chips according to the requirements of the same time and different sampling rates.

5. A four-channel high-speed synchronous FMC acquisition device as in claim 1, wherein: the power conversion circuit comprises a power DC-DC chip LTM4622 and an LDO chip SM74401 which are connected through two FMC daughter cards at the output end of the FMC connector plug, and 12V and 3.3V power sources input by the FMC daughter cards on the FMC connector plug.

6. A four-channel high-speed synchronous FMC acquisition device as in claim 5 further comprising: 12V input by the FMC daughter card is output to two SM74401 through the output end of a power supply DC-DC chip LTM4622, 5V is output to 1 path, then the two SM74401 are respectively converted into analog and digital 3.3V required by an AD chip ADS4449 and a clock splitter HMC7044, and the other path of output is output to 1.8V to the other SM74401 to be converted into digital 1.25V required by an AD chip AD 9680.

7. A four-channel high-speed synchronous FMC acquisition device as in claim 6 further comprising: the 3.3V power supply output by the FMC daughter card is converted into analog 2.5V and analog 1.25V required by the AD chip AD9680 through two SM 74401.

8. A four-channel high-speed synchronous FMC acquisition device as in claim 7, wherein: temperature and voltage detection detects FMC daughter card temperature, 12V voltage, 3.3V voltage and 1.8V voltage through sensor ADT7411, and then reports a signal processing carrier plate through an FMC connector by using an I2C bus.

9. A four-channel high-speed synchronous FMC acquisition device as in claim 1, wherein: the FMC acquisition device comprises an acquisition device, an FMC connector plug, an FMC connector socket and a signal processing carrier plate.

10. A four-channel high-speed synchronous FMC acquisition device as in claim 9, wherein: the acquisition device is buckled on the signal processing carrier plate through a plug and a socket of the FMC connector.