CN205721785U - A kind of multiple signals multi-channel output device - Google Patents
A kind of multiple signals multi-channel output device Download PDFInfo
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- CN205721785U CN205721785U CN201620367644.9U CN201620367644U CN205721785U CN 205721785 U CN205721785 U CN 205721785U CN 201620367644 U CN201620367644 U CN 201620367644U CN 205721785 U CN205721785 U CN 205721785U
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Abstract
This utility model belongs to signal input and output field, particularly to a kind of multiple signals multi-channel output device.This device includes microprocessor unit and FPGA logic cell, and microprocessor unit is used for receiving and parsing through passage configuration-direct, and the data after resolving are stored in the buffer area of inside, and the outfan of described microprocessor unit connects the input of FPGA logic cell；FPGA logic cell is for receiving from the data after the parsing of microprocessor unit, and the input of described FPGA logic cell connects all of input signal, and the outfan of FPGA logic cell connects output channel.Therefore this utility model can change passage configuration-direct and change the input signal that each road output channel is corresponding flexibly；Change the way of output channel and input signal by the number changing output channel module, and this utility model be also equipped with simple in construction, with low cost, reliable and stable, be easy to the advantage promoted the use of.
Description
Technical field
This utility model belongs to signal input and output field, particularly to a kind of multiple signals multichannel output
Device.
Background technology
Multiple signals input/output unit is widely used in various I/O channel test neck at present
In territory, signal input/output unit is when testing, and the kind of the input signal that output channel is corresponding needs
The most changeable, just can make the comparatively perfect that test result becomes.
Multiple signals multi-channel output device of the prior art mostly uses hardware circuit to build or FPGA
Logical block, the way of input signal and the way of output channel all can not be changed flexibly, and output channel
Corresponding input signal kind can not change neatly, and complex circuit designs, relatively costly.
Therefore a kind of way that can change input signal of proposition and the way of output channel, and output are needed badly
The multiple signals multi-channel output device that the input signal kind that passage is corresponding can change neatly.
Utility model content
This utility model is in order to overcome above-mentioned the deficiencies in the prior art, it is provided that a kind of multiple signals multichannel
Output device, this device is possible not only to change input signal and the way of output channel, it is also possible to neatly
Change the input signal kind that output channel is corresponding, and possess simple in construction, feature with low cost.
For achieving the above object, this utility model have employed techniques below measure:
A kind of multiple signals multi-channel output device, this device includes for receiving and parsing through from passage
Microprocessor unit this utility model of dispensing unit passage of the present utility model configuration-direct, described micro-place
Reason device unit outfan of the present utility model connects FPGA logic cell input of the present utility model；Institute
State FPGA logic cell input of the present utility model and connect all of input signal, FPGA logic cell
Outfan of the present utility model connects output channel；
Described microprocessor unit this utility model, FPGA logic cell input end of clock of the present utility model
It is all connected with clock signal.
This utility model can also be realized further by techniques below measure.
Preferably, described FPGA logic cell this utility model includes data reception module this utility model
With signal selection module this utility model, described data reception module input of the present utility model connects micro-
Processor unit outfan of the present utility model, data reception module data output end of the present utility model is even
Connecing signal selection module data input pin of the present utility model, described data reception module is of the present utility model
Input end of clock connects clock signal；Described signal selection module input of the present utility model connects all
Input signal, signal selection module outfan of the present utility model connect output channel.
Preferably, described signal selection module includes independent of one another and identical output channel module, each
The input of described output channel module is all connected with all of input signal, the number of each output channel module
Be all connected with the data output end of data reception module according to input, the outfan of each output channel module is equal
Connect a road output channel.
Further, the figure place of described passage configuration-direct is come certainly by the way of input signal Yu output channel
Fixed.
Further, the input of described data reception module connects the defeated of microprocessor unit by bus
Go out end.
Further, described microprocessor unit this utility model, FPGA logic cell this utility model collection
Becoming in same double-core chip, the model of double-core chip is that Microsemi company of the U.S. produces
SmartFusion2 chip.
The beneficial effects of the utility model are:
1), this utility model microprocessor unit and FPGA logic cell are combined use, utilize micro-
Processor unit receives and parses through the passage configuration-direct from passage dispensing unit, and after resolving
Data transmission, to the data input pin of each output channel module, comes flexibly by changing passage configuration-direct
Change the input signal that each road output channel is corresponding；Changed by the number changing output channel module
Become output channel and the way of input signal, and this utility model be also equipped with simple in construction, with low cost,
Reliable and stable, be easy to the advantage promoted the use of.
Be worth it is emphasized that: this utility model is only protected by above-mentioned physical unit and connects each thing
Manage device or physical platform that the circuit between parts is constituted, without regard to software section therein.
2), described microprocessor unit, FPGA logic cell be integrated in same double-core chip, described
The model of double-core chip is the SmartFusion2 chip that Microsemi company of the U.S. produces, and improves
Operational efficiency of the present utility model and processing speed, enhance program portability, it is simple to secondary development.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model；
Fig. 2 is RTL schematic diagram of the present utility model；
Fig. 3 is the RTL view of signal selection module of the present utility model.
In figure, the implication of label symbol is as follows:
10 microprocessor unit 20 FPGA logic cell
21 data reception module 22 signal selection module
30 passage dispensing units
221～228 first output channel module～the 8th output channel modules
Detailed description of the invention
Below in conjunction with the accompanying drawing in this utility model embodiment, to the technology in this utility model embodiment
Scheme is clearly and completely described, it is clear that described embodiment is only this utility model one
Divide embodiment rather than whole embodiments.Based on the embodiment in this utility model, this area is common
The every other embodiment that technical staff is obtained under not making creative work premise, broadly falls into this
The scope of utility model protection.
As it is shown in figure 1, a kind of multiple signals multi-channel output device receives from passage dispensing unit 30
Passage configuration-direct, by change passage configuration-direct, it is achieved that this device outfan connect each
Road output channel is corresponding with input signal flexibly.
As in figure 2 it is shown, this device includes microprocessor unit 10 and FPGA logic cell 20, described micro-
Processor unit 10 is used for receiving and parsing through the passage configuration-direct from passage dispensing unit 30, and will
Data after parsing are stored in the buffer area of inside, and the outfan of described microprocessor unit 10 connects
The input of FPGA logic cell 20；Described FPGA logic cell 20 is for receiving from microprocessor
Data after the parsing of unit 10, the input of described FPGA logic cell 20 connects all of input
Signal, the outfan of FPGA logic cell 20 connects output channel；Described microprocessor unit 10, FPGA
The input end of clock of logical block 20 is all connected with clock signal.
Described FPGA logic cell 20 includes data reception module 21 and signal selection module 22, described
The input of data reception module 21 connects the outfan of microprocessor unit 10, data reception module 21
Data output end connect signal selection module 22 data input pin, described data reception module 21
Input end of clock connects clock signal；The input of described signal selection module 22 connects all of input
Signal, the outfan of signal selection module 22 connects output channel.
As it is shown on figure 3, described signal selection module 22 includes that 8 independent of one another and identical outputs are led to
Road module, respectively first output channel module the 221, second output channel module the 222, the 3rd output
The output of channel module the 223, the 4th output channel module the 224, the 5th output channel module the 225, the 6th is logical
Road module the 226, the 7th output channel module the 227, the 8th output channel module 228, each described output
The input of channel module is all connected with all of input signal, the data input pin of each output channel module
Being all connected with the data output end of data reception module 21, the outfan of each output channel module is all connected with
One tunnel output channel.
Described passage configuration-direct is made up of 32 bit binary data.
Described microprocessor unit 10, FPGA logic cell 20 are integrated in same double-core chip, described
The model of double-core chip is the SmartFusion2 chip that Microsemi company of the U.S. produces.
This utility model in use, can coordinate with software of the prior art and use.Below
In conjunction with software of the prior art, operation principle of the present utility model is described, it must be noted that
It is: the software matched with this utility model is not innovative part of the present utility model, is not this practicality
Novel ingredient.
As shown in Figures 1 to 3, the output intent of a kind of multiple signals multi-channel output device, its feature exists
In comprising the following steps:
S1, described microprocessor unit 10 receive the passage configuration-direct from passage dispensing unit 30
Post analysis passage configuration-direct, if described passage configuration-direct is by 000000000000000000000001
The 32 bit binary data compositions of 01000100, the 100 of the 0th to the 2nd of binary data are
1st group, expression for output channel Output0, corresponding input signal is Signal4, binary system
The 000 of the 3rd to the 5th of data is the 2nd group, expression for output channel Output1, corresponding
Input signal is Signal0 ..., the 000 of the 21st to the 23rd is the 8th group, expression for defeated
Going out passage Output7, corresponding input signal is Signal0, microprocessor unit 10 will resolve after number
According in the buffer area being stored in inside；
Data after S2, described microprocessor unit 10 will resolve again are passed through total by its internal buffer area
Line is sent to data reception module 21；
S3, described data reception module 21 data output end will resolve after data transmission defeated to each
Going out the data input pin of channel module, the input of each described output channel module is all connected with all of defeated
Enter signal, be Input0～Input5；The outfan of each described output channel module is all connected with a road
Output channel, the outfan such as the first output channel module 221 connects Output0；First output channel
The outfan of module 221 connects Output0；The outfan of the second output channel module 222 connects
Output1；
Corresponding input signal can be sent into defeated according to the data after resolving by S4, described output channel module
Go out in passage.As the input of the first output channel module 221 connects all of input signal it is
Input0～Input5, exports according to described first output channel module 221 corresponding in the data after resolving
The binary data of passage is 100, corresponding input signal Input4 i.e. Signal4 delivers to output logical
In road Output0；Logical according to described second output channel module 222 output corresponding in the data after resolving
The binary data in road is 000, and corresponding input signal Input0 i.e. Signal0 is delivered to output channel
In Output1.
Accordingly, for remaining output channel module, according to each output channel in the data after resolving
The binary data of module is 000, is sent into by the i.e. Signal0 of corresponding input signal Input0 corresponding
Output channel Outputi, non-Output2 and Output0 of described Outputi.
The input signal that each road output channel is corresponding is changed flexibly by changing passage configuration-direct；
The way of output channel and input signal is changed by the number changing output channel module.And this reality
With novel be also equipped with simple in construction, with low cost, reliable and stable, be easy to the advantage promoted the use of, this reality
It is widely used in various I/O channel field tests with novel.
Claims (6)
1. a multiple signals multi-channel output device, it is characterised in that: this device includes for connecing
Receive and resolve the microprocessor unit (10) of the passage configuration-direct from passage dispensing unit (30),
The outfan of described microprocessor unit (10) connects the input of FPGA logic cell (20)；Institute
The input stating FPGA logic cell (20) connects all of input signal, FPGA logic cell (20)
Outfan connect output channel；
When described microprocessor unit (10), the input end of clock of FPGA logic cell (20) are all connected with
Clock signal.
2. a kind of multiple signals multi-channel output device as claimed in claim 1, it is characterised in that:
Described FPGA logic cell (20) includes data reception module (21) and signal selection module (22),
The input of described data reception module (21) connects the outfan of microprocessor unit (10), data
The data output end of receiver module (21) connects the data input pin of signal selection module (22), described
The input end of clock of data reception module (21) connects clock signal；Described signal selection module (22)
Input connect all of input signal, the outfan of signal selection module (22) connects output channel.
3. a kind of multiple signals multi-channel output device as claimed in claim 2, it is characterised in that:
Described signal selection module (22) includes independent of one another and identical output channel module, each described defeated
The input going out channel module is all connected with all of input signal, the data input of each output channel module
End is all connected with the data output end of data reception module (21), and the outfan of each output channel module is equal
Connect a road output channel.
4. a kind of multiple signals multi-channel output device as claimed in claim 3, it is characterised in that:
The figure place of described passage configuration-direct is determined by the way of input signal with output channel.
5. a kind of multiple signals multi-channel output device as claimed in claim 3, it is characterised in that:
The input of described data reception module (21) connects the output of microprocessor unit (10) by bus
End.
6. a kind of multiple signals multi-channel output device as described in any one of claims 1 to 3, it is special
Levy and be: described microprocessor unit (10), FPGA logic cell (20) are integrated in same double-core core
In sheet, the model of double-core chip is the SmartFusion2 chip that Microsemi company of the U.S. produces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620367644.9U CN205721785U (en) | 2016-04-26 | 2016-04-26 | A kind of multiple signals multi-channel output device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620367644.9U CN205721785U (en) | 2016-04-26 | 2016-04-26 | A kind of multiple signals multi-channel output device |
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| Publication Number | Publication Date |
|---|---|
| CN205721785U true CN205721785U (en) | 2016-11-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620367644.9U Expired - Fee Related CN205721785U (en) | 2016-04-26 | 2016-04-26 | A kind of multiple signals multi-channel output device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105868507A (en) * | 2016-04-26 | 2016-08-17 | 安徽四创电子股份有限公司 | Multipath signal multichannel output device and output method thereof |
| CN112836463A (en) * | 2020-12-31 | 2021-05-25 | 北京百瑞互联技术有限公司 | Device, method, storage medium and equipment for integrated circuit IO port multiplexing |
-
2016
- 2016-04-26 CN CN201620367644.9U patent/CN205721785U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105868507A (en) * | 2016-04-26 | 2016-08-17 | 安徽四创电子股份有限公司 | Multipath signal multichannel output device and output method thereof |
| CN112836463A (en) * | 2020-12-31 | 2021-05-25 | 北京百瑞互联技术有限公司 | Device, method, storage medium and equipment for integrated circuit IO port multiplexing |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161123 Termination date: 20200426 |
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| CF01 | Termination of patent right due to non-payment of annual fee |