CN112836463A

CN112836463A - Device, method, storage medium and equipment for integrated circuit IO port multiplexing

Info

Publication number: CN112836463A
Application number: CN202011616701.XA
Authority: CN
Inventors: 葛颖峰; 李孙华; 徐祎喆; 朱勇
Original assignee: Barrot Wireless Co Ltd
Current assignee: Barrot Wireless Co Ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-05-25

Abstract

The application discloses a device, a method, a storage medium and equipment for integrated circuit IO port multiplexing design, and belongs to the technical field of integrated circuit design. The device mainly comprises a signal transmission module, a signal processing module and a signal processing module, wherein the signal transmission module simultaneously transmits N signals in a chip to each output end of M output ends in a hardware circuit, N is larger than M, and both N and M are positive integers; a multiplexing module that selects the N signals such that each of M output terminals in the hardware circuit corresponds to any one of the N signals; and the output module outputs the signal corresponding to each output end of the M output ends through the corresponding IO port. The method and the device greatly reduce the design complexity through the simplification of the algorithm, achieve the purpose that any signal is output in any sequence, and can achieve quite complex IO port multiplexing technology under the condition of no need of grouping.

Description

Device, method, storage medium and equipment for integrated circuit IO port multiplexing

Technical Field

The present application relates to the field of integrated circuit design technologies, and in particular, to an integrated circuit IO port multiplexing apparatus, method, storage medium, and device.

Background

In an embedded device, especially in an IoT embedded device that is widely used at present, in order to enable the IoT embedded device to be applied to various environments, a strict requirement is often imposed on a package size of a chip, which generally requires that the package size of the chip is small, and at the same time, the chip is required to have as many functions as possible inside the chip, so as to achieve flexibility and adaptability to various application scenarios.

The chip needs to have special interfaces, such as an I2C interface, a PWM interface, an I2S interface, and the like, for controlling various devices on the PCB, such as sensors, motors, audio communication, and the like. These interfaces often require pins that occupy the chip. But the smaller the chip package size the fewer the number of pins available. The package for an IoT chip typically has only 32 pins or even less, and typically only 20 pins or even less remain after power and control or signal pins that must be independent are removed.

In practical application, not only the chip is required to be reduced, but also the size of the PCB is often required to be very small, and the cost of the PCB is also required to be controlled, so that the size of the PCB cannot be reduced by using a multi-layer routing manner, and thus the chip is required to be matched with a specific PCB very flexibly, that is, after the chip is attached to the PCB, the pins of the chip are preferably directly aligned with the functional outlets of the PCB, and do not need to be wound around the PCB.

Disclosure of Invention

The application mainly provides a device, a method, a storage medium and equipment for integrated circuit IO port multiplexing design, so as to solve the problem that chip IO port pins need to be multiplexed for multiple times in integrated circuit design.

In order to solve the above problems, the present application adopts a technical solution that: an apparatus for integrated circuit IO port multiplexing design is provided, which includes: the signal transmission module is used for simultaneously transmitting N signals in the chip to each output end of M output ends in the hardware circuit, wherein N is larger than M, and both N and M are positive integers; a multiplexing module that selects the N signals such that each of M output terminals in the hardware circuit corresponds to any one of the N signals; and the output module outputs the signal corresponding to each output end of the M output ends through the corresponding IO port.

Another technical scheme adopted by the application is as follows: a method for designing integrated circuit IO port multiplexing is provided, which comprises the following steps: a signal transmission step, wherein N signals in the chip are simultaneously transmitted to each output end of M output ends in the hardware circuit, wherein N is larger than M, and both N and M are positive integers; a multiplexing step of selecting the N signals so that each output end of the M output ends in the hardware circuit corresponds to any one of the N signals; and an output step, namely outputting the signal corresponding to each output end in the M output ends through the corresponding IO port.

Another technical scheme adopted by the application is as follows: a computer readable storage medium is provided that stores computer instructions operable to perform the method of integrated circuit IO port multiplexing in scheme two.

Another technical scheme adopted by the application is as follows: there is provided a computer device comprising a processor and a memory, the memory storing computer instructions, wherein the processor operates the computer instructions to perform the method of integrated circuit IO port multiplexing in scheme two.

The technical scheme of the application can reach the beneficial effects that: the application designs a device, a method, a storage medium and equipment for integrated circuit IO port multiplexing. According to the scheme, one signal is selected from a plurality of signals transmitted to one output end to serve as an output signal, the complexity of IO port multiplexing design is reduced, and the signals do not need to be grouped, so that the complex IO port multiplexing function can be achieved.

Drawings

FIG. 1 is a schematic diagram of an embodiment of an apparatus for integrated circuit IO port multiplexing according to the present application;

FIG. 2 is a schematic diagram of an embodiment of an integrated circuit IO port multiplexing apparatus according to the present disclosure;

fig. 3 is a schematic diagram of an embodiment of a method for IO port multiplexing of an integrated circuit according to the present application.

Detailed Description

The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will provide those skilled in the art with a better understanding of the advantages and features of the present application, and will make the scope of the present application more clear and definite.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising.." does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the same element.

In the prior art, the integrated chip needs to have special interfaces, such as I2C interface, PWM interface, I2S interface and the like, for controlling various devices, such as sensors, motors, codecs and the like, on the integrated circuit board, the interfaces need to occupy a fixed number of pins, but the smaller the package size of the integrated chip, the fewer the number of pins available, and the fewer the number of pins that are left, typically 20 pins or even less, after power supply and signal pins that must be controlled independently are removed. The device, the method, the storage medium and the equipment for the IO port multiplexing design of the integrated circuit are applied to the integrated circuit design industry, and the problem that IO PAD needs to be multiplexed for multiple times in the integrated circuit design is solved.

Fig. 1 shows an embodiment of an integrated circuit IO port multiplexing apparatus according to the present application.

In the specific embodiment shown in fig. 1, the device for multiplexing the IO ports of the integrated circuit mainly includes a signal transmission module 101, which transmits N signals inside the chip to each of M output terminals in the hardware circuit, where N is greater than M, and N and M are both positive integers.

In this embodiment, the signal transmission module transmits the signal generated by the chip, and transmits N signals inside the chip to each of M output terminals in the hardware circuit at the same time, so that each output terminal faces N signal inputs at the same time, where N and M are positive integers, and N is greater than M. The complexity of the IO port multiplexing design is reduced by selecting one signal from the multiple signals transmitted to each output end as the output signal of the IO port pin, and the quite complex multiplexing function of the IO port can be realized without grouping the signals to perform the selective output of the signals.

In a specific embodiment of the present application, the device for multiplexing an IO port of an integrated circuit further includes a signal receiving module, which controls N input terminals of the hardware circuit to receive N signals inside the chip, where the N input terminals correspond to the N signals one to one. Each signal in the N signals waits for transmission at each input end in the N corresponding input ends respectively, so that the signal output does not need to be arranged and combined, the complexity of selecting the signal output sequence is reduced, and simultaneously, each output end is ensured to correspond to the input of the N signals simultaneously.

In a specific embodiment of the present application, in the signal receiving module, each of the N signals is simultaneously input to each of the N input terminals without repetition, so that the N input terminals correspond to the N signals one to one, thereby facilitating the selective output of the signal by the subsequent multiplexing module.

In one embodiment of the present application, assuming that a group of functional signals includes 100 signals, the input terminals of the corresponding hardware circuit are designed to have 100 ports, one signal corresponding to each input terminal. First, any one of the 100 signals selects one input terminal, and each signal can select only one input terminal, and the input terminals selected by each signal are not repeated.

Fig. 2 shows a specific example of an apparatus for IO port multiplexing of an integrated circuit according to the present application.

In the example shown in fig. 2, there are 5 signals at the input terminals, S0, S1, S2, S3, and S4, i.e., N is 5; the Output terminals include Output0, Output1 and Output2, i.e. M is 3. As shown in fig. 2, 5 signals are transmitted to 3 output terminals respectively through the signal transmission module, so that each output terminal has 5 signals from the input terminal. Each of the 5 signals is simultaneously input to each of the 5 input terminals through the signal receiving module without repetition, so that the 5 input terminals correspond to the 5 signals one to one.

In one embodiment of the present application, the N signals include a plurality of signals of the same kind and/or a plurality of signals of different kinds that perform a set of functions. Signals internal to the integrated circuit chip may include analog signals, digital signals, and mixed digital and analog signals. In order to ensure that the pins of the chip can be configured with a multiplexing function, a plurality of selected signals need to be capable of ensuring to complete a group of functions, and any one of the group of functional signals is ensured to be output to the outside of the chip through the pins of the chip in any sequence.

In the embodiment shown in fig. 1, the device for multiplexing an IO port of an integrated circuit according to the present application includes a multiplexing module 102, which selects N signals such that each of M outputs in a hardware circuit corresponds to any one of the N signals.

In this embodiment, the multiplexing module selects the signal to be transmitted. Each output terminal arbitrarily selects one signal among the N signals transmitted to the input terminal to realize output of the signals in an arbitrary order.

In one embodiment of the present application, in the multiplexer module, the N signals are selected by a plurality of selection elements according to a signal selection instruction of the central processing unit, wherein the selection elements include transistors or logic elements.

In this embodiment, the central processing unit sends different signal selection instructions to the storage unit, so that the multiplexing module controls different selection elements to be turned on, and a signal path corresponding to an output end of the hardware circuit is opened, so that a controlled signal is transmitted.

In one embodiment of the present application, the multiplexing module may design multiplexing according to the custom of a designer, wherein a logic gate may be used as the signal selection transmission channel, and a field effect transistor may also be used as the signal selection transmission channel. In the designed hardware circuit, each output end corresponds to N signal selection transmission channels, the N signal selection transmission channels correspond to N input ends, and each output end only selects one signal in the N signals.

In an embodiment of the present application, taking 5 signals transmitted to 3 output terminals as an example, as shown in fig. 2, 5 signals respectively select a port at an input terminal of a hardware circuit, one signal selects an input terminal, and 5 signals select 5 input terminals, for example, the input terminals S0, S1, S2, S3, and S4 respectively correspond to one signal, and the signals corresponding to each input terminal are different. Firstly, each signal corresponds to an input end, and a field effect tube circuit in the middle of a hardware circuit is used for realizing signal transmission; then each signal in each input terminal S0, S1, S2, S3, S4 is transmitted to the output terminals output0, output1, output2 of the hardware circuit through the fet circuit in the middle of the hardware circuit; the output0 selects a signal in one of the inputs S0, S1, S2, S3, S4, e.g., the output0 selects the signal in the input S2, the output1 selects the signal in the input S4, and the output2 selects the signal in the input S3; the chip pin corresponding to the output0 has the signal at the input terminal S2 as a signal that can be actually transmitted to the outside of the chip, the chip pin corresponding to the output1 has the signal at the input terminal S4 as a signal that can be actually transmitted to the outside of the chip, and the chip pin corresponding to the output2 has the signal at the input terminal S3 as a signal that can be actually transmitted to the outside of the chip.

In this particular example, the scheme changes from a complex decoding circuit to a simple path selection circuit. Similarly, in fig. 2, one of the 5 inputs, that is, S0, S1, S2, S3, and S4, may be arbitrarily selected as the output signal by the output terminal output0, and one of the 5 inputs, that is, S0, S1, S2, S3, and S4, may also be arbitrarily selected as the output signal by the output terminal output1 and the output terminal output2, so that the arbitrary signals may be output in an arbitrary order.

In the embodiment shown in fig. 1, the device for multiplexing an IO port of an integrated circuit according to the present application includes an output module 103, which outputs a signal corresponding to each of M output ports through the corresponding IO port.

In a specific embodiment of the present application, one of the N signals selected by each of the M output terminals in the hardware circuit is used as a signal that can be transmitted to the outside of the chip through an IO port pin in the chip.

In a specific example of the present application, for example, 100 signals are selected at each of 20 output terminals, one output terminal does not repeatedly select one specific signal during the process of inputting the corresponding 100 signals according to the instruction of the central processing unit, the 20 signals selected by the 20 output terminals have no specific sequence, and the 20 signals are simultaneously transmitted as output signals to the outside of the chip through the IO port pins in the chip to communicate with other chips or devices.

In an embodiment of the present application, each of the M output terminals is connected to a plurality of IO port pins in the chip in a one-to-one correspondence. The signal selected by each output end can be transmitted to the outside of the chip by the chip pin, and the multiplexing function of the chip IO port pin is realized.

In this embodiment, one pin in the chip can be used as both a signal input port and a signal output port. The scheme needs to design the interior of a chip to have as many functions as possible so as to realize flexibility and adaptability to various application scenes, a hardware circuit in the chip is designed to realize the arrangement idea that a plurality of output ends select one signal in a plurality of signals, in the process of logic design, the pins of the chip are ensured to be capable of transmitting signals to the outside of the chip, and each signal in the plurality of output ends is transmitted through the pins of the chip in different sequences.

In a specific example of the present application, the number of signals that can perform a set of functions inside the chip is not certain, and there may be hundreds of signals or tens of signals. The number of outputs of the hardware circuits involved inside the chip is limited, and is consistent with the number of pins of the chip, since the package of the chip usually has only 32 pins or less, and the package of the chip usually has only 20 pins or less left after the power supply and the signal pins which must be controlled independently are removed.

In the prior art, circuit designers have named IO MUX modules the modules that control the transfer of signals from a certain pin to a certain pin. If the IO MUX module wants to transmit any signal from the inside of the chip to any IO, and the sequence can be changed at will, the combination of the permutations needs to be implemented as follows:

for selecting 20 signals from 100 signals, the number of transfer modes required to be realized by the IO MUX module is

This is obviously not possible to achieve.

In one embodiment of the present application, under the conditions of the prior art, it is often necessary to group signals for simplicity many times in the actual chip logic design. For example, the SPI serial peripheral interface has 4 lines, i.e., a serial clock line, a master input/slave output data line, a master output/slave input data line, and a low-level active slave selection line, and the 4 lines may be grouped into a group, and the order of signal lines in the group is not changed. Only the order between the groups needs to be adjusted. Therefore, the implementation difficulty of the IO MUX module is greatly reduced. For example, there may be 8 sets of signals in total, and then only 5 sets would be simultaneously fed to the pins. The IO MUX module need only allow flexible changes to the groups of signals to the various pins of the chip. Even if the sequence of the groups needs to be changed arbitrarily, the number of the 8-group-by-5-group arrangement which needs to be realized is only 6720, and the IO MUX module can be completely realized. In the remaining three groups of signals, taking as an example that 3 groups are selected from the 3 groups to be sent out of the chip, the logic design circuit can be described as a decoding circuit like the following: assuming that three groups of signals are a, b and c respectively, the decoding circuit starts to select the sequence of the output groups as a, b and c when the binary code is 000; when the binary code is 001, the sequence of the output groups is b, a and c; when the binary code is 010, the order of the output groups is c, b, a; when the binary code is 011, the order of the output groups is a, c, b; when the binary code is 100, the order of the output groups is c, b, a; when the binary code is 101, the order of the output groups is b, c, a; however, such an implementation is not optimal, and is still somewhat insufficient in consideration of the difficulty of PCB wiring. It is still desirable in integrated circuit design to have any signal within the chip mapped independently to any pin outside the chip, which only allows the chip to be applied to any PCB layout scenario.

In a specific example of the present application, multiple fan-outs are achieved by using a digital circuit, that is, the maximum number of digital signals that can be driven by a single logic gate can be input, but the characteristic that multiple driving cannot be allowed is utilized to design a set of simplified algorithms, and then a hardware circuit is designed to implement the algorithm idea, so that the complexity of implementing the algorithms can be reduced.

In a specific example of the present application, a pin of a chip may only transmit a signal inside the chip at the same time, but may not transmit more than one signal, so that the solution of the algorithm may actually be converted into a signal starting from n sources and simultaneously transmitted to m end points, where n signals are transmitted simultaneously at each end point, and only 1 signal from the n simultaneously transmitted signals needs to be selected as a signal that can be really transmitted to the outside of the chip through the pin of the chip. This allows for the desired connection of any signals in any order, while reducing the complexity of the chip logic design.

The device for multiplexing the IO port of the integrated circuit can achieve flexibility and adaptability of the integrated circuit to various application scenes, and through the design of an internal hardware circuit of the integrated circuit, any signal can be output in any sequence due to the limited number of pins.

Fig. 3 shows an embodiment of a method for IO port multiplexing design of an integrated circuit according to the present application.

In a specific embodiment of the present application, the method for designing an IO port of an integrated circuit mainly includes a signal transmission step S301, where N signals inside a chip are simultaneously transmitted to each of M output terminals in a hardware circuit, where N is greater than M, and both N and M are positive integers.

In a specific embodiment of the present application, the method for designing an IO port of an integrated circuit mainly includes a multiplexing step S302 of selecting N signals so that each of M output terminals in a hardware circuit corresponds to any one of the N signals.

In a specific embodiment of the present application, the method for multiplexing design of an IO port of an integrated circuit mainly includes an output step S303, where a signal corresponding to each output terminal of M output terminals is output through the corresponding IO port.

The method for multiplexing design of the IO port of the integrated circuit provided by the present application can be used for implementing the device for multiplexing design of the IO port of the integrated circuit described in any of the above embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.

In another embodiment of the present application, a computer-readable storage medium stores computer instructions, wherein the computer instructions are operable to perform the method for IO port multiplexing design of an integrated circuit described in any of the embodiments.

In another embodiment of the present application, a computer device comprises a processor and a memory, the memory storing computer instructions, wherein the processor operates the computer instructions to perform the method for integrated circuit IO port multiplexing described in any of the embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings, which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

Claims

1. An apparatus for integrated circuit IO port multiplexing, comprising:

the signal transmission module is used for simultaneously transmitting N signals inside a chip to each output end of M output ends in a hardware circuit, wherein N is larger than M, and N and M are positive integers;

a multiplexing module that selects the N signals such that each of the M outputs in the hardware circuit corresponds to any of the N signals; and

and the output module outputs the signal corresponding to each output end of the M output ends through the corresponding IO port.

2. The integrated circuit IO port multiplexing device of claim 1, further comprising:

and the signal receiving module controls N input ends of the hardware circuit to receive N signals in the chip, wherein the N input ends correspond to the N signals one by one.

3. The device for integrated circuit IO port multiplexing of claim 2, wherein in the signal receiving module, the N input terminals are in one-to-one correspondence with the N signals by simultaneously inputting each of the N signals to each of the N input terminals without repeating.

4. The device for multiplexing IO ports of an integrated circuit of claim 1, wherein in the multiplexing module, the N signals are selected by a plurality of selection components according to a signal selection command of a central processing unit, wherein the selection components comprise transistors or logic components.

5. The device for integrated circuit IO port multiplexing of claim 1, wherein one of the N signals selected by each of M outputs in the hardware circuit is used as a signal that can be transmitted to the outside of the chip through an IO port pin in the chip.

6. The device for integrated circuit IO port multiplexing of claim 5, wherein each of the M output terminals is connected to a plurality of IO port pins in the chip in a one-to-one correspondence.

7. The device for integrated circuit IO port multiplexing of claim 1, wherein the N signals comprise a plurality of signals of the same kind and/or a plurality of signals of different kinds that perform a set of functions.

8. A method for multiplexing IO ports of an integrated circuit, comprising:

a signal transmission step, wherein N signals inside a chip are simultaneously transmitted to each output end of M output ends in a hardware circuit, wherein N is larger than M, and both N and M are positive integers;

a multiplexing step of selecting the N signals so that each of the M output terminals in the hardware circuit corresponds to any one of the N signals; and

and an output step, namely outputting the signal corresponding to each output end in the M output ends through a corresponding IO port.

9. A computer readable storage medium storing computer instructions, wherein the computer instructions are operable to perform the method of integrated circuit IO port multiplexing of claim 8.

10. A computer device comprising a processor and a memory, the memory storing computer instructions, wherein the processor operates the computer instructions to perform the method of integrated circuit IO port multiplexing of claim 8.