CN214122753U

CN214122753U - Multichannel radio frequency direct mining system

Info

Publication number: CN214122753U
Application number: CN202120399483.2U
Authority: CN
Inventors: 陆庆松; 胡罗林; 张华彬; 李昌杨; 段麒麟; 杨伟
Original assignee: Chengdu Phase Lock Electronic Technology Co Ltd
Current assignee: Chengdu Phase Lock Electronic Technology Co Ltd
Priority date: 2021-02-23
Filing date: 2021-02-23
Publication date: 2021-09-03
Anticipated expiration: 2031-02-23

Abstract

The utility model provides a multi-channel radio frequency direct acquisition system, which comprises a digital processing unit, an AD signal acquisition unit and a clock unit, wherein the digital processing unit is respectively connected with the AD signal acquisition unit and the clock unit, the digital processing unit comprises an FPGA chip and a DSP processor respectively connected with the FPGA chip, a plurality of high-speed ADC chips, a transceiver module and a 24-channel transmitting optical module, an ARM processor is connected with the DSP processor, the AD signal acquisition unit comprises a plurality of signal acquisition channels, the signal acquisition channels comprise an acquisition interface and a balun matching circuit which are sequentially connected, the output end of the balun matching circuit is connected with the high-speed ADC chips, the clock unit comprises a clock chip, the clock chip is respectively connected with the high-speed ADC chips, the FPGA chip is also connected with a first memory module, a trigger output module and a trigger input module, the utility model can realize synchronous acquisition and synchronous transmission and has high data transmission speed, the integration level is high.

Description

Multichannel radio frequency direct mining system

Technical Field

The utility model relates to a radio frequency signal gathers technical field, particularly, relates to a system is directly adopted to radio frequency of multichannel.

Background

The synchronous acquisition and processing card system of the multichannel ADC and the FPGA is mainly applied to the occasions requiring synchronous acquisition and processing of multichannel data, such as array signal processing, a multichannel radio monitoring direction-finding system, a communication radar testing instrument and the like, and the application requires that an acquisition and processing board has high-speed and high-precision data acquisition capacity, can synchronously acquire multichannel input signals, and performs high-speed data processing and high-speed data transmission.

Most of the current acquisition and processing boards in the industry are constructed by 1-2 ADC chips and FPGA chips, and have the defects of low sampling rate, incapability of adapting to multi-path synchronous high-speed high-precision acquisition and storage, small transmission bandwidth, poor signal processing and data processing capabilities and the like.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a system is directly adopted to radio frequency of multichannel, its VPX appearance structure that adopts 6U can realize synchronous acquisition and synchronous transmission, makes data transmission rate up to 10Gbps through connecting 24 passageway transmission optical module and receiving and dispatching integrated optical module, and data transmission is fast and the integrated level is high.

The embodiment of the utility model discloses a realize through following technical scheme:

a multi-channel radio frequency direct acquisition system comprises a digital processing unit, an AD signal acquisition unit and a clock unit, the AD signal acquisition unit and the clock unit are respectively connected with the digital processing unit, the digital processing unit comprises an ARM processor, an FPGA chip, a DSP processor, a plurality of high-speed ADC chips, a transceiver module and a 24-path transmitting optical module, the FPGA chip is respectively connected with the ARM processor, the DSP processor, the high-speed ADC chip, the transceiver module and the 24-path transmitting optical module, the ARM processor is connected with the DSP processor, the AD signal acquisition unit comprises a plurality of signal acquisition channels, the signal acquisition channel comprises an acquisition interface and a balun matching circuit which are connected in sequence, the output end of the balun matching circuit is connected with the high-speed ADC chip, the clock unit comprises clock chips which are respectively connected with the high-speed ADC chips.

Preferably, the FPGA chip is further connected to a first memory module, the first memory module includes a plurality of DDR4 memories, and the DDR4 memories are respectively connected to the FPGA chip.

Preferably, the FPGA chip is further connected with a trigger output module and a trigger input module respectively, an output end of the trigger output module is connected with a trigger output interface, and an input end of the trigger input module is connected with a trigger input interface.

Preferably, the DSP processor is further connected to a first ethernet transceiver, a second ethernet transceiver, a line driver, a four-bus buffer, an SPI flash memory, a NOR flash memory, and a second memory module, where the second memory module includes a DD3 memory and an ECC memory, the first ethernet transceiver is connected to a first network port communication interface, the second ethernet transceiver is connected to a second network port communication interface, and the line driver and the four-bus buffer are connected to a signal debugging interface, respectively.

Preferably, the digital processing unit further comprises a clock driving circuit, the clock driving circuit comprises a crystal oscillator, a clock distribution module, a clock generator and a clock driving module which are sequentially connected, the clock distribution module is further respectively connected with the ARM processor, the first ethernet transceiver and the second ethernet transceiver, the clock generator is further connected with the DSP processor, and the clock driving module is further respectively connected with the FPGA chip and the transceiver module.

Preferably, the ARM processor is further connected with an I2C multiplexing switch, and the I2C multiplexing switch is connected with a digital temperature sensor.

Preferably, the digital processing unit further comprises a power supply module, an input end of the power supply module is connected with the power supply input interface, and an output end of the power supply module is connected with the ARM processor.

Preferably, the digital processing unit further comprises a RapidIO chip, and the RapidIO chip is respectively connected with the FPGA chip, the DSP processor, the clock generator and the high-speed signal transmission interface.

Preferably, the clock chip is connected to a mixer, a power divider amplifier and a voltage controlled oscillator, an input end of the mixer is connected to a synchronous acquisition input interface and a crystal oscillator, an input end of the power divider amplifier is connected to a clock input interface, and an output end of the power divider amplifier is connected to the clock chip and a clock output interface.

Preferably, the transceiver optical module is connected with a Cage optical port, the 24-path transmitting optical module is connected with an MPT optical port, and the ARM processor is respectively connected with a hundred mega network port and a USB interface.

The utility model discloses technical scheme has following advantage and beneficial effect at least:

1. the utility model adopts a plurality of signal acquisition channels to acquire AD signals, and can realize synchronous acquisition and synchronous transmission;

2. the utility model has the transmitting and receiving optical module and the 24-path transmitting optical module, can realize 10Gbps data transmission, and has fast data transmission;

3. the utility model discloses a DSP treater has the giga net function, can be used to the injection and the receipt of data, also can realize data transmission and communication function

The utility model relates to a rationally, simple structure, the integrated level is high, the practicality is strong.

Drawings

Fig. 1 is a schematic structural diagram of a multi-channel radio frequency direct mining system provided in embodiment 1 of the present invention;

fig. 2 is a schematic structural diagram of an AD signal acquisition unit provided in embodiment 1 of the present invention;

fig. 3 is a schematic structural diagram of a DSP processor provided in embodiment 1 of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Example 1

As shown in fig. 1-3, a multi-channel rf direct sampling system includes a digital processing unit, an AD signal acquisition unit, and a clock unit, where the AD signal acquisition unit and the clock unit are respectively connected to the digital processing unit, the digital processing unit includes an ARM processor, an FPGA chip, a DSP processor, a plurality of high-speed ADC chips, a transceiver module, and 24-channel transmitter modules, the FPGA chip is respectively connected to the ARM processor, the DSP processor, the high-speed ADC chips, the transceiver module, and the 24-channel transmitter modules, the ARM processor is connected to the DSP processor, the AD signal acquisition unit includes a plurality of signal acquisition channels, the signal acquisition channels include an acquisition interface and a balun matching circuit that are sequentially connected, an output end of the balun matching circuit is connected to the high-speed ADC chips, and the clock unit includes a clock chip, the clock chips are respectively connected with the high-speed ADC chips.

The AD signal acquisition unit is used for acquiring AD signals and transmitting the AD signals to the digital processing unit, the balun matching circuit is used for converting the single-ended signals into differential signals and inputting the differential signals into the high-speed ADC chip, and the high-speed ADC chip transmits the sampled differential signals to the FPGA chip for storage and processing and forwards the differential signals to the DSP processor for signal processing. Each high-speed ADC chip respectively receives differential signals acquired and converted by two signal acquisition channels, and the clock chip respectively provides a sampling clock and a reference clock for each high-speed ADC chip. In this embodiment, there are eight signal acquisition channels and 4 high-speed ADC chips.

The FPGA chip is further connected with a first memory module, the first memory module comprises a plurality of DDR4 memories, and the DDR4 memories are respectively connected with the FPGA chip. The specific memory value of the DDR4 memory is 2 GB. In the present embodiment, the number of the DDRs 4 is four.

The FPGA chip is further connected with a trigger output module and a trigger input module respectively, the output end of the trigger output module is connected with a trigger output interface, and the input end of the trigger input module is connected with a trigger input interface.

The DSP treater still is connected with first ethernet transceiver, second ethernet transceiver, line driver, four bus buffer, SPI flash memory ware, NOR flash memory ware and second memory module respectively, the second memory module includes DD3 memory and ECC memory, first ethernet transceiver is connected with first net gape communication interface, the second ethernet transceiver is connected with second net gape communication interface, signal debugging interface is connected respectively to line driver and four bus buffer. Specifically, the memory value of the DDR3 memory is 2GB, and the memory value of the ECC memory is 4 GB.

The digital processing unit further comprises a clock driving circuit, the clock driving circuit comprises a crystal oscillator, a clock distribution module, a clock generator and a clock driving module which are sequentially connected, the clock distribution module is further respectively connected with the ARM processor, the first Ethernet transceiver and the second Ethernet transceiver, the clock generator is further connected with the DSP processor, and the clock driving module is further respectively connected with the FPGA chip and the transceiver optical module. Specifically, the crystal oscillator adopts 100MHz, and the first ethernet transceiver and the second ethernet transceiver are used for ethernet port communication.

The ARM processor is further connected with an I2C multiplexing switch, and the I2C multiplexing switch is connected with a digital temperature sensor. The I2C multiplexing switch is used to expand the I2C channel count of the ARM processor and the digital temperature sensor is used to detect the temperature of the ARM processor.

The digital processing unit further comprises a power supply module, the input end of the power supply module is connected with the power supply input interface, and the output end of the power supply module is connected with the ARM processor.

The digital processing unit further comprises a RapidIO chip, and the RapidIO chip is respectively connected with the FPGA chip, the DSP processor, the clock generator and the high-speed signal transmission interface. The RapidIO chip is used for carrying out high-speed data transmission among the back plate, the FPGA chip and the DSP processor.

The clock chip is connected with a frequency mixer, a power distribution amplifier and a voltage-controlled oscillator respectively, the input end of the frequency mixer is connected with a collection synchronous input interface and a crystal oscillator respectively, the input end of the power distribution amplifier is connected with a clock input interface, and the output end of the power distribution amplifier is connected with the clock chip and a clock output interface.

The receiving and transmitting optical module is connected with a Cage optical port, the 24-path transmitting optical module is connected with an MPT optical port, and the ARM processor is respectively connected with a hundred-million network port and a USB interface.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-channel radio frequency direct acquisition system is characterized by comprising a digital processing unit, an AD signal acquisition unit and a clock unit, the AD signal acquisition unit and the clock unit are respectively connected with the digital processing unit, the digital processing unit comprises an ARM processor, an FPGA chip, a DSP processor, a plurality of high-speed ADC chips, a transceiver module and a 24-path transmitting optical module, the FPGA chip is respectively connected with the ARM processor, the DSP processor, the high-speed ADC chip, the transceiver module and the 24-path transmitting optical module, the ARM processor is connected with the DSP processor, the AD signal acquisition unit comprises a plurality of signal acquisition channels, the signal acquisition channel comprises an acquisition interface and a balun matching circuit which are connected in sequence, the output end of the balun matching circuit is connected with the high-speed ADC chip, the clock unit comprises clock chips which are respectively connected with the high-speed ADC chips.

2. The multi-channel radio frequency direct sampling system according to claim 1, wherein the FPGA chip is further connected with a first memory module, the first memory module comprises a plurality of DDR4 memories, and the DDR4 memories are respectively connected with the FPGA chip.

3. The multi-channel radio frequency direct sampling system according to claim 1, wherein the FPGA chip is further connected to a trigger output module and a trigger input module, respectively, an output end of the trigger output module is connected to a trigger output interface, and an input end of the trigger input module is connected to a trigger input interface.

4. The multi-channel radio frequency direct sampling system according to claim 1, wherein the DSP processor is further connected with a first ethernet transceiver, a second ethernet transceiver, a line driver, a four-bus buffer, an SPI flash memory, a NOR flash memory, and a second memory module, respectively, the second memory module includes a DD3 memory and an ECC memory, the first ethernet transceiver is connected with a first net-port communication interface, the second ethernet transceiver is connected with a second net-port communication interface, and the line driver and the four-bus buffer are connected with a signal debugging interface, respectively.

5. The multi-channel radio frequency direct sampling system according to claim 4, wherein the digital processing unit further comprises a clock driving circuit, the clock driving circuit comprises a crystal oscillator, a clock distribution module, a clock generator and a clock driving module which are sequentially connected, the clock distribution module is further respectively connected with the ARM processor, the first Ethernet transceiver and the second Ethernet transceiver, the clock generator is further connected with the DSP processor, and the clock driving module is further respectively connected with the FPGA chip and the transceiver module.

6. The multi-channel radio frequency direct recovery system of claim 1 wherein the ARM processor is further coupled to an I2C multiplexing switch, the I2C multiplexing switch being coupled to a digital temperature sensor.

7. The multi-channel radio frequency direct sampling system according to claim 1, wherein the digital processing unit further comprises a power supply module, an input end of the power supply module is connected to the power input interface, and an output end of the power supply module is connected to the ARM processor.

8. The multi-channel radio frequency direct sampling system according to claim 5, wherein the digital processing unit further comprises a RapidIO chip, and the RapidIO chip is respectively connected with the FPGA chip, the DSP processor, the clock generator and the high-speed signal transmission interface.

9. The multi-channel radio frequency direct sampling system according to claim 1, wherein the clock chip is connected to a mixer, a power divider amplifier and a voltage controlled oscillator, the mixer has an input connected to a sampling synchronization input interface and a crystal oscillator, the power divider amplifier has an input connected to a clock input interface, and the power divider amplifier has an output connected to the clock chip and a clock output interface.

10. The multi-channel radio frequency direct sampling system according to claim 1, wherein the transceiver optical module is connected to a Cage optical port, the 24-channel transmitter optical module is connected to an MPT optical port, and the ARM processor is connected to a gigabit network port and a USB interface, respectively.