CN211127781U - FMC card for analog-digital conversion - Google Patents
FMC card for analog-digital conversion Download PDFInfo
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- CN211127781U CN211127781U CN202020342542.8U CN202020342542U CN211127781U CN 211127781 U CN211127781 U CN 211127781U CN 202020342542 U CN202020342542 U CN 202020342542U CN 211127781 U CN211127781 U CN 211127781U
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Abstract
The utility model discloses an analog-to-digital conversion's FMC card relates to information processing's technical field, has solved prior art and has been difficult to satisfy the technical problem to the transmission requirement of high-speed data. The FMC comprises a high-frequency analog signal input end, an FMC interface, an analog-digital acquisition chip and a clock chip, wherein a clock signal output end of the clock chip is connected with a clock terminal of the FMC interface, a clock signal output end of the clock chip is also connected with the analog-digital acquisition chip, an input end of the analog-digital acquisition chip is connected with the high-frequency analog signal input end, and an output end of the analog-digital acquisition chip is connected with a digital terminal of the FMC interface through a high-speed serial channel. The utility model discloses the realization has avoided the problem that parallel transmission brought to the high-speed serial transmission of data, and need not design buffer and sample hold circuit, has optimized the structure of FMC card, still need not to introduce outside clock, does benefit to the effective utilization of port.
Description
Technical Field
The present invention relates to information processing, and more particularly, to an FMC card for analog-to-digital conversion.
Background
The signal processing platform takes a digital signal processing technology as a core, and is widely applied to the fields of radars, aerospace, videos, digital communication, image processing, robots and the like. The development of information technology is fast, and the requirements of people on the data demand and the data transmission speed are continuously improved. High-speed data transmission requires high sampling speed and sampling precision, and higher requirements are put forward for a converter with high sampling rate and high sampling precision.
In order to meet the transmission requirement of high-speed data, a parallel transmission mode is generally adopted. The parallel transmission improves the high sampling precision, but leads to more pins and more difficult wiring by improving the data bit width; the high sampling rate is improved through parallel transmission, but electromagnetic interference among pins is increased and intersymbol interference is increased through clock improvement; in addition, parallel transmission of clock and data synchronization is more difficult.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is not enough to prior art, provides an analog-to-digital conversion's FMC card, has realized the transmission to high-speed data.
The technical scheme of the utility model lies in: an FMC card for analog-digital conversion comprises a high-frequency analog signal input end, an FMC interface, an analog-digital acquisition chip and a clock chip, wherein a clock signal output end of the clock chip is connected with a clock terminal of the FMC interface, a clock signal output end of the clock chip is further connected with a clock signal input end of the analog-digital acquisition chip, an input end of the analog-digital acquisition chip is connected with the high-frequency analog signal input end, and an output end of the analog-digital acquisition chip is connected with a digital terminal of the FMC interface through a high-speed serial channel.
The analog-digital acquisition chip is an AD6688 chip.
The high-speed serial channel is a JESD204B x8 interface channel.
The clock chip is an HMC7044 chip.
The FMC card further comprises a temperature-controlled oscillator and a voltage-controlled clock oscillator, the temperature-controlled oscillator is connected with a first frequency input end of the clock chip, and the voltage-controlled clock oscillator is connected with a second frequency input end of the clock chip.
The FMC interface is connected with a synchronous input end of the analog-digital acquisition chip through a synchronous signal channel.
The FMC interface is electrically connected with a temperature sensor.
The FMC interface is electrically connected with an EEPROM.
The clock chip comprises a first clock signal output end, a second clock signal output end and a third clock signal output end, wherein the first clock signal output end is connected with a first clock input end of the FMC interface, the second clock signal output end is connected with a second clock input end of the FMC interface, and the third clock signal output end is connected with a third clock input end of the FMC interface; the first clock signal output end is also connected with a first clock input end of the analog-digital acquisition chip, and the second clock signal output end is also connected with a second clock input end of the analog-digital acquisition chip;
the clock chip also comprises a serial input port which is connected with a serial output port of the FMC interface through a serial bus.
Advantageous effects
The utility model has the advantages that: the analog-digital acquisition chip on the FMC card is connected with the input end of the high-frequency analog signal, the high-adoption-rate high-speed conversion of high-speed data is realized by directly acquiring and converting the high-frequency analog signal through the analog-digital acquisition chip, a buffer and a sampling holding circuit are not required to be designed for the FMC card, the structure of the FMC card is optimized, the low-power-consumption performance of the FMC card is realized, and the size of the FMC card is reduced. The analog-digital acquisition chip is connected with a digital terminal of the FMC interface through a high-speed serial channel so as to realize high-speed serial transmission of data and avoid the problems caused by parallel transmission. The FMC card also provides a homologous clock for a clock terminal of the FMC interface and the analog-digital acquisition chip through the clock chip, so that the FMC card does not need to introduce an external clock, and the effective utilization of a port is facilitated.
Drawings
Fig. 1 is a schematic structural diagram of an analog-to-digital conversion FMC card of the present invention.
Detailed Description
The present invention will be further described with reference to the following examples, which are not intended to limit the scope of the present invention, but are intended to be covered by the appended claims in any way.
Referring to fig. 1, the present invention relates to an analog-to-digital conversion FMC card, which comprises a high frequency analog signal input terminal, an FMC interface, an analog-to-digital acquisition chip and a clock chip, wherein the FMC interface employs a four-hundred pin HPC connector, which has ten pins in total and forty pins in each row, when the FMC interface employs a L PC connector, which only includes four pins in total and a L PC connector having one hundred and sixty pins in total, so that the HPC connector with high pin count is a L PC connector compatible with low pin count during design, and can be subsequently extended in series based on the existing design.
The clock signal output end of the clock chip is connected with the clock terminal of the FMC interface, and the clock signal output end of the clock chip is also connected with the analog-digital acquisition chip. The clock chip provides a homologous clock for the FMC card, so that the FMC card does not need to introduce an external clock, and the effective utilization of the port is facilitated. The clock chip is an HMC7044 chip.
In addition, the HMC7044 chip has two integer modes P LL which can be selected through a serial bus SPI and an overlapped on-chip VCO, the tuning ranges of the two integer modes P LL and the overlapped on-chip VCO respectively reach 2.5GHz and 3 GHz.
The clock chip also comprises a serial input port which is connected with a serial output port of the FMC interface through a serial bus SPI. Namely, the HMC7044 chip is also connected to the FMC interface through the serial bus SPI to enable writing of corresponding management and control information to the control registers of the HMC7044 chip.
The clock chip comprises a first clock signal output end, a second clock signal output end and a third clock signal output end. The first clock signal output end is connected with the first clock input end of the FMC interface, the second clock signal output end is connected with the second clock input end of the FMC interface, and the third clock signal output end is connected with the third clock input end of the FMC interface. The first clock signal output end is further connected with a first clock input end of the analog-digital acquisition chip, and the second clock signal output end is further connected with a second clock input end of the analog-digital acquisition chip.
The HMC7044 chip may configure the output signal path as a Device Clock signal or a SYSREF Clock signal, or as more reference clocks that may be independently adjusted in phase and frequency, as desired. In the HMC7044 chip of this embodiment, the first Clock signal output terminal provides a Device Clock signal to the FMC interface, the second Clock signal output terminal provides a SYSREF Clock signal to the FMC interface, and the third Clock signal output terminal provides a GTXREF Clock signal to the FMC interface. Namely, the HMC7044 chip provides three Clock signals of Device Clock, SYSREF and GTXREF to the field programmable gate array FPGA connected with the FMC interface module. In addition, the first Clock signal output end of the HMC7044 chip also provides a SYSREF Clock signal, and the second Clock signal output end of the HMC7044 chip also provides a Device Clock signal to the analog-digital acquisition chip.
The FMC card of this embodiment further includes a temperature controlled oscillator TCXO and a voltage controlled clock oscillator VCXO. Wherein, the temperature controlled oscillator TCXO is a crystal oscillator which controls frequency output through temperature; the voltage controlled clock oscillator VCXO is a crystal oscillator that controls frequency output by voltage. The temperature-controlled oscillator TCXO is connected with a first frequency input end of the clock chip, and the voltage-controlled clock oscillator VCXO is connected with a second frequency input end of the clock chip and used for providing oscillation frequency for the HMC7044 chip.
Specifically, the HMC7044 chip has two phase locked loops P LL and an overlapping on-chip voltage controlled oscillator VCO the first phase locked loop P LL locks a low noise voltage controlled clock oscillator VCXO to a relatively noisy reference, while the second phase locked loop P LL multiplies the voltage controlled clock oscillator VCXO signal to the voltage controlled oscillator VCO frequency, adding only very little noise.
The input end of the analog-digital acquisition chip is connected with the input end of the high-frequency analog signal so as to acquire the high-frequency analog signal. The analog-digital acquisition chip is an AD6688 chip, a buffer, a sampling holding circuit and a broadband digital down converter DDC are contained in the chip, and input high-frequency analog signals can be processed, so that the FMC card does not need to design the buffer and the sampling holding circuit, the structure of the FMC card is optimized, the low power consumption performance of the FMC card is realized, and the size of the FMC card is reduced.
The AD6688 chip is a 1.2GHz bandwidth, mixed signal, direct RF sampling receiver. The digital-to-analog converter consists of two fourteen-bit 3.0GSPS analog-to-digital converters (ADC), various digital signal processing modules and four broadband digital down-converters (DDC). The ADC core of the dual-mode digital converter is provided with a multi-stage and differential pipeline architecture, and is integrated with output error correction logic and a reference voltage source, so that design consideration is simplified. Also, the analog input and clock signal of the AD6688 chip are differential inputs. The data output of the analog-to-digital converter ADC is internally connected to the four wideband digital down-converters DDC through a crossbar multiplexer. Each wideband digital down-converter DDC comprises at most five cascaded signal processing stages: and the numerically controlled oscillator NCO can select a preset frequency band pin on the general input/output, and can select three frequency bands at most.
And a serial input port of the analog-digital acquisition chip is connected with a serial output port of the FMC interface through a serial bus SPI. I.e. the user can also select the AD6688 chip operation programmable configuration file between the DDC modes of the wideband digital down-converter through the serial bus SPI.
Besides the DDC module, the AD6688 chip also has multiple functions, which can simplify the automatic gain control. The programmable threshold detector allows monitoring of the input signal power using fast detection control bits in register 0x0245 of the analog-to-digital converter ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because the fast detection indicator has low latency, the user can quickly reduce the system gain to avoid an over-range condition at the ADC input. In addition to the fast detection output, the AD6688 chip also provides a signal monitoring function. The AD6688 chip has a flexible power down option that can save a lot of power when needed.
The high-frequency analog signal input end on the FMC card is connected with the analog input end CHA and the analog input end CHB of the AD6688 chip so as to directly input the high-frequency analog signal to the AD6688 chip without a sampling and holding circuit, and the size of the FMC card is effectively reduced. The AD6688 chip achieves high sampling speed and sampling accuracy for the input signal. The AD6688 chip is integrated on the FMC card, so that the FMC card not only provides acquisition of multiple paths of analog signals, but also can receive high-frequency signals, can directly sample broadband analog signals up to 5GHz, and meets the requirements of high-speed data on high adoption speed and sampling precision.
The output end of the analog-digital acquisition chip is connected with the digital terminal of the FMC interface through the high-speed serial channel so as to realize high-speed transmission of data and avoid the problems caused by parallel transmission. Specifically, the high-speed serial channel is a JESD204B x8 interface channel. That is, the high-frequency analog signal is directly input to the analog input CHA and the analog input CHB of the AD6688 chip, and a 14-bit digital signal is output through the JESD204B x8 interface channel after analog-to-digital conversion. The high-speed data transmission is realized by the conversion of the AD6688 chip with high sampling speed and sampling precision to high-frequency analog signals and the transmission of digital signals by the high-speed serial channel JESD204B x8 interface channel.
The JESD204B series protocol standard is mainly used for data transmission of converters and logic devices, such as Field Programmable Gate Arrays (FPGAs) and programmable chip ASICs, and has the advantages of small packaging area, small wiring quantity, reduced system design cost, lower power consumption and the like, is more convenient for board-level PCB design, and has stronger practicability.
Compared with the conventional interfaces, such as CMOS, L VDS and the like, the JESD204B interface has the following advantages:
first, the system design is simplified. When using the conventional interface, if the number of channels of the analog-to-digital converter ADC is large, the wiring between the analog-to-digital converter ADC and the field programmable gate array FPGA will be very dense, and the wiring length of each channel needs to be the same, otherwise the data quality may be deteriorated, which is relatively troublesome to implement. The JESD204B interface can be used to greatly simplify the wiring between the ADC and the FPGA.
Second, the number of pins is reduced. Compared with the traditional interface, the JESD204B interface can greatly reduce the pin number, thereby reducing the cost of the board arrangement.
Third, the use of the JESD204B interface will make the package smaller and simpler, since the wiring is simpler and the pin count is smaller.
Fourth, the data rate advantage of the JESD204B interface will result in large bandwidth.
The JESD204B interface is specific to high data rate systems. The 3.2GHz HMC7044 chip clock jitter attenuator is internally provided with a unique function which can support and enhance the standard characteristic of the JESD204B interface. The HMC7044 chip provides 50fs jitter performance and improves the signal-to-noise ratio and dynamic range of high speed data converters. The HMC7044 chip also provides fourteen low noise and configurable outputs that can flexibly interface with many different devices, allowing designers to build a complete clock design with a single device. The HMC7044 chip clock jitter attenuator may generate source-synchronous and adjustable sample and frame alignment SYSREF clocks in a data converter system, simplifying the JESD204B interface design.
In summary, the application of the JESD204B interface to the FMC card not only meets the requirement of high-speed data transmission, but also reduces the number of input/output pins between the logic device and the converter.
The FMC interface is connected with a synchronous input end of the analog-digital acquisition chip through a synchronous signal channel. Synchronous signal SYNC carries out digital signal's control processing on transmitting AD6688 chip through the FMC interface, can realize that polylith AD6688 chip carries out the purpose of gathering in step, can be used to the data acquisition who constructs many high frequency analog signal passageway, has realized the collection to multichannel high frequency analog signal.
The FMC card of this embodiment is further provided with a trigger input port for inputting a trigger signal TRIG. The trigger signal TRIG is directly input to the FMC interface from the outside to inform the field programmable gate array FPGA when it receives the converted data of the AD6688 chip.
The FMC interface is electrically connected with a temperature sensor. The temperature sensor is used for detecting the working temperature of the FMC card and sending the detected temperature information to the field programmable gate array FPGA through the FMC interface; the FPGA judges whether the working environment of the FMC card is proper or not according to the temperature value, and if the working environment of the FMC card is smaller than the normal working threshold temperature value of the FMC card, a heater is started; and if the temperature is higher than the normal working threshold temperature value of the FMC card, starting the fan to provide a proper working environment for the FMC card.
The FMC interface is electrically connected with an EEPROM.
The EEPROM and the temperature sensor of the embodiment are both provided with I2The C bus is connected with the FMC interface. I.e. EEPROM and temperature sensor both pass I2The C bus is communicated with the field programmable gate array FPGA.
The above is only the preferred embodiment of the present invention, and it should be noted that for those skilled in the art, without departing from the structure of the present invention, several modifications and improvements can be made, which will not affect the utility model and the utility of the patent.
Claims (9)
1. The FMC card for analog-digital conversion is characterized by comprising a high-frequency analog signal input end, an FMC interface, an analog-digital acquisition chip and a clock chip, wherein a clock signal output end of the clock chip is connected with a clock terminal of the FMC interface, a clock signal output end of the clock chip is also connected with a clock signal input end of the analog-digital acquisition chip, an input end of the analog-digital acquisition chip is connected with the high-frequency analog signal input end, and an output end of the analog-digital acquisition chip is connected with a digital terminal of the FMC interface through a high-speed serial channel.
2. An FMC card according to claim 1 characterised in that the analogue-to-digital converter is an AD6688 chip.
3. An analog-to-digital converted FMC card as in claim 1, wherein said high speed serial channel is JESD204B x8 interface channel.
4. An analog-to-digital converted FMC card as in claim 1, wherein said clock chip is an HMC7044 chip.
5. An FMC card according to claim 1 or 4 characterised in that it further comprises a temperature controlled oscillator connected to a first frequency input of the clock chip and a voltage controlled clock oscillator connected to a second frequency input of the clock chip.
6. An analog-to-digital converted FMC card according to claim 1 or 2, wherein the FMC interface is connected to the synchronization input of the analog-to-digital acquisition chip through a synchronization signal channel.
7. An analog-to-digital converted FMC card as in claim 1, wherein said FMC interface is electrically connected to a temperature sensor.
8. The FMC card for analog-to-digital conversion of claim 1, wherein said FMC interface is electrically connected to an EEPROM.
9. An analog-to-digital (FMC) card according to claim 1 or 4, characterised in that said clock chip comprises a first clock signal output coupled to a first clock input of the FMC interface, a second clock signal output coupled to a second clock input of the FMC interface, and a third clock signal output coupled to a third clock input of the FMC interface; the first clock signal output end is also connected with a first clock input end of the analog-digital acquisition chip, and the second clock signal output end is also connected with a second clock input end of the analog-digital acquisition chip;
the clock chip also comprises a serial input port which is connected with a serial output port of the FMC interface through a serial bus.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020342542.8U CN211127781U (en) | 2020-03-18 | 2020-03-18 | FMC card for analog-digital conversion |
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| CN202020342542.8U CN211127781U (en) | 2020-03-18 | 2020-03-18 | FMC card for analog-digital conversion |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112104366A (en) * | 2020-08-30 | 2020-12-18 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Four-channel high-speed synchronous FMC acquisition device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112104366A (en) * | 2020-08-30 | 2020-12-18 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Four-channel high-speed synchronous FMC acquisition device |
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