CN203708224U - Multipurpose serial time code decoder - Google Patents
Multipurpose serial time code decoder Download PDFInfo
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- CN203708224U CN203708224U CN201420066611.1U CN201420066611U CN203708224U CN 203708224 U CN203708224 U CN 203708224U CN 201420066611 U CN201420066611 U CN 201420066611U CN 203708224 U CN203708224 U CN 203708224U
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Abstract
The utility model discloses a multipurpose serial time code decoder, so as to achieve the goal of precise time synchronization among various electric power automation devices. The decoder comprises an external input modulation circuit, a main control circuit and a signal output circuit. The main control circuit is connected to the external input modulation circuit to receive an externally input serial time code and covert the time code into multipath time setting signals using different interfaces. The external input modulation circuit is connected to the main control circuit to output the multipath time setting signals using different interfaces. Based on a high-end field programmable gate array platform, the decoder utilizes an advanced system on chip and a hardware logic modularization design mode, and meets the requirements of different time setting interfaces and different time setting precision of various automation equipment, in combination with the advantages of rich resources of input and output ports of the field programmable gate array.
Description
Technical field
The utility model relates to power domain, particularly a kind of multipurpose serial timing code decoder.
Background technology
U.S. target range instrument group (Inter-Range Instrumentation Group, be called for short IRIG) time standard have two large classes: a class is parallel time code form, and this class code is owing to being parallel form, and transmission range is nearer, and be binary system, therefore can not show a candle to serial form extensive; Another kind of is serial timing code, has six kinds of forms, i.e. A, B, D, E, G, H.Their main difference is the frame rate difference of timing code, and IRIG-B is Type B code wherein.
The frame rate of IRIG-B was 1 frame/second, and every frame can transmit the information of 100, and its content has comprised the information such as year life Hour Minute Second and leap second correction, can obtain the pulse signal of multi-frequency and current temporal information after decoding.IRIG-B code to time mode have advantages of that data are abundant, time precision is high and do not need additionally to arrange data; Shortcoming is to carry out the Code And Decode more complicated than serial mode.
The research of electric grid secondary system time simultaneous techniques specification has just clearly been proposed to accelerate in " about the notice of strengthening electric power secondary system Clock management " that State Grid Corporation of China issues, progressively adopt IRIG-B standard implementation global positioning system (Global Positioning System, be called for short GPS) timing device and related system or equipment to time, synchronous calibration relative time and absolute time, critical system and equipment should support to receive standby clock source to time signal, with safeguards system safety.The time precision of timing device should be not less than 7 × 10 under normal circumstances
-7second/minute.
In electric power system, Electric Power Automation Equipment is numerous, and time synchronized clock, time synchronizing method and transmission medium to time synchronized require to be also not quite similar.Therefore, electric power system clock synchronization system should have specific aim and flexibility concurrently, meets different Electric Power Automation Equipment time synchronized demands.At present, the time synchronizing method that Electric Power Automation Equipment can be selected have pulse mode, serial ports message mode, IRIG-B code to time four kinds of mode and network modes.For example calculating fee of electric energy system requirements precision is less than 0.5s, use network to time or serial ports message to time; Distribution automation system precision prescribed is less than 10ms, use serial ports message to time; Fault oscillograph precision prescribed is less than 1ms, use IRIG-B or pulse per second (PPS) (PPS)/point pulse (PPM) add serial ports message to time mode; Require the highest equipment, as circuit traveling wave fault location device, synchronous phasor measuring device and lightning location system etc., precision must reach the level of 1us, use IRIG-B or pulse per second (PPS) (PPS)/point pulse (PPM) add serial ports message to time mode.
The design of traditional IRIG-B decoder is (the Complex Programable Logic Device of the CPLD based on low side often, be called for short CPLD) compound mode of CPLD and single-chip microcomputer, be confined to CPLD logic gate number limited, the not high factor of single-chip microcomputer performance, this mode cost is high, complex structure, practical function is single, precision is not high yet, usually occurs the situation of decoding error, and there is significant limitation complicated application scenario at the scene.The utility model is given full play to the performance advantage of Novel site programmable gate array, well-designed and emulation, integrated whole system on a chips, reduce the design of a large amount of peripheral circuits, greatly reduce volume and the power consumption of equipment, met the sync cap demand of different power equipments, and improved precision, through on-the-spot test and application, obtain good result of use.
Utility model content
The utility model, in order to meet the demand of following intelligent grid to time synchronized, for prior art weak point, provides a kind of multipurpose serial timing code decoder, to realize the object of various Electric Power Automation Equipment exact time synchronization.
The utility model is for reaching technical requirement by the following technical solutions:
The multipurpose serial timing code decoder that the utility model provides comprises outside input modulation circuit, governor circuit and signal output apparatus, wherein governor circuit is connected with outside input modulation circuit, to receive the serial timing code of outside input, and be converted to multichannel distinct interface to time signal; Outside input modulation circuit, is connected with governor circuit, with output multi-channel distinct interface to time signal.
Alternatively, governor circuit comprises: field programmable gate array chip, series arrangement device, SDRAM chip, constant-temperature crystal oscillator, reset circuit, wherein, field programmable gate array chip is main control chip, is connected respectively with series arrangement device, SDRAM chip, constant-temperature crystal oscillator and reset circuit.
Alternatively, field programmable gate array chip comprises: DC B code decoder module, alternating-current B code decoder module, time bias module, phase-locked loop module, pulse generating module, SOC (system on a chip).
Alternatively, signal output apparatus comprises: high speed photo coupling, RS232 transceiving chip, RS485 transceiving chip, ethernet transceiver, wherein, high speed photo coupling output pulse and direct current form to time signal; RS232 transceiving chip output RS232 form to time signal; RS485 transceiving chip output RS485 form to time signal; Ethernet transceiver output network message form to time signal.
Alternatively, outside input modulation circuit comprises: A/D convertor circuit, to receive the interchange serial time code signal of outside input; DC isolation circuit, to receive the direct current serial time code signal of outside input.
Compared with prior art, the utility model has the advantage of: the field programmable gate array platform based on high-end, adopt advanced SOC (system on a chip) and hardware logic modularized design mode, its on single-chip, realized to time mode flexible collocation, in decoding, output accuracy can compensation adjustment IRIG-B code, pulse signal, serial ports to time message and network time message, and reserved design space for later expansion interface, in conjunction with the resourceful advantage of input/output port of field programmable gate array.Met various automation equipments for difference to time interface and different to time precision requirement.Meanwhile, the utility model has been accomplished to have ensured the quick application on Different field programmable gate array chip, has effectively been reduced product cost.
According to the detailed description to the utility model specific embodiment by reference to the accompanying drawings below, those skilled in the art will understand above-mentioned and other objects, advantage and feature of the present utility model more.
Brief description of the drawings
Hereinafter describe specific embodiments more of the present utility model in detail in exemplary and nonrestrictive mode with reference to the accompanying drawings.In accompanying drawing, identical Reference numeral has indicated same or similar parts or part.It should be appreciated by those skilled in the art that these accompanying drawings may not draw in proportion.In accompanying drawing:
Fig. 1 is according to the circuit diagram of the multipurpose serial timing code decoder of an embodiment of the present utility model;
Fig. 2 is according to the circuit diagram of the multipurpose serial timing code decoder of another embodiment of the present utility model;
Fig. 3 is according to the circuit diagram of the multipurpose serial timing code decoder of another embodiment of the present utility model;
Fig. 4 is according to the reset circuit schematic diagram of the multipurpose serial timing code decoder of an embodiment of the present utility model;
Fig. 5 is according to the edge sense circuit schematic diagram of the decoding circuit of the multipurpose serial timing code decoder of an embodiment of the present utility model;
Fig. 6 is according to the execution oscillogram of the B code coding of the multipurpose serial timing code decoder of an embodiment of the present utility model;
Fig. 7 carries out oscillogram according to the decoding of the B code of the multipurpose serial timing code decoder of an embodiment of the present utility model; Fig. 8 is according to the basic code element schematic diagram of DC B code of the multipurpose serial timing code decoder of an embodiment of the present utility model; And
Fig. 9 is according to the basic code element schematic diagram of alternating-current B code of the multipurpose serial timing code decoder of an embodiment of the present utility model.
Embodiment
Fig. 1 is according to the circuit diagram of the multipurpose serial timing code decoder of an embodiment of the present utility model.This multipurpose serial timing code decoder comprises outside input modulation circuit 10, governor circuit 20 and signal output apparatus 30, wherein governor circuit 20 is connected with outside input modulation circuit 10, to receive the serial timing code of outside input, and be converted to multichannel distinct interface to time signal; Outside input modulation circuit 10, is connected with governor circuit 20, with output multi-channel distinct interface to time signal.
Fig. 2 is according to the circuit diagram of the multipurpose serial timing code decoder of another embodiment of the present utility model.In this embodiment, outside input modulation circuit 10 comprises: A/D convertor circuit 11, to receive the interchange serial time code signal of outside input; DC isolation circuit 12, to receive the direct current serial time code signal of outside input.Governor circuit 20 comprises: field programmable gate array chip 21, series arrangement device 23, SDRAM chip 22(SDRAM), constant-temperature crystal oscillator 24, reset circuit 25, wherein, field programmable gate array chip 21 is main control chip, is connected respectively with series arrangement device 23, SDRAM chip 22, constant-temperature crystal oscillator 24 and reset circuit 25.Signal output apparatus 30 comprises: high speed photo coupling 31, RS232 transceiving chip 32, RS485 transceiving chip 33, ethernet transceiver 34, wherein, high speed photo coupling 31 export pulse and direct current form to time signal; RS232 transceiving chip 32 export RS232 form to time signal; RS485 transceiving chip 33 export RS485 form to time signal; Ethernet transceiver 34 output network message forms to time signal.
Particularly, A/D convertor circuit 11 in outside input modulation circuit 10 is for modulating alternating-current B code, the high amplitude minimum of AC code is 0.25V, and low amplitude value minimum is 0.042V, and getting analog-to-digital figure place is 8, reference voltage is 5V, resolution is 20mV, the conversion of corresponding B code lowest amplitude, high-amplitude correspondence 12, correspondence 2 by a narrow margin, therefore high low amplitude is easy to just can judge.DC isolation circuit 12 in outside input modulation circuit 10, for the modulation to DC B code, carries out light-coupled isolation and corresponding level modulation, used RS485 chip modulate out as the B coded signal of differential signal, and Transistor-Transistor Logic level is converted to by optocoupler.
Fig. 3 is according to the circuit diagram of the multipurpose serial timing code decoder of another embodiment of the present utility model.Alternatively, field programmable gate array chip 21 comprises: DC B code decoder module 211, alternating-current B code decoder module 212, time bias module 213, phase-locked loop module 214, pulse generating module 215, SOC (system on a chip) 216.Can preferably adopt EPCS16 model chip at above series arrangement device 23, in this case, field programmable gate array chip 21 is as main control chip, EPSC16 chip is configured field programmable gate array chip 21, field programmable gate array completes after hardware initialization, start to receive outside B coded signal, process laggard line output.Decoding packets of information is out containing two kinds: pulse per second (PPS) and current B code code element.Wherein time bias module 213 is exported in pulse per second (PPS), and time bias module 213 produces the pulse per second (PPS) of corresponding precision according to the required precision of time bias; Current B code code element is exported to SOC (system on a chip) 216 modules by universal input and output signal pin, carried out next step B code decodes by SOC (system on a chip) 216 modules, obtain the current information such as Hour Minute Second and date, subsequently these information are processed, finally by the information of processing with serial ports time message and network time message form send.In two kinds of decoder modules, designed watchdog circuit, in the time of B code interface no signal, decoder module carries out Self-resetting, and simultaneously field programmable gate array chip 21 enters from punctual state, continue the certain precision of output to time signal.Phase-locked loop module 214 carries out frequency multiplication to constant-temperature crystal oscillator 24, exports to respectively decoding circuit, SOC (system on a chip) 216 and time bias module 213.SOC (system on a chip) 216, has comprised SOC (system on a chip) processor module, SDRAM control module, EPCS16 control module, universal input and output module, universal asynchronous reception/dispensing device (UART) module, ethernet module and spare module.
In the parts except field programmable gate array in governor circuit 20, SDRAM, for SOC (system on a chip) 216 service data buffer memorys; Constant-temperature crystal oscillator 24, moves required high-precision frequency source for generation of field programmable gate array, and reset RESET circuit, for carrying out reset operation to decoder.
Signal output apparatus 30 comprises: high speed photo coupling 31, RS232 transceiving chip 32, RS485 transceiving chip 33, ethernet transceiver 34, wherein, high speed photo coupling 31 export pulse and direct current form to time signal, for carrying out electrical isolation with Electric Power Automation Equipment; RS232 transceiving chip 32 export RS232 form to time signal, to send RS232 level serial ports time message; RS485 transceiving chip 33 export RS485 form to time signal, to receive and to send RS485 differential mode level; Ethernet transceiver 34 output network message forms to time signal, can preferably adopt DP83640 chip.
The time delay of B code channel transmission is very large, the often requirement of overtime synchronous error, if propagation delay time is not revised, the time synchronization error of terminal will be overproof.Therefore need in decoding circuit, add delay compensating circuit.Delay compensation value is the time delay measured value of channel used.The 1pps signal that B code obtains after decoding is exported punctual 1pps signal for frequency divider synchronously after compensation of delay.
Serial ports time message is sent by UART bus, by after optocoupler, exports respectively by RS232 and RS485 chip.Network time, message passed through after DP83640 chip, and output after isolating by network transformer, is connected by two kinds of buses of RMII and MIIM between DP83640 and field programmable gate array.In signal output apparatus 30, also comprise the communication interface of other agreements, as extendible module, meet other interface requirements of site of deployment.
Fig. 4 is according to reset circuit 25 schematic diagrames of the multipurpose serial timing code decoder of an embodiment of the present utility model.After powering on or resetting, RESET circuit carries out reset operation to decoder, in order to improve the reset reliability of whole system, avoids occurring metastable state, on the basis of outside RESET signal, a kind of asynchronous reset, the synchronous double buffering RESET circuit discharging are designed.
Fig. 5 is according to the edge sense circuit schematic diagram of the decoding circuit of the multipurpose serial timing code decoder of an embodiment of the present utility model.DC B code decoder module 211 is decoded to DC B code and the alternating-current B code of outside input respectively with alternating-current B code decoder module 212, and edge sense circuit is differentiated rising edge and trailing edge the output of B code in real time, has ensured the accuracy of decoding.
Fig. 6 is according to the execution oscillogram of the B code coding of the multipurpose serial timing code decoder of an embodiment of the present utility model.Wherein the first row waveform is clock signal; The second row waveform is reset signal, and whole system is started working during for high level at it; The third line waveform is pps pulse per second signal; Fourth line waveform is B code code signal, can find out, the rising edge of its first code element aligns with the rising edge of pulse per second (PPS), illustrates that coding is correct.
Fig. 7 carries out oscillogram according to the decoding of the B code of the multipurpose serial timing code decoder of an embodiment of the present utility model.Wherein the first row waveform is clock signal; The second row waveform is reset signal, and whole system is started working during for high level at it; The third line waveform is the simulate signal of input B code; Fourth line waveform is clearing pps pulse per second signals out, can find out, the rising edge of pulse per second (PPS) aligns with first code element rising edge of B code, illustrates that decoding is correct.
Fig. 8 is according to the basic code element schematic diagram of DC B code of the multipurpose serial timing code decoder of an embodiment of the present utility model, and Fig. 9 is according to the basic code element schematic diagram of alternating-current B code of the multipurpose serial timing code decoder of an embodiment of the present utility model.Wherein the length of every kind of code element is 10ms, and wherein pulsewidth 2ms's is code element " 0 "; That pulsewidth 8ms is code element " P "; Pulsewidth 5ms's is code element " 1 ".B code decoding circuit and other circuit that the utility model is designed all design according to its feature.
In above embodiment, in multipurpose serial timing code decoder, each parts, module directly complete by hardware circuit, utilize the complete technical purpose that realizes of circuit structure, solve the require high problem of following intelligent grid to time synchronized.
Claims (5)
1. a multipurpose serial timing code decoder, is characterized in that, comprises outside input modulation circuit, governor circuit and signal output apparatus, wherein,
Described governor circuit is connected with described outside input modulation circuit, to receive the outside serial timing code of inputting, and be converted to multichannel distinct interface to time signal;
Described outside input modulation circuit, is connected with described governor circuit, with export described multichannel distinct interface to time signal.
2. serial timing code decoder according to claim 1, it is characterized in that, described governor circuit comprises: field programmable gate array chip, series arrangement device, SDRAM chip, constant-temperature crystal oscillator, reset circuit, wherein, described field programmable gate array chip is main control chip, is connected respectively with described series arrangement device, described SDRAM chip, described constant-temperature crystal oscillator and described reset circuit.
3. serial timing code decoder according to claim 2, it is characterized in that, described field programmable gate array chip comprises: DC B code decoder module, alternating-current B code decoder module, time bias module, phase-locked loop module, pulse generating module, SOC (system on a chip).
4. serial timing code decoder according to claim 1, is characterized in that, described signal output apparatus comprises: high speed photo coupling, RS232 transceiving chip, RS485 transceiving chip, ethernet transceiver, wherein,
The output pulse of described high speed photo coupling and direct current form to time signal;
Described RS232 transceiving chip output RS232 form to time signal;
Described RS485 transceiving chip output RS485 form to time signal;
Described ethernet transceiver output network message form to time signal.
5. serial timing code decoder according to claim 1, is characterized in that, described outside input modulation circuit comprises:
A/D convertor circuit, to receive the interchange serial time code signal of outside input;
DC isolation circuit, to receive the direct current serial time code signal of outside input.
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| CN201420066611.1U CN203708224U (en) | 2014-02-13 | 2014-02-13 | Multipurpose serial time code decoder |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110095973A (en) * | 2019-05-24 | 2019-08-06 | 国网四川省电力公司电力科学研究院 | Time synchronization tester based on multi signal general-purpose interface |
| CN112305904A (en) * | 2019-07-26 | 2021-02-02 | 中国石油天然气集团有限公司 | Clock calibration method for acquisition equipment and acquisition equipment |
| CN113791533A (en) * | 2021-07-02 | 2021-12-14 | 中国船舶重工集团公司第七0七研究所 | IRIG-B direct-current code decoding and time synchronization automatic switching method based on FPGA |
-
2014
- 2014-02-13 CN CN201420066611.1U patent/CN203708224U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110095973A (en) * | 2019-05-24 | 2019-08-06 | 国网四川省电力公司电力科学研究院 | Time synchronization tester based on multi signal general-purpose interface |
| CN112305904A (en) * | 2019-07-26 | 2021-02-02 | 中国石油天然气集团有限公司 | Clock calibration method for acquisition equipment and acquisition equipment |
| CN113791533A (en) * | 2021-07-02 | 2021-12-14 | 中国船舶重工集团公司第七0七研究所 | IRIG-B direct-current code decoding and time synchronization automatic switching method based on FPGA |
| CN113791533B (en) * | 2021-07-02 | 2023-06-20 | 中国船舶重工集团公司第七0七研究所 | IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA |
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