CN203455835U

CN203455835U - Bus triggering backplate applied to PXI (PCI extension for instrumentation) test platform

Info

Publication number: CN203455835U
Application number: CN201320529549.0U
Authority: CN
Inventors: 唐海军; 叶圣江; 杨健; 吴真
Original assignee: CHENGDU M & S TECHNOLOGY Co Ltd
Current assignee: CHENGDU M & S TECHNOLOGY Co Ltd
Priority date: 2013-08-28
Filing date: 2013-08-28
Publication date: 2014-02-26
Anticipated expiration: 2023-08-28

Abstract

The utility model discloses a bus triggering backplate applied to a PXI (PCI extension for instrumentation) test platform. The bus triggering backplate comprises a backplate provided with a time reference circuit, a PXI triggering slot and multiple PXI expansion slots; the multiple PXI expansion slots are bridged by chips on the backplate; 8 bus triggering ports and 1 time triggering port are arranged on the backplate; the 8 bus triggering ports are respectively connected with the triggering input end of the PXI triggering slot and the triggering input ends of the PXI expansion slots by the backplate; the time triggering port is respectively connected with the input ends of the multiple PXI expansion slots by the time reference circuit. The bus triggering backplate applied to the PXI test platform adopts the PXI bus as the communicating bus between a computer and other collecting board cards, so the reliability of a digital test module is greatly improved, cooperative work of multiple modules is realized, and the multi-channel data simulation and measurement are realized.

Description

A kind of bus-type that is applied to PXI test platform triggers backboard

Technical field

The utility model belongs to observation and control technology field, and the bus-type that relates in particular to a kind of PXI of being applied to test platform triggers backboard.

Background technology

PXI(PCI Extension for Instrumentation) bus is that American National instrument company (National Instrumentation, NI) is in the modular instrument bus specification of issue in 1997.Its core is that all superior functions of high-speed PCI bus and Compact PCI modular structure are rolled into one.PXI bus has 32/64 bit data transmittability and respectively up to the data rate of 132MB/s and 264MB/s, in addition, also supports the expansion of PCI-PCI bridge road and plug and play.

After carrying out mainly using in data acquisition data that different detectors are collected to transform by data with after slot on backboard is connected by analog input card in prior art, be transferred to computing machine, owing to being subject to the restriction of high speed fabric swatch technique and data processing scale, can not realize at present on data transmission to analog input card that different detectors are received and processing, common practice is to be divided into several analog input cards to process, and then uploads to respectively computing machine and carry out last data output processing.Therefore, require the analog input card of design to be easy to expansion, it is strict synchronous that the sampling clock of each board is wanted, but CPU adopts pci interface to occupy an individual slots position, takies system bandwidth, causes system speed slow to such an extent as to unstable, system complexity is high, and cost of manufacture is high.

Utility model content

The purpose of this utility model provides a kind of simple in structure with regard to being in order to address the above problem, the bus-type that is applied to PXI test platform that data transmission time delay is few triggers backboard.

The utility model is achieved through the following technical solutions above-mentioned purpose:

The utility model comprises backboard, on described backboard, be provided with reference time circuit, PXI triggering groove and a plurality of PXI expansion slot, a plurality of described PXI expansion slot are by the chip bridge joint on described backboard, on described backboard, be provided with eight buses and trigger port and time triggering port, eight described buses trigger port and are connected with the described PXI triggering triggering input end of groove and the triggering input end of a plurality of described PXI expansion slot respectively by described backboard, and the described time triggers port and is connected with the input end of a plurality of described PXI expansion slot respectively by described reference time circuit.

Particularly, the frequency of described reference clock circuit is 10MHz.

Further, described PXI expansion slot is 11.

The beneficial effects of the utility model are:

The utility model adopts PXI bus as the bus with computing machine and other board communications, greatly improved the reliability of testing digital module, can multimode collaborative work, realize multichannel data simulation and measurement, expanded more high-performance I/O groove position, can enjoy the advantage of PXI structure, avoid again changing the great number expenditure that whole system is brought simultaneously.

Accompanying drawing explanation

Fig. 1 is structural representation of the present utility model;

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail:

As shown in Figure 1, the utility model comprises backboard, on backboard, be provided with reference time circuit, PXI triggering groove and a plurality of PXI expansion slot, a plurality of PXI expansion slot are by the chip bridge joint on backboard, on backboard, be provided with eight buses and trigger port and time triggering port, eight buses trigger port and are connected with the PXI triggering triggering input end of groove and the triggering input end of a plurality of PXI expansion slot respectively by backboard, and the time triggers port and is connected with the input end of a plurality of PXI expansion slot respectively by reference to time circuit.

As shown in Figure 1, in the present embodiment, backboard is provided with 12 groove positions altogether, and the 1st groove position be as power supply and the mechanical interface of bus system controller, and 2nd～11 groove positions are as power supply and the mechanical interface of peripheral module.

TTL bus triggers by 8 bus PXI_TRIG[0:7] form, trigger line high flexible, can use differently, such as trigger can be used for the synchronous operation between a plurality of different PXI peripheral modules, also can utilize the module timing order that accurately other module operations are carried out in control system, trigger pip can be delivered to another module from a module, allows that the asynchronous external event to monitoring or controlling produces accurate timing response.Trigger routing module and input according to outside, set up the pair relationhip of trigger source and triggering terminal; When selecting the pair relationhip of one group of current use, according to selected pair relationhip, trigger source is exported to triggering terminal.

PXI Trigger Bus is comprised of eight signals, and each expansion slot all connects so far bus, and sees through PXI Trigger Bus, also can reach synchronous function.But because the characteristic of its bus, so the crooked degree of accuracy of clock pulse only requires to being less than 10ns, by a technical grade bridging chip bridge joint, realizes the accurate transmission of 12 groove position high speed signals on PXI backboard.

These are only preferred embodiment of the present utility model, not in order to limit the utility model, all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., all should be included in protection domain of the present utility model.

Claims

1. a bus-type that is applied to PXI test platform triggers backboard, comprise backboard, on described backboard, be provided with PXI and trigger groove and a plurality of PXI expansion slot, a plurality of described PXI expansion slot are by the chip bridge joint on described backboard, it is characterized in that: also comprise reference time circuit, on described backboard, be provided with eight buses and trigger port and time triggering port, eight described buses trigger port and are connected with the described PXI triggering triggering input end of groove and the triggering input end of a plurality of described PXI expansion slot respectively by described backboard, the described time triggers port and is connected with the input end of a plurality of described PXI expansion slot respectively by described reference time circuit.

2. a kind of bus-type that is applied to PXI test platform according to claim 1 triggers backboard, it is characterized in that: the frequency of described reference clock circuit is 10MHz.

3. a kind of bus-type that is applied to PXI test platform according to claim 1 triggers backboard, it is characterized in that: described PXI expansion slot is 11.