CN113572474B - Multichannel high-speed AD sampling device - Google Patents

Abstract

The multichannel high-speed AD sampling device disclosed by the invention has the advantages of good universality and high sampling rate. The invention is realized by the following technical scheme: the FPGA circuit is provided with a phase-locked loop PLL and a high-speed AD chip, an external connector is input or an on-board crystal oscillator is used for outputting an AD sampling clock to be provided to the high-speed AD chip as a sampling clock after being phase-locked by the phase-locked loop PLL; the analog intermediate frequency signals are sent to an ADC channel through at least 4 SMP sockets, and are sent to an analog-digital AD acquisition circuit for sampling after passing through an analog matching circuit, synchronous SYNC signals are input according to a clock synchronization circuit, the sampling signals are sent to transformers which are connected in series on the ADC channels for sampling, the signals are converted into 4 groups of low-voltage differential signals LVDS which support synchronization among chips, high-speed LVDS parallel data and double-edge alignment clock signals after sampling are output to an FMC connector which is connected in a point-to-point or point-to-multipoint mode, and sampling of the 4 paths of analog signals is completed.

Description

Multichannel high-speed AD sampling device

Technical Field

The invention relates to the fields of measurement and control, communication, software radio and the like, in particular to a high-speed AD sampling device.

Background

In a measurement and control and communication system, the rate, synchronization and analog input bandwidth of AD sampling have great influence on system design and performance, and particularly in the field of software radio, high-speed AD acquisition plays a very critical role. The existing acquisition card interfaces are mostly PCI bus, ISA bus, 1394 bus, etc., which not only has high cost, but also is difficult to realize. And the existing FMC acquisition board card has low acquisition rate, the whole delay of the system is higher after being connected to fpga, the programmable sampling clock and the external reference clock on the board cannot be flexibly supported, and the working state cannot be detected. The acquisition devices used in the fields of measurement and control, communication and the like at present have the defects of large volume, low sampling speed, long design period, incapability of multiplexing, difficulty in expansion, insufficient reliability verification, incapability of ensuring synchronization among a plurality of acquisition devices, no independent onboard clock and the like.

With the development of radar technology and modern broadband communication technology, high-speed ADCs play an important role in the design of digital broadband receivers

The system has wider and wider requirements on analog input bandwidth, and at the same time, the performance requirements on the ADC are higher and higher, and the conventional acquisition system cannot meet the requirement of high data rate. Previous designs have been difficult to meet current requirements. The application range of intermediate frequency sampling and radio frequency sampling in radar signal processing is continuously expanded, and the sampling technology also presents new characteristics, such as high integration level, multiple channels, high resolution and the like. Most of the existing radar signal acquisition circuits are three channels and four channels, and the maximum number is eight channels; the sampling rates are different from KHz to GHz; the resolution is mainly 8 bits, 10 bits, 14 bits and 16 bits. Generally, the higher the sampling rate, the lower the resolution. At the present stage, a multi-channel AD product which simultaneously meets the requirements of high sampling rate and high resolution is not provided in China. In this case, there are fewer and fewer products in this aspect that are applied to the field of radar signal processing. Taking a certain radar signal processing as an example, the high-speed AD sampling module is specifically characterized in that (1) 12 channels of intermediate frequency signals are input; (2) sample rate can be configured by software, up to 250Mbps; (3) the resolution reaches 14 bits; and (4) the volume is small, and the integration level is high. The related index requirements of the project on the AD sampling circuit are that the number of channels is 12, the sampling rate is not lower than 160MHz, the resolution is not lower than 14 bits, the number of significant bits is not lower than 10 bits, the SFDR is not lower than 80dBc, and the available circuit board area is about 10cm to 11cm according to the requirements on FPGA processing resources and storage capacity. Under the condition, the scheme of adopting the traditional single-channel AD chip occupies a large area of the circuit board, has a complex conditioning circuit and high cost and cannot meet the requirement. The clock circuit is designed in a high-speed data acquisition system, and the clock is one of the most critical parts. The accuracy of its signal has a direct influence on the detection performance of the whole AD. Theoretically, the AD chip ADs4449 with 14 bits can provide an SNR of 86dB, and in practical applications, jitter of the sampling clock inevitably causes a reduction in the SNR. If the sampling clock generates jitter, the performance of the whole circuit is deteriorated, particularly parameters such as signal-to-noise ratio and effective digit are deteriorated. In the process of continuously improving the digital technical level, the radar echo signals are mostly collected in the intermediate frequency when being sampled, and when the frequency of the analog input signals is improved, the requirement corresponding to clock jitter is also improved. Therefore, clock quality is critical in ADC design. Clock jitter will reduce the signal-to-noise ratio during design and cause the inter-channel amplitude coherence to be broken. When a signal-to-noise ratio of 72dB and a spur-free dynamic range of 83dB is required, an anti-aliasing filter (AAF) must be used to improve spur performance and lower signal harmonics. But this does not solve the input drive and channel flatness problem. In the design process, the two aspects of power supply are realized respectively, an isolation filter circuit needs to be arranged between the two aspects of power supply, and the same voltage of different power supplies needs to be isolated well. When the circuit is designed, the digital ground and the analog ground are not distinguished, the blind separation of the ground layer only increases the inductance of a return path, the defect brought by the blind separation of the ground layer is larger than the benefit, and the key is that the circuit is reasonably divided, so that the ground layer does not need to be separated. A good circuit partitioning requires the use of capacitors with different capacities to reduce the impedance generated by the power transfer system (PDS), and the selected capacitors should have the appropriate capacitance and type to reduce the PDS impedance, but not all capacitors are equal, even though the same supplier is different in terms of design and process. If the capacitance values or types of the capacitors are selected incorrectly, an inductive loop may be formed, thereby negatively affecting the PDS. Due to the use of inconsistent capacitors or improper capacitor assembly, resonance may occur.

Disclosure of Invention

The invention aims to solve the problems and provides a multi-channel high-speed AD sampling device which supports multi-channel multi-mode synchronous sampling, has good universality and high sampling speed.

The above object of the present invention can be achieved by a multichannel high-speed AD sampling apparatus comprising: AD acquisition circuit, the FPGA circuit, the clock synchronization circuit and the temperature detection circuit of board-mounted connect in parallel at monitoring circuit, power supply circuit between clock synchronization circuit and FMC connector, its characterized in that: the FPGA circuit is provided with a phase-locked loop PLL and a high-speed AD chip, an external connector is input or an on-board crystal oscillator, and an AD sampling clock is output to the high-speed AD chip as a sampling clock after phase locking of the phase-locked loop PLL; analog intermediate frequency signals are sent to 4 paths of 10-bit ADC channels through at least any 4 paths of SMP sockets and are sent to 4 groups of analog-digital AD acquisition circuits for sampling after passing through an analog matching circuit, the 4 groups of analog-digital AD acquisition circuits input synchronous SYNC signals according to a clock synchronization circuit and send sampling signals to transformers connected in series on respective ADC channels for sampling to convert the signals into 4 groups of low-voltage differential signals LVDS supporting synchronization among chips, high-speed LVDS parallel data and clock signals with aligned double edges of four paths of ABCD are sampled, and a group of LVDS data or 4 groups of LVDS clocks are output to an FMC connector connected in a point-to-point or point-to-multipoint mode to finish sampling of analog signals of the paths A, B, C and D4.

Compared with the prior art, the invention has the beneficial effects that:

multimode synchronous sampling is supported. The invention adopts the following steps: the analog-digital converter comprises an AD acquisition circuit, an FPGA circuit, a clock synchronization circuit, a temperature detection circuit, a multi-channel high-speed AD sampling device consisting of a monitoring circuit and a power supply circuit which are connected in parallel between the clock synchronization circuit and an FMC connector, and a SYNC circuit is designed to support synchronous sampling of a plurality of sampling devices, a working mode can be configured according to requirements, 4-channel 10-bit ADC channel analog-to-digital AD high-speed conversion can be provided, and 3 sampling modes of 5GSPS (single channel)/2.5 GSPS (double channel)/1.25 GSPS (four channels) sampling rate are supported. And the device has an independent on-board clock, while supporting an external reference clock and an external sampling clock input. Can meet the application of analog-digital conversion at the front end of the common broadband signal processing.

The universality and the testability are good. The invention adopts an FPGA circuit to configure a phase-locked loop PLL and a high-speed AD chip, inputs an external connector into or uses an on-board crystal oscillator, and outputs an AD sampling clock after phase locking by the phase-locked loop PLL to be provided for the high-speed AD chip as a sampling clock; the analog intermediate frequency signals are sent to 4 paths of 10-bit ADC channels through at least 4 SMP sockets, and are sent to 4 groups of analog-to-digital AD acquisition circuits for sampling after passing through an analog matching circuit, and the 4 groups of analog-to-digital AD acquisition circuits input synchronous SYNC signals according to a clock synchronization circuit, send the sampling signals to transformers connected in series on respective ADC channels for sampling, and convert the sampling signals into 4 groups of low-voltage differential signals LVDS supporting synchronization among chips. The interface definition and the structure size of the daughter card adopting the FMC standard conform to the VITA57.1 standard, the daughter card can be used on various signal processing carrier boards meeting the VITA57.1 standard, a programmable sampling clock or an external reference clock on the board can be flexibly selected, and the daughter card is good in universality.

The sampling rate is high. The sampling rate is high, after sampling, high-speed LVDS parallel data of four paths of the ABCD and clock signals with aligned double edges are output to a point-to-point or point-to-multipoint connected FMC connector through a group of LVDS data or 4 groups of LVDS clocks, sampling of analog signals of paths A, B, C and D4 is completed, and the sampling rate is high. The temperature detection circuit and the voltage detection circuit are realized through testing, the working state of the monitoring device can be conveniently monitored, the fault detection rate is improved, and the testability is improved.

Drawings

The invention is further described with reference to the following figures and examples.

FIG. 1 is a schematic diagram of the multi-channel high-speed AD sampling device of the present invention;

FIG. 2 is a schematic diagram of the AD acquisition circuit of FIG. 1;

FIG. 3 is a schematic diagram of the synchronization principle of the ADC of FIG. 2;

FIG. 4 is a schematic diagram of the on-board FPGA circuit of FIG. 1;

fig. 5 is a schematic diagram of the power supply circuit of fig. 1.

The technical scheme of the invention is further described in detail in the following with reference to the attached drawings.

Detailed Description

See fig. 1. In an embodiment described below, a multi-channel high-speed AD sampling apparatus includes: AD acquisition circuit, the FPGA circuit, the clock synchronization circuit and the temperature detection circuit of board-mounted connect in parallel at monitoring circuit, power supply circuit between clock synchronization circuit and FMC connector, its characterized in that: the FPGA circuit is provided with a phase-locked loop PLL and a high-speed AD chip, an external connector is input or an on-board crystal oscillator is used for outputting an AD sampling clock to be provided to the high-speed AD chip as a sampling clock after being phase-locked by the phase-locked loop PLL; the analog intermediate frequency signal is sent to 4 paths of 10-bit ADC channels through at least any 4 paths of SMP sockets, and is sent to 4 groups of analog-digital AD acquisition circuits for sampling after passing through an analog matching circuit, the 4 groups of analog-digital AD acquisition circuits input synchronous SYNC signals according to a clock synchronization circuit, the sampling signals are sent to transformers which are connected in series on respective ADC channels for sampling, the signals are converted into 4 groups of low-voltage differential signals LVDS which support synchronization among chips, high-speed LVDS parallel data and clock signals with aligned double edges of four paths of ABCD are obtained after sampling, one group of LVDS data or 4 groups of LVDS clocks are output to an FMC connector which is connected point-to-point or point-to-multipoint, and sampling of analog signals of A, B, C and D4 paths is completed.

And the monitoring circuit with an I2C interface is connected to the FMC connector, and is used for monitoring and carrying out communication according to the configuration of the AD circuit, the clock circuit and the synchronous circuit and the working state of the device. The SYNC signal can be input by the front panel connector or by the FMC connector for synchronization between multiple acquisition devices. The power supply circuit is used for supplying power to the chip in the board.

The PLL circuit provides clock input for the AD, the high-speed AD circuit provides 4 paths of 10-bit ADC channels, 4/2/1 sampling modes are supported, 4 groups of LVDS data are output, the FPGA circuit is used for configuring the PLL and the high-speed AD chip, the SYNC circuit is used for synchronizing a plurality of ADC sampling devices, the temperature detection circuit is used for detecting the internal temperature of the AD, and the voltage detection circuit is used for detecting the internal voltage of the AD sampling devices.

EV10AQ190 from E2V company is used as AD.

See fig. 2. The AD acquisition circuit includes: the method comprises the steps of providing 4 paths of 10-bit ADC channels, supporting an analog multiplexer of 4/2/1 sampling modes, sending any one path of an ABCD four-path analog intermediate-frequency signal into an analog matching circuit through an SMP socket, sending the signal to an AD (analog-to-digital converter) for sampling after passing through the analog matching circuit, generating 4 paths of 1.25GHz sampling clocks with 90-degree difference by the transformer through the analog multiplexer, outputting 4 groups of 1.25GHz sampling clocks to support ADC1, ADC2, ADC3 and ADC4 four-path AD to simultaneously sample, generating 2.5GHz clock signals by an external input or a PLL (phase locked loop) on a board for supplying the AD by the sampling clocks, outputting 1 bit 1.25Gbps high-speed LVDS parallel data and 625MHz double-edge aligned clock signals in four paths of the ABCD after sampling, and outputting 4 xDataLVDS data of a 4 xLVDS sampling clock synchronized among AD chips and 4 xDataLVDS data to an FMC connector.

In a 4-channel 1.25Gsps working mode, four paths of analog intermediate frequency signals are sent into an analog matching circuit by an ABCD four-path SMP socket, one path of analog intermediate frequency signals AB is sent into any path of SMP socket, the other path of analog intermediate frequency signals are sent into the analog matching circuit by any path SMP socket and then are sent into an ADC for sampling, a sampling clock is externally input or is generated by a PLL (phase locked loop) on a board to generate 2.5GHz clock signals to be supplied to the AD, 2 paths of 1.25GHz sampling clocks with 180-degree phase difference are generated inside the AD to simultaneously sample four paths of AD, and after sampling, the four paths of ABCD have respectively 10bit 1.25Gbps high-speed LVDS parallel data and 625MHz double-edge aligned clock signals to be output to an FMC connector.

In an optional embodiment, the PLL chip of the PLL may be a PLL with an output frequency of 300MHz to 4.8GHz, an internal VCO, an input reference frequency of 0.5MHz to 350MHz, an input frequency range of an external VCO of 15MHz to 9ghz, and a model TRF3765 for the company ti.

See fig. 3. The clock synchronization circuit has an independent onboard clock, simultaneously supports an external reference clock and an external sampling clock to input an ADC synchronization signal SYNC, the clock synchronization circuit clock can be provided by an external input or an onboard crystal oscillator, and the onboard temperature compensation crystal oscillator can select STXO25DE40MASIV. The REF pin, selected by the rf switch, connected to TRF3765 is multiplied by the internal VCO to generate the ADC sampling clock. In addition, the AD sampling clock can also be directly connected to the EXTVCO pin of the TRF3765 through an external input and then sent to the AD after direct connection. Clock logic selection is achieved by controlling the two radio frequency switches ADG 918.

See fig. 4. A synchronous SYNC signal used for an ADC is input into an IC chip NB6N14SMNG input clock through an SMP interface, is converted into LVDS level, is sent to LVDS input with safety failure and LVDS output in one path, is sent to a multiplexer with the model number of MAX9176 in one path, is sent to an FMC connector in the other path, can also be input through the FMC connector, and is sent to the ADC for synchronization after an input source is selected through one LVDS MUX chip MAX 9176.

See fig. 5. The temperature detection pin of the ADC chip is connected to a temperature monitoring chip TMP423, the FPGA reads a built-in register of the temperature monitoring chip TMP423 through an I2C interface, the internal temperature of the ADC is obtained through temperature conversion, and the voltage detection function can be realized by acquiring the output voltage of 3.3V, 1.8V and 1.2V of DCDC through the XADC in the FPGA. The FPGA can be XC7A50T-2CPG236I of Xilinx company, and the temperature monitoring chip can be TMP423 of TI company.

The power circuit consists of 2 LTMs 4622 and 1 MAX8556, the DC +12V power input is used for converting 1 LTM4622 into 3.6V from 12V and then converting MAX8556 into D3.3V for the internal circuit of the daughter card, and the +3.3V is converted into D1.8V and D1.0V for AD and FPGA by another LTM 4622. The VADJ is directly used by 1 bank IO of the FPGA.

While the foregoing is directed to the preferred embodiment for implementing a high speed AD acquisition device, it is to be understood that the invention is not limited to the form disclosed herein, but is not intended to be exhaustive of other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. A multi-channel high-speed AD sampling apparatus comprising: AD acquisition circuit, the FPGA circuit, the clock synchronization circuit and the temperature detection circuit of board year, parallelly connected monitoring circuit, the power supply circuit between clock synchronization circuit and FMC connector, its characterized in that: the FPGA circuit is provided with a phase-locked loop PLL and a high-speed AD chip, an external connector is input or an on-board crystal oscillator, and an AD sampling clock is output to the high-speed AD chip as a sampling clock after phase locking of the phase-locked loop PLL; the analog intermediate frequency signal is sent to 4 paths of 10-bit ADC channels through at least any 4 paths of SMP sockets, and is sent to 4 groups of analog-digital AD acquisition circuits for sampling after passing through an analog matching circuit, the 4 groups of analog-digital AD acquisition circuits input synchronous SYNC signals according to a clock synchronization circuit, the sampling signals are sent to transformers connected in series on respective ADC channels for sampling, and are converted into 4 groups of low-voltage differential signals LVDS supporting synchronization among chips, high-speed LVDS parallel data and clock signals with aligned double edges of four paths of ABCD are sampled, and a group of LVDS data or 4 groups of LVDS clocks are output to an FMC connector in point-to-point or point-to-multipoint connection, so that the sampling of analog signals of A, B, C and D4 paths is completed.

2.A multi-channel high-speed AD sampling apparatus as claimed in claim 1, wherein: and the monitoring circuit is provided with an I2C interface connected to the FMC connector, and is used for monitoring and carrying out communication by the carrier board according to the configuration of the AD circuit, the clock circuit and the synchronous circuit and the working state of the device.

3. A multi-channel high-speed AD sampling apparatus as claimed in claim 1, wherein: the SYNC signal is input by the front panel connector or by the FMC connector, or with synchronization between multiple acquisition devices.

4. The multi-channel high-speed AD sampling apparatus of claim 1, wherein: the AD acquisition circuit includes: the method comprises the steps that 4 paths of 10-bit ADC channels are provided, an analog multiplexer of 4/2/1 sampling modes is supported, any one path of an ABCD four-path analog intermediate-frequency signal is sent into an analog matching circuit through an SMP socket and then sent to an AD sampling transformer through the analog matching circuit, the transformer generates 4 paths of 1.25GHz sampling clocks with 90-degree difference through the analog multiplexer and outputs 4 groups of sampling clocks which support the four paths of ADCs 1, ADC2, ADC3 and ADC4 to carry out sampling simultaneously.

5. The multi-channel high-speed AD sampling apparatus of claim 4, wherein: the sampling clock is supplied to the AD by 2.5GHz clock signals generated by external input or a PLL (phase locked loop) on a board, after sampling, four paths of the ABCD respectively have high-speed LVDS parallel data of 10bit 1.25Gbps and clock signals with 625MHz double-edge alignment, and LVDS data of a 4 Xclk sampling clock and 4 XdataLVDS data which are synchronous among AD chips are output to the FMC connector.

6. The multi-channel high-speed AD sampling apparatus of claim 5, wherein: in a 4-channel 1.25Gsps working mode, four paths of analog intermediate frequency signals are sent into an analog matching circuit through an ABCD four-path SMP socket, one path of analog intermediate frequency signals AB are sent into any path of SMP socket, the other path of analog intermediate frequency signals are sent into the analog matching circuit through any path SMP socket and then are sent into an ADC for sampling, a sampling clock is externally input or is generated by a PLL (phase locked loop) on a board to generate 2.5GHz clock signals for AD, 2 paths of 1.25GHz sampling clocks with 180-degree phase difference are generated inside the AD to simultaneously sample the four paths of AD, and after sampling, the four paths of ABCD respectively have 10bit 1.25Gbps high-speed LVDS parallel data and 625MHz double-edge aligned clock signals and are output to an FMC connector.

7. The multi-channel high-speed AD sampling apparatus of claim 1, wherein: the PLL chip selects a PLL with the output frequency of 300 MHz-4.8 GHz, an internally integrated VCO, the input reference frequency of 0.5 MHz-350 MHz, the input frequency range of an external VCO of 15 MHz-9 GHz and the type TRF 3765.

8. The multi-channel high-speed AD sampling apparatus of claim 1, wherein: the PLL chip selects a phase-locked loop with the output frequency of 300 MHz-4.8 GHz, an internally integrated VCO, the input reference frequency of 0.5 MHz-350 MHz, the input frequency range of an external VCO of 15 MHz-9GHz and the model of TI company TRF 3765.

9. A multi-channel high-speed AD sampling apparatus as claimed in claim 1, wherein: the power supply circuit consists of 2 LTMs 4622 and 1 MAX8556, the DC +12V power supply input is adopted, 12V is firstly converted into 3.6V by using 1 LTM4622 and then is converted into D3.3V by using MAX8556 for use by daughter card internal circuits, the +3.3V is converted into D1.8V and D1.0V for use by AD and FPGA by using another LTM4622, and the VADJ is directly used for 1 bank IO of the FPGA.

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