YU46402B - SIGNATURE REGISTER CIRCUIT FOR TRONIVO LOGIC - Google Patents

SIGNATURE REGISTER CIRCUIT FOR TRONIVO LOGIC

Info

Publication number
YU46402B
YU46402B YU74286A YU74286A YU46402B YU 46402 B YU46402 B YU 46402B YU 74286 A YU74286 A YU 74286A YU 74286 A YU74286 A YU 74286A YU 46402 B YU46402 B YU 46402B
Authority
YU
Yugoslavia
Prior art keywords
circuit
input
signature register
register
signature
Prior art date
Application number
YU74286A
Other languages
Serbo-Croatian (sh)
Other versions
YU74286A (en
Inventor
A. Dobrin
F. Novak
Original Assignee
Institut "Jožef Stefan"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institut "Jožef Stefan" filed Critical Institut "Jožef Stefan"
Priority to YU74286A priority Critical patent/YU46402B/en
Publication of YU74286A publication Critical patent/YU74286A/en
Publication of YU46402B publication Critical patent/YU46402B/en

Links

Landscapes

  • Logic Circuits (AREA)

Abstract

VEZJE SIGNATURNEGA REGISTRA ZA TRONIVOJSKO LOGIKO, označeno s tem, da je linija vhodnega krmilnega signala RESET povezana z vhodom 24 vezja za krmiljenje signaturnih registrov (3), in da je linija vhodnega krmilnega signala STOP povezana z vhodom 23 vezja za krmiljenje signaturnih registrov (3), in da je linija vhodnega krmilnega signala START povezana z vhodom 22 vezja za krmiljenje signaturnih registrov (3), in da je linija vhodnega krmilnega signala URA povezana z vhodom 21 vezja za krmiljenje signaturnih registrov (3) in vhodom 16 vezja za izračun podatka osnovnega signaturnega registra (2) in vhodom 9 vezja za izračun podatka dodatnega signaturnega registra 1 in da je linija vhodnega podatkovnega signala DATA povezana z vhodom 15 vezja za izračun podatka osnovnega signaturnega registra (2) in z vhodom 8 vezja za izračun podatka dodatnega signaturnega registra (1), in da je vhod 20 vezja za krmiljenje signaturnih registrov (3) povezan z izhodom 12 vezja za izračun podatka dodatnega signaturnega registra (1), in da je izhod 25 vezja za krmiljenje signaturnih registrov (3) povezan z vhodom 18 vezja za izračun podatka osnovnega signaturnega registra (2), in da je izhod 26 vezja za krmiljenje signaturnih registrov (3) povezan z vhodom 34 vezja osnovnega signaturnega registra (5) in vhodom 30 vezja dodatnega signaturnega registra (4), in da je izhod vezja za krmiljenje signaturnih registrov (3) povezan z vhodom 40 vezja za prikaz rezultatov (6) in z vhodom 36 vezja osnovnega signaturnega registra (5) in z vhodom 31 vezja dodatnega signaturnega registra (4) in z vhodom 14 vezja za izračun podatka osnovnega signaturnega registra (23) in z vhodom 10 vezja za izračun podatka dodatnega signaturnega registra (1), in da je izhod 28 vezja za krmiljenje signaturnih registrov (3) povezan z vhodom 41 vezja za prikaz rezultatov (6), in da je izhod 19 vezja za izračun podatka osnovnega signaturnega registra (2) povezan z vhodom 35 vezja osnovnega signaturnega registra (5), in da je izhod 11 vezja za izračun podatka dodatnega signaturnega registra (1) povezan z vhodom 29 vezja dodatnega signaturnega registra (4), in da je izhod 32 vezja dodatnega signaturnega registra (4) povezan z vhodom 7 vezja za izračun podatka dodatnega signaturnega registra (1), in da je izhod 33 vezja dodatnega signaturnega registra (4) povezan z vhodom 13 vezja za izračun podatka osnovnega signaturnega registra (2), in da je paralelni izhod 37 vezja osnovnega signaturnega registra (5) povezan preko paralelnega vodila s paralelnim vhodom 39 vezja za prikaz rezultatov (6), in da je izhod 38 vezja osnovnega signaturnega registra (5) povezan z vhodom 17 vezja za izračun podatka osnovnega signaturnega registra (2).SIGNATURE REGISTER CIRCUIT FOR THREE-LEVEL LOGIC, characterized in that the line of the input control signal RESET is connected to the input 24 of the circuit for controlling the signature registers (3), and that the line of the input control signal STOP is connected to the input 23 of the control circuit ), and that the line of the input control signal START is connected to the input 22 of the circuit for controlling the signature registers (3), and that the line of the input control signal URA is connected to the input 21 of the circuit for controlling the signature registers (3) and the input 16 of the circuit of the basic signature register (2) and the input of the circuit for calculating the data of the additional signature register 1 and that the line of the input data signal DATA is connected to the input 15 of the circuit for calculating the data of the basic signature register (2) and the input 8 of the circuit for calculating the data of the additional signature register (1), and that the input 20 of the signature register control circuit (3) is connected to the output 12 of the data calculation circuit dod signature output register (1), and that the output 25 of the signature register control circuit (3) is connected to the input 18 of the basic signature register data circuit (2), and that the output 26 of the signature register control circuit (3) is connected to the input of the basic signature register circuit (5) and the input 30 of the secondary signature register circuit (4), and that the output of the control register control circuit (3) is connected to the input 40 of the result display circuit (6) and to the input 36 of the basic signature circuit of the register (5) and with the input 31 of the circuit of the additional signature register (4) and with the input 14 of the circuit for calculating the data of the basic signature register (23) and with the input 10 of the circuit for calculating the data of the additional signature register (1), and that the output 28 for controlling the signature registers (3) connected to the input 41 of the circuit for displaying the results (6), and that the output 19 of the circuit for calculating the data of the basic signature register (2) is connected to the input 35 of the circuit of the basic signature register ( 5), and that the output of the additional signature register data circuit (1) is connected to the input 29 of the additional signature register circuit (4), and that the output 32 of the additional signature register circuit (4) is connected to the data calculation circuit input 7 of the additional signature register (1), and that the output 33 of the circuit of the additional signature register (4) is connected to the input 13 of the circuit for calculating the data of the basic signature register (2), and that the parallel output 37 of the circuit of the basic signature register (5) is connected via a parallel a bus with a parallel input 39 of the circuit for displaying the results (6), and that the output 38 of the circuit of the basic signature register (5) is connected to the input 17 of the circuit for calculating the data of the basic signature register (2).

YU74286A 1986-05-08 1986-05-08 SIGNATURE REGISTER CIRCUIT FOR TRONIVO LOGIC YU46402B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
YU74286A YU46402B (en) 1986-05-08 1986-05-08 SIGNATURE REGISTER CIRCUIT FOR TRONIVO LOGIC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
YU74286A YU46402B (en) 1986-05-08 1986-05-08 SIGNATURE REGISTER CIRCUIT FOR TRONIVO LOGIC

Publications (2)

Publication Number Publication Date
YU74286A YU74286A (en) 1988-08-31
YU46402B true YU46402B (en) 1993-10-20

Family

ID=25551233

Family Applications (1)

Application Number Title Priority Date Filing Date
YU74286A YU46402B (en) 1986-05-08 1986-05-08 SIGNATURE REGISTER CIRCUIT FOR TRONIVO LOGIC

Country Status (1)

Country Link
YU (1) YU46402B (en)

Also Published As

Publication number Publication date
YU74286A (en) 1988-08-31

Similar Documents

Publication Publication Date Title
SG49193A1 (en) Protection systems for critical memory information
YU46402B (en) SIGNATURE REGISTER CIRCUIT FOR TRONIVO LOGIC
JPS54139443A (en) Information processor
JPS5570997A (en) Error bit check system for read only memory
JPS641050A (en) Computer system provided with byte order conversion mechanism
JPS5691534A (en) Array logic circuit
SU1383492A1 (en) Subtracting decade counter for seven-segment indicators
JPS55116122A (en) Information processor
SU487385A1 (en) Digital comparator
JPS5467337A (en) Video memory unit
JPS6476486A (en) Memory ic
EP0264740A3 (en) Time partitioned bus arrangement
JPS57114939A (en) Buffer register control system
JPS57174722A (en) Data processor
JPS5572261A (en) Logic unit
FR2445672A1 (en) Identification word generator - receives serial data from bus connecting CPU and peripherals and initiates reply signal
JPS6459551A (en) Input circuit
SU970366A1 (en) Microprogram control device
SU440795A1 (en) Reversible binary counter
JPS5729160A (en) Information processor
JPS5659335A (en) Bus check system
JPS55152491A (en) Electronic timepiece
JPS6450138A (en) Arithmetic unit
JPS5469043A (en) Output contol system for lsi
JPS5422137A (en) Bus line chekcing device