WO2025112978A1 - 显示面板、驱动方法、驱动电路及显示装置 - Google Patents

显示面板、驱动方法、驱动电路及显示装置 Download PDF

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Publication number
WO2025112978A1
WO2025112978A1 PCT/CN2024/126156 CN2024126156W WO2025112978A1 WO 2025112978 A1 WO2025112978 A1 WO 2025112978A1 CN 2024126156 W CN2024126156 W CN 2024126156W WO 2025112978 A1 WO2025112978 A1 WO 2025112978A1
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Prior art keywords
unit
node
transistor
reset
turned
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PCT/CN2024/126156
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English (en)
French (fr)
Inventor
青海刚
宋江
郑海
王本莲
胡明
邱海军
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US19/498,095 priority Critical patent/US20260237349A1/en
Publication of WO2025112978A1 publication Critical patent/WO2025112978A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a driving method, a driving circuit and a display device.
  • AMOLED Active-matrix organic light-emitting diode
  • OLED Organic Light-Emitting Diode
  • Pixel circuits made by combining LTPS (Low Temperature Poly-Silicon) and oxide technology are widely used because of the low leakage of oxide transistors and the high maturity of LTPS technology.
  • oxide transistors are sensitive to temperature and voltage fluctuations, they are prone to characteristic deviation, which causes changes in the driving current in the pixel circuit, causing uneven brightness of the display screen and reducing the display effect of the display screen.
  • the display panel, driving method, driving circuit and display device provided by the present disclosure can improve the phenomenon of uneven brightness of the display screen caused by the characteristic deviation of the oxide transistor in the pixel circuit.
  • a display panel including a plurality of pixel circuits, wherein the pixel circuits include:
  • a first light emitting control unit the first light emitting control unit is electrically connected between a first node and a second node, and the first node is used to receive a first driving signal;
  • a second light emitting control unit wherein the second light emitting control unit is electrically connected between the third node and the fourth node;
  • the driving unit is electrically connected to the second node, the third node and the fifth node respectively;
  • a first data writing unit the first data writing unit is electrically connected between the third node and the sixth node, and the first data writing unit includes an oxide transistor;
  • isolation unit being electrically connected between the fifth node and the sixth node, the isolation unit comprising a polysilicon transistor;
  • a light emitting unit one end of which is electrically connected to the fourth node, and the other end of which is used to receive a second driving signal
  • the oxide transistor of the first data writing unit is in a saturation region during the first time period.
  • the oxide transistor of the first data writing unit is of N-type
  • the polysilicon transistor of the isolation unit is of P type
  • the rising edge of the gate signal of the oxide transistor is located before the falling edge of the gate signal of the polysilicon transistor;
  • the falling edge of the gate signal of the oxide transistor is located at the After the rising edge.
  • the pixel circuit further includes:
  • first reset unit being electrically connected to the sixth node, and the first reset unit being configured to transmit a first reset signal to the sixth node;
  • the isolation unit and the first reset unit are turned on simultaneously, and before the third time period, the first reset unit is turned on before the isolation unit.
  • the pixel circuit further includes:
  • the second data writing unit being electrically connected to the second node, and the second data writing unit being used to transmit a data signal to the second node;
  • the switching state of the second data writing unit is the same as that of the isolation unit.
  • the pixel circuit further includes:
  • the second reset unit being electrically connected to the fourth node, and the second reset unit being used to transmit a second reset signal to the fourth node;
  • a capacitor one end of the capacitor is electrically connected to the first node, and the other end of the capacitor is electrically connected to the fifth node.
  • the first reset unit includes an oxide transistor; and/or,
  • the second data writing unit includes a polysilicon transistor; and/or,
  • the second reset unit includes a polysilicon transistor; and/or,
  • the third reset unit includes a polysilicon transistor; and/or,
  • the first light emitting control unit comprises a polysilicon transistor; and/or,
  • the second light emitting control unit comprises a polysilicon transistor; and/or,
  • the driving unit includes a polysilicon transistor.
  • the driving unit when the driving unit is a P-type polysilicon transistor, the potential of the third reset signal is greater than the potential of the first driving signal;
  • the potential of the third reset signal is lower than the potential of the first driving signal.
  • the first light emitting control unit is turned on for at least one row scanning duration before the second light emitting control unit is turned on.
  • a second aspect of the embodiments of the present disclosure provides a method for driving a display panel, which is applied to the display panel as described in any one of the first aspects, and the driving method includes:
  • the first light emitting control unit and the second light emitting control unit are controlled to be turned on, so that the light emitting unit emits light under the action of the first driving signal and the second driving signal.
  • the driving method when the pixel circuit includes a first reset unit, and there is a second time period in which the first data writing unit and the first reset unit are turned on at the same time, the driving method further includes:
  • the second time period lasts for at least one row scanning duration.
  • the driving method further includes:
  • the isolation unit is controlled to be turned on for at least one of the third time periods to transmit the first reset signal to the fifth node, wherein the third time period lasts for at least one row scanning duration.
  • the driving method further comprises:
  • the first light emitting control unit Before controlling the first light emitting control unit and the second light emitting control unit to be turned on, the first light emitting control unit is controlled to be turned on earlier than the second light emitting control unit for at least one row scanning duration.
  • a third aspect of the embodiments of the present disclosure provides a driving circuit for use in the method for driving a display panel as described in any one of the second aspects.
  • a fourth aspect of the embodiments of the present disclosure provides a display device, comprising a display panel as described in any one of the first aspect; and/or a driving circuit as described in the third aspect.
  • the display panel provided by the present disclosure includes a plurality of pixel circuits, and the pixel circuit includes: a first light-emitting control unit, the first light-emitting control unit is electrically connected between the first node and the second node, and the first node is used to receive a first driving signal; a second light-emitting control unit, the second light-emitting control unit is electrically connected between the third node and the fourth node; a driving unit, the driving unit is electrically connected to the second node, the third node and the fifth node respectively; a first data writing unit, the first data writing unit is electrically connected between the third node and the sixth node, and the first data writing unit includes an oxide transistor; an isolation unit, the isolation unit is electrically connected between the fifth node and the sixth node, and the isolation unit includes a polysilicon transistor light-emitting unit, one end of the light-emitting unit is electrically connected to the fourth node, and the other end is used to receive a second driving signal;
  • the present disclosure sets an isolation unit between the first data writing unit and the driving unit, and the isolation unit includes a polysilicon transistor.
  • the polysilicon transistor in the isolation unit is first turned off, and then the oxide transistor of the first data writing unit is turned off.
  • Polysilicon transistors especially low-temperature polysilicon transistors, have a mature manufacturing process. Their semiconductor layers are made of polysilicon. Polysilicon is more stable, has stronger electron binding force, and is not easily affected by the external environment. Oxide transistors are less stable. After long-term operation, the device temperature rises, the electron activity intensifies, and the electron binding force is further reduced.
  • the present invention first turns off the polysilicon transistor in the isolation unit, and uses the strong stability of the polysilicon transistor to turn off the gate-source voltage at the gate-source voltage.
  • the threshold voltage is not easily offset, so that at the moment of cut-off, the potential difference of the gate node of the write driving transistor is greatly reduced.
  • the driving current generated by the driving transistor has a high degree of restoration, and the brightness of the light-emitting unit will not become darker or brighter. It can improve the technical problem of uneven brightness of the display screen and improve the uniformity of the display picture.
  • the driving method, driving circuit and display device provided by the present disclosure also have the above technical effects.
  • FIG1 is a schematic structural block diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG2 is a diagram showing a relationship between an oxide transistor threshold voltage and OLED brightness provided by an embodiment of the present disclosure
  • FIG3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG4 is a schematic signal timing diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG5 is a schematic structural block diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • FIG6 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • FIG7 is a schematic signal timing diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • FIG8 is a schematic structural block diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • FIG9 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • FIG10 is a schematic signal timing diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • FIG11 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • FIG12 is a schematic signal timing diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • FIG13 is a schematic flow chart of a driving method provided in an embodiment of the present disclosure.
  • FIG14 is a schematic structural block diagram of a driving circuit connection relationship provided in an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure.
  • FIG1, FIG3, FIG5, FIG6, FIG8, FIG9, FIG11, FIG14 and FIG15 The corresponding relationship between the names and numbers of the components in FIG1, FIG3, FIG5, FIG6, FIG8, FIG9, FIG11, FIG14 and FIG15 is as follows: 1000 display device; 100 pixel circuit, 200 light emitting array driving circuit, 300 first gate array driving circuit, 400 A second gate array driving circuit; 101 a first light-emitting control unit, 102 a second light-emitting control unit, 103 a driving unit, 104 a first data writing unit, 105 an isolation unit, 106 a light-emitting unit, 107 a first reset unit, 108 a second data writing unit, 109 a second reset unit, 110 a third reset unit; N1 a first node, N2 a second node, N3 a third node, N4 a fourth node, N5 a fifth node, N6 a sixth node, T5 a polysilicon transistor, T6 an oxide transistor, VDD a first driving signal, VSS
  • the present invention does not include some steps or units, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
  • the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.
  • FIG. 1 is a schematic structural block diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit 100 includes: a first light-emitting control unit 101, the first light-emitting control unit 101 is electrically connected between a first node N1 and a second node N2, and the first node N1 is used to receive a first driving signal VDD; a second light-emitting control unit, the second light-emitting control unit is electrically connected between a third node N3 and a fourth node N4; a driving unit 103, the driving unit 103 is electrically connected to the second node N2, the third node N3 and the fifth node N5 respectively; a first data A write unit 104, wherein the first data write unit 104 is electrically connected between the third node N3 and the sixth node N6, and the first data write unit 104 includes
  • the first light-emitting control unit 101 is used to control the conduction and cutoff between the first node N1 and the second node N2.
  • the first drive signal VDD is written into the second node N2.
  • the second light-emitting control unit 102 is used to control the conduction and cutoff between the third node N3 and the fourth node N4.
  • the drive unit 103 is used to control the conduction and cutoff between the second node N2 and the third node N3 under the action of the fifth node N5.
  • the light-emitting unit 106 emits light under the action of the first drive signal VDD and the second drive signal VSS.
  • the isolation unit 105 is used to control the conduction and cutoff between the fifth node N5 and the sixth node N6, and the first data writing unit 104 is used to control the conduction and cutoff between the third node N3 and the sixth node N6.
  • the first time period represents the time period in which the isolation unit 105 and the first data writing unit 104 are simultaneously turned on.
  • the potential of the third node N3 can be written into the fifth node N5 through the first data writing unit 104 and the isolation unit 105.
  • the isolation unit 105 is turned off first, and then the first data writing unit 104 is turned off.
  • the isolation unit 105 includes a polysilicon transistor, and the first data writing unit 104 includes an oxide transistor.
  • oxide transistors such as IGZO (Indium Gallium Zinc Oxide) have the characteristic of low leakage.
  • an oxide transistor can be used as an isolation switch for writing a control signal into the gate of the driving transistor, which can prevent the charge of the gate capacitor from being lost when the driving transistor is in the on state, thereby ensuring the on-state stability of the driving transistor.
  • the threshold voltage characteristics of oxide transistors are prone to shift, especially when the voltage fluctuates. In this way, at the cut-off moment of the oxide transistor, the threshold voltage will produce a positive shift or a reverse shift.
  • FIG2 is a relationship diagram between the threshold voltage of an oxide transistor and the brightness of an OLED provided in an embodiment of the present disclosure, wherein the horizontal coordinate ⁇ V_th in FIG2 represents the fluctuation of the threshold voltage of the oxide transistor, in V (volts), and the vertical coordinate ⁇ Ioled/Ioled represents the percentage change in the brightness of the OLED.
  • the oxide transistor threshold voltage increases, resulting in an increase in the amount of charge written into the gate of the driver transistor, a decrease in the absolute value of the gate-source voltage of the driver transistor, a decrease in the drive current generated by the driver transistor, and a decrease in the brightness of the OLED compared to normal conditions; conversely, when the oxide transistor is reversely offset, the oxide transistor threshold voltage decreases, resulting in a decrease in the brightness of the OLED compared to normal conditions.
  • the amount of charge written into the gate of the driver transistor decreases, the absolute value of the gate-source voltage of the driver transistor increases, the driving current generated by the driver transistor increases, and the brightness of the OLED is brighter than normal. Therefore, based on the offset of the threshold voltage of the oxide transistor, the display screen will produce uneven horizontal stripes.
  • an isolation unit 105 is provided between the first data writing unit 104 and the driving unit 103.
  • the isolation unit 105 includes a polysilicon transistor. After the first time period, that is, when it is necessary to stop writing charge to the fifth node N5, the polysilicon transistor in the isolation unit 105 is first turned off, and then the oxide transistor of the first data writing unit 104 is turned off.
  • the polysilicon transistor especially the low-temperature polysilicon transistor, has a mature manufacturing process, and its semiconductor layer is made of polysilicon.
  • the polysilicon has stronger stability, stronger binding force on electrons, and is not easily affected by the external environment.
  • the oxide transistor has weaker stability.
  • the embodiment of the present disclosure first turns off the polysilicon transistor in the isolation unit 105, and utilizes the strong stability of the polysilicon transistor.
  • the threshold voltage is not easily offset, so that at the moment of cutoff, the potential difference of the gate node of the write drive transistor is greatly reduced, and then the driving current generated by the drive transistor has a high degree of restoration, and the brightness of the light-emitting unit will not have the problem of dimming or brightening, which can improve the technical problem of uneven brightness of the display screen and improve the uniformity of the display screen.
  • the first light-emitting control unit 101, the second light-emitting control unit 102, the isolation unit 105 and the first data writing unit 104 can be controlled by the driver chip or processor in the display panel, and the specific control method is not limited.
  • FIG3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the first light-emitting control unit 101 includes a transistor T1
  • the second light-emitting control unit 102 includes a transistor T2
  • the driving unit 103 includes a transistor T3
  • the first data writing unit 104 includes an oxide transistor T4
  • the isolation unit 105 includes a polysilicon transistor T5
  • the light-emitting unit 106 includes an OLED.
  • the oxide transistor T4 is exemplified by an N-type transistor
  • the transistor T1, the transistor T2, the transistor T3, and the polysilicon transistor T5 are exemplified by P-type transistors.
  • FIG4 is a schematic signal timing diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the transistor T1 and the transistor T2 are turned off, under the high potential of the first gate driving signal Ngate, the oxide transistor T4 is turned on, and under the low potential of the second gate driving signal Pgate, the polysilicon transistor T5 is turned on.
  • the first time period in which the oxide transistor T4 and the polysilicon transistor T5 are turned on at the same time is the T period in FIG4.
  • the potential of the third node N3 is written into the fifth node N5 through the sixth node N6, and the potential of the fifth node N5 is stored in the gate capacitance of the transistor T3.
  • the polysilicon transistor T5 is turned off, and after the polysilicon transistor T5 is turned off, the oxide transistor T4 can be turned off.
  • the cut-off interval time between the polysilicon transistor T5 and the oxide transistor T4 can be determined according to actual conditions, so as to ensure that the oxide transistor T4 is cut off after the polysilicon transistor T5 is completely cut off.
  • the oxide transistor of the first data writing unit 104 in FIGS. 1 and 3 is in a saturation region during the first time period.
  • the oxide transistor in the first data writing unit 104 when the oxide transistor in the first data writing unit 104 is in the saturation region, the source-drain current is little affected by the gate potential. Therefore, when writing data to the fifth node N5 in the first time period, the first gate driving signal Ngate can be prevented from fluctuating to cause the written data to change, thereby improving the gate potential of the driving transistor in the writing driving unit 103.
  • the accuracy of the capacitor charge, and thus the accuracy of the driving current can accurately restore the brightness of the OLED.
  • the oxide transistor of the first data writing unit 104 is of N type; the polysilicon transistor of the isolation unit 105 is of P type; wherein, before the first time period, the rising edge of the gate signal of the oxide transistor is before the falling edge of the gate signal of the polysilicon transistor; after the first time period, the falling edge of the gate signal of the oxide transistor is after the rising edge of the polysilicon transistor.
  • the oxide transistor T4 of the first data unit starts to conduct at the rising edge of the first gate driving signal Ngate
  • the polysilicon transistor T5 of the isolation unit 105 starts to conduct at the falling edge of the second gate driving signal Pagate, and the rising edge of the first gate driving signal Ngate precedes the falling edge of the second gate driving signal Pagate; after the time T, the polysilicon transistor T5 of the isolation unit 105 is turned off at the rising edge of the second gate driving signal Pagate, and the oxide transistor T4 of the first data unit 104 is turned off at the falling edge of the first gate driving signal Ngate, and the falling edge of the first gate driving signal Ngate is later than the rising edge of the second gate driving signal Pagate.
  • Figure 5 is a schematic structural block diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit 100 also includes: a first reset unit 107, the first reset unit 107 is electrically connected to the sixth node N6, and the first reset unit 107 is used to transmit a first reset signal to the sixth node N6; wherein, the first data write unit 104 and the first reset unit 107 have a second time period in which they are turned on at the same time, and before the second time period, the first reset unit 107 is turned on before the first data write unit 104, and after the second time period, the first reset unit 107 is turned off before the first data write unit 104, and the second time period does not overlap with the first time period.
  • the first reset unit 107 is used to transmit the first reset signal Vinit1 to the sixth node N6 under the action of the control signal.
  • the first reset signal Vinit1 is written into the third node N3. Since the first data writing unit 104 and the isolation unit 105 are turned on at the same time in the first time period to write the potential of the third node N3 into the fifth node N5, the first reset unit 107 cannot write the first reset signal Vinit1 into the third node N3 in the first time period, and the first time period cannot overlap with the second time period.
  • Figure 6 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • the first reset unit 107 includes a transistor T6, the gate of the transistor T6 receives the first reset drive signal Reset_n, one of the source or drain is electrically connected to the sixth node N6, and the other receives the first reset signal Vinit1.
  • Figure 7 is a schematic signal timing diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the first reset drive signal Reset_n is at a high potential
  • the transistor T6 is turned on
  • the first gate drive signal Ngate is at a high potential
  • the oxide transistor T4 is turned on
  • the first reset signal Vinit1 is written to the third node N3 to set the third node N3.
  • the transistor T6 is turned on to precharge the sixth node N6, so as to adjust the gate-source voltage of the oxide transistor T4 to remove the influence of the residual charge in the last frame of display picture.
  • the transistor T6 is turned off first, so as to prevent the first reset signal Vinit1 from being continuously written into the sixth node N6, so as to affect the setting of the fifth node N5 in the subsequent stage.
  • the third node N3 is connected to the transistor T3 in the driving unit 103, setting the third node N3 can adjust the threshold voltage of the transistor T3 and eliminate the offset of the threshold voltage of the transistor T3 in the previous frame display. Thereby improving the accuracy of the driving current, and then being able to accurately restore the brightness of the OLED.
  • the isolation unit 105 and the first reset unit 107 are turned on simultaneously for at least one third time period, and before the third time period, the first reset unit 107 is turned on before the isolation unit 105 .
  • the second gate drive signal Pgate in at least one low potential time period, such as the time period t2' in FIG7 , and in the time period t2' the first reset drive signal Reset_n is in a high potential, the polysilicon transistor T5 in the isolation unit 105 and the transistor T6 in the first reset unit 107 are turned on at the same time, and the first reset signal Vinit1 is written into the fifth node N5 through the polysilicon transistor T5.
  • setting the electric position of the fifth node N5 as the first reset signal Vinit1 can clear the residual charge of the fifth node N5, adjust the gate stress of the transistor T3 in the driving unit 103 to control the threshold voltage of the transistor T3, and eliminate the offset of the threshold voltage of the transistor T3 in the previous frame display image, thereby improving the accuracy of the driving current and the brightness restoration of the OLED, and then improving the afterimage problem of the display screen.
  • the transistor T6 is turned on before the polysilicon transistor T5 and sets the sixth node N6 first, thereby clearing the residual charge in the sixth node N6 and eliminating the influence on the polysilicon transistor T5, thereby improving the accuracy of writing the first reset signal Vinit1.
  • the pixel circuit 100 also includes: a second data writing unit 108, the second data writing unit 108 is electrically connected to the second node N2, and the second data writing unit 108 is used to transmit the data signal Data to the second node N2; wherein the second data writing unit 108 has the same switching state as the isolation unit 105.
  • the pixel circuit 100 further includes a second data writing unit 108, and the second data writing unit 108 is electrically connected to the second node N2.
  • the data signal Data is written into the fifth node N5 through the driving unit 103, the first data writing unit 104 and the isolation unit 105. Since the second data writing unit 108 and the isolation unit 105 are connected in series in the same branch, and the second data writing unit 108 and the isolation unit 105 are functionally bound, the switching states of the second data writing unit 108 and the isolation unit 105 can be the same, thereby simplifying the control logic of the display panel and reducing the driving power consumption.
  • the second data writing unit 108 is used to write the data signal Data to the fifth node N5, which can avoid the influence of the residual charge of the sixth node N6 on the conduction state of the isolation unit 105 and the first data writing unit 104, thereby improving the accuracy of the data signal Data writing.
  • the second data writing unit 108 includes a transistor T7, a gate of the transistor T7 receives a second gate drive signal Pgate, one of a source and a drain receives a data signal Data, and the other of the source and the drain is electrically connected to the second node N2.
  • the transistor T7 and the polysilicon transistor T5 are turned on at the same time under the low potential of the second gate drive signal Pgate, and the transistor T6 is turned on under the action of the first reset drive signal Reset_n, and the electric position of the sixth node N6 is set as the first reset signal Vinit1.
  • the sixth node N6 is firstly set to clear the residual charge therein and eliminate the influence of the previous frame display picture.
  • the transistor T7 and the polysilicon transistor T5 are turned on at the same time under the low potential of the second gate drive signal Pgate in the first time period, and the data signal Data passes through the transistor T3 and the transistor T5. T2 and transistor T9 write into the fifth node N5.
  • Figure 8 is a schematic structural block diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit 100 also includes: a second reset unit 109, the second reset unit 109 is electrically connected to the fourth node N4, and the second reset unit 109 is used to transmit the second reset signal Vinit2 to the fourth node N4; a third reset unit 110, the third reset unit 110 is electrically connected to the second node N2, and the third reset unit 110 is used to transmit the third reset signal Vinit3 to the second node N2; a capacitor Cst, one end of the capacitor Cst is electrically connected to the first node N1, and the other end is electrically connected to the fifth node N5.
  • the second reset unit 109 when the second reset unit 109 is turned on, the second reset signal Vinit2 is written into the fourth node N4.
  • the third reset unit 110 When the third reset unit 110 is turned on, the third reset signal Vinit3 is written into the second node N2.
  • Both ends of the capacitor Cst are electrically connected to the first node N1 and the fifth node N5, respectively, for storing the charge when the driving transistor T3 is turned on.
  • FIG9 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • the second reset unit 109 includes a transistor T8, the gate of the transistor T8 receives the second reset drive signal Reset_p, one of the source and the drain is connected to the fourth node N4, and the other of the source and the drain receives the second reset signal Vinit2.
  • the third reset unit 110 includes a transistor T9, the gate of the transistor T9 can also receive the second reset drive signal Reset_p, one of the source or the drain is connected to the second node N2, and the other receives the third reset signal Vinit3.
  • FIG10 is a schematic signal timing diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • the various working stages of the pixel circuit 100 provided in an embodiment of the present disclosure are described in combination with FIG9 and FIG10 :
  • the second reset drive signal Reset_p is at a low potential, transistors T8 and T9 are turned on, and the other transistors are in the off state.
  • the second reset signal Vinit2 and the third reset signal Vinit3 are written to the second node N2 and the fourth node N4 respectively to clear the residual charge after the previous frame is displayed.
  • the first reset drive signal Reset_n is at a high potential, and the transistor T6 is in a conducting state.
  • the polysilicon transistor T5 can be turned on once or multiple times under the action of the second gate drive signal Pgate, such as the t2' time period.
  • the first reset signal Vinit1 is written to the fifth node N5 through the transistor T6 and the polysilicon transistor T5 to clear the residual charge of the fifth node N5 before, and the gate stress of the transistor T3 in the driving unit 103 can be adjusted to clear the influence of its threshold voltage in the previous frame display. , so that the accuracy of the driving current is improved, the brightness restoration of the OLED is improved, and then the afterimage problem of the display screen can be improved. Setting multiple t2' time periods can improve the effect of adjusting the gate stress of the transistor T3.
  • the first reset drive signal Reset_n is at a high potential
  • the first gate drive signal Ngate is at a high potential
  • the second gate drive signal Pgate is at a high potential
  • the transistor T6 and the oxide transistor T4 are turned on
  • the transistor T5 is turned off
  • the first reset signal Vinit1 sets the third node N3 to clear the residual charge of the third node N3 and biases the threshold voltage of the transistor T3 to further clear the influence of the display picture on its threshold voltage.
  • the first gate drive signal Ngate is at a high potential
  • the first reset drive signal Reset_n is at a low potential
  • the oxide transistor T4 is turned on
  • the transistor T6 is turned off.
  • the second gate drive signal Pgate is at a low point in the t4' period, so that the polysilicon transistor T5 and the transistor T7 are turned on, and the transistor T3 is turned on under the action of the capacitor Cst.
  • the data signal Data is written into the capacitor Cst through the transistor T7, the transistor T3, the transistor T4 and the polysilicon transistor T5.
  • the second reset driving signal Reset_p is at a low potential, transistors T9 and T8 are turned on, and the third reset The signal Vinit3 is written into the second node N2 and the third node N3, and the second reset signal Vinit2 is written into the fourth node N4.
  • the third node N3 is set, so that after the transistor T2 is turned on, the charge can be quickly transferred to the capacitor of the OLED, thereby increasing the lighting rate of the OLED.
  • the second node N2 and the third node N3 are set, and the threshold voltage of the transistor T3 can be adjusted to improve the accuracy of the driving current.
  • the duration of the t5 stage can also be set according to actual conditions without specific limitation.
  • the light-emitting control signal EM is at a low level, transistors T1 and T2 are turned on, and transistor T3 is turned on by capacitor Cst.
  • V sg V DD -(V data -
  • V DD represents the potential of the first driving signal VDD
  • V data represents the potential of the data signal Data.
  • the display panel provided by the embodiment of the present disclosure completes the driving process of a frame of display picture.
  • the first reset unit 107 includes an oxide transistor; and/or, the second data write unit 108 includes a polysilicon transistor; and/or, the second reset unit 109 includes a polysilicon transistor; and/or, the third reset unit 110 includes a polysilicon transistor; and/or, the first light-emitting control unit 101 includes a polysilicon transistor; and/or the second light-emitting control unit 102 includes a polysilicon transistor; and/or, the driving unit 103 includes a polysilicon transistor.
  • transistors T1 , T2 , T3 , T7 , T8 , and T9 may be polysilicon transistors, and transistor T6 may be an oxide transistor.
  • the transistor T6 is connected in series to the branch of the polysilicon transistor T5 and the capacitor Cst, there is a risk of leakage. Therefore, the transistor T6 is set as an oxide transistor to reduce the risk of leakage.
  • the driving unit 103 when the driving unit 103 is a P-type polysilicon transistor, the potential of the third reset signal Vinit3 is greater than the potential of the first driving signal VDD; when the driving unit 103 is an N-type polysilicon transistor, the potential of the third reset signal Vinit3 is less than the potential of the first driving signal VDD.
  • the driving unit 103 when the driving unit 103 is a P-type polysilicon transistor, its threshold voltage is less than zero. Therefore, in order to ensure that the transistor T3 is turned on, the source or drain potential of the transistor T3 can be adjusted higher, that is, the potential of the third reset signal Vinit3 is greater than the potential of the first driving signal VDD, so that the transistor T3 is in a forward bias, so that the second node N2 and the third node N3 can be set.
  • the driving unit 103 when the driving unit 103 is an N-type polysilicon transistor, its threshold voltage is greater than zero. Therefore, in order to ensure that the transistor T3 is turned on, the source or drain potential of the transistor T3 can be lowered, that is, the potential of the third reset signal Vinit3 is less than the potential of the first driving signal VDD, so that the transistor T3 is in a forward bias, so that the second node N2 and the third node N3 can be set.
  • the first light emitting control unit 101 is turned on for at least one row scanning duration before the second light emitting control unit 102 .
  • Figure 11 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • the first light-emitting control unit 101 includes a transistor T1
  • the second light-emitting control unit 102 includes a transistor T2.
  • the gates of the transistor T1 and the transistor T2 receive a first light-emitting control signal EM1 and a second light-emitting control signal EM2, respectively.
  • FIG12 is a schematic signal timing diagram of another pixel circuit provided in an embodiment of the present disclosure.
  • the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are both at a high potential, and the transistors T1 and T2 are cut off. The rest are the same as those described above and will not be described again.
  • the first light emitting control signal EM1 is at a low potential
  • the transistor T1 is turned on
  • the second light emitting control signal EM2 is at a high potential
  • the transistor T2 is turned off
  • the second node N2 can be pre-charged.
  • both transistor T1 and transistor T2 are turned on, and the OLED emits light.
  • the t6 stage by precharging the second node N2, in the subsequent t7 stage, the precharged charge of the second node N2 can be quickly transferred to the capacitor of the OLED, thereby increasing the light emission rate of the OLED.
  • the t6 stage lasts for at least one row scanning time to ensure sufficient precharging.
  • the row scanning time can be understood as the time interval between display images of adjacent frames.
  • the pulse widths of the first light-emitting control signal EM1 and the second light-emitting control signal EM2 can be the same, and the timing difference is one row scanning duration. Therefore, when a driving circuit is used to provide the first light-emitting control signal EM1 and the second light-emitting control signal EM2, every two rows of pixel circuits 100 can share a driving circuit, thereby reducing the width of the non-display area of the display panel.
  • FIG. 13 is a schematic flow chart of a driving method provided by an embodiment of the present disclosure. As shown in FIG. 13 , the driving method includes:
  • the first data writing unit 104 and the isolation unit 105 are controlled to be turned on at the same time in the first time period, so that the write data can be transmitted to the driving unit 103 through the third node N3, the sixth node N6 and the fifth node.
  • the first data writing unit 104 includes an oxide transistor T4
  • the isolation unit 105 includes a polysilicon transistor T5
  • the driving unit 103 may include a transistor T3.
  • the first time period represents the time when the first data writing unit 104 and the isolation unit 105 are turned on at the same time.
  • the first data writing unit 104 and the isolation unit 105 are turned on and off at the same time, as shown in the t time period in FIG. 4 .
  • the first data writing unit 104 and the isolation unit 105 are not limited to being turned on and off at the same time.
  • the manufacturing process of polysilicon transistors is mature, and the semiconductor layer is made of polysilicon material, which has a strong binding force on electrons.
  • the characteristics of the transistor are relatively stable, and the threshold voltage is not easily affected by the external environment.
  • the semiconductor layer of the oxide transistor is made of oxide, and the characteristics are relatively unstable, and the threshold voltage is prone to shift, especially in the case of voltage fluctuations. Referring to Figures 3, 6, 9 and 11, after the first time period, the polysilicon transistor T5 in the isolation unit 105 is first disconnected, and then the oxide transistor T4 in the first data writing unit 104 is disconnected.
  • the current flowing into the fifth node N5 will not produce a sudden change due to the threshold voltage shift that may occur in the oxide transistor T4, resulting in an increase or decrease in the gate-source voltage of the driving transistor in the driving unit 103, so that the driving current generated by the driving unit 103 will not change, and the brightness of the OLED will not have the problem of dimming or brightening, thereby improving the technical problem of uneven brightness of the display screen.
  • the isolation unit 105 is turned off, the first light emitting control unit 101 and the second light emitting control unit 102 are controlled to be turned on, and the light emitting unit 106 emits light under the action of the first driving signal VDD and the second driving signal VSS.
  • the driving method provided in the embodiments of the present disclosure is also applicable to the embodiments of FIGS. 6 and 7 , the embodiments of FIGS. 9 and 10 , and the embodiments of FIGS. 11 and 12 .
  • the driving method further includes: before the second time period, controlling the first reset unit to be turned on first; after the second time period, controlling the first reset unit 107 to be turned off first; wherein the second time period lasts for at least one row scanning duration.
  • the transistor T6 Before the stage t3, the transistor T6 is turned on first, so that the transistor T6 can be preheated, so that the transistor T6 is more fully turned on during the stage t3, and is prepared for writing data into the fifth node N5.
  • the driving method further includes: before the second time period, controlling the first reset unit 107 to be turned on to transmit the first reset signal to the sixth node; after the first reset unit 107 is turned on, controlling the isolation unit 105 to be turned on for at least one third time period time period to transmit the first reset signal to the fifth node, wherein the third time period lasts for at least one row scanning time length.
  • the t2’ time period represents the third time period mentioned above.
  • the first reset drive signal Reset_n is at a high potential
  • the polysilicon transistor T5 in the isolation unit 105 and the transistor T6 in the first reset unit 107 are turned on at the same time
  • the first reset signal Vinit1 is written to the fifth node N5 through the polysilicon transistor T5, which can clear the residual charge before the fifth node N5, and adjust the gate stress of the transistor T3 in the driving unit 103 to clear the influence of the threshold voltage of the previous frame display, thereby improving the accuracy of the driving current, and then improving the afterimage problem of the display screen.
  • the driving method further includes: before controlling the first light emitting control unit 101 and the second light emitting control unit 102 to be turned on, controlling the first light emitting control unit 101 to be turned on earlier than the second light emitting control unit 102 for at least one row scanning duration.
  • the first light emitting control unit 101 may include a transistor T1
  • the second light emitting control unit 102 may include a transistor T2
  • the gate of the transistor T1 receives a first light emitting control signal EM1
  • the gate of the transistor T2 receives a second light emitting control signal EM2.
  • the transistor T2 and the transistor T1 are turned on at the same time, which corresponds to the stage t7 in FIG. 12 , and the OLED enters the light-emitting state in the stage t7.
  • the transistor T1 is turned on by the first light-emitting control signal EM1
  • the transistor T2 is turned off by the second light-emitting control signal EM2
  • the first driving signal VDD can be written into the second node N2 and the third node N3, and the transistor T3 in the driving unit 103 is pre-charged.
  • the t6 stage by precharging the second node N2, in the subsequent t7 stage, the precharged charge of the second node N2 can be quickly transferred to the capacitor of the OLED, thereby increasing the light emission rate of the OLED.
  • the t6 stage lasts for at least one row scanning time to ensure sufficient precharging.
  • the row scanning time can be understood as the time interval between display images of adjacent frames.
  • a third aspect of the embodiments of the present disclosure provides a driving circuit for executing a display panel driving method as described in any one of the second aspects.
  • FIG14 is a schematic structural block diagram of a driving circuit connection relationship provided by an embodiment of the present disclosure.
  • the driving circuit may include an EOA (Emission gate ON Array) circuit and a GOA (Gate ON Array) circuit.
  • the EOA circuit is a light emitting array driving circuit 200, which is used to provide a light emitting control signal EM to the pixel circuit 100.
  • the GOA1 circuit is a first gate array driving circuit 300, which is used to provide a first gate driving signal to the pixel circuit 100, such as Ngate in FIG3.
  • the GOA2 circuit is a second gate array driving circuit 400, which is used to provide a second gate driving signal to the pixel circuit 100, such as Pgate in FIG3.
  • the driving circuit may transmit the control signal to the pixel circuit 100 under the control of the driving chip in the display panel, or under other control modes, such as a remote controller, etc., which is not specifically limited.
  • FIG15 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. As shown in FIG15 , the above-mentioned display device 1000 includes a display panel as in any one of the first aspect; and/or a driving circuit as in the third aspect.
  • the display device 1000 provided in the embodiment of the present disclosure can be applied to vehicle-mounted displays, smart phones, computers,
  • the embodiments of the present disclosure are not specifically limited in scenarios such as medical displays, televisions, and smart wearable displays.
  • the display device 1000 provided in the embodiment of the present disclosure includes the display panel of any one of the first aspects, and therefore also has all the beneficial effects of the above-mentioned display panels, which will not be elaborated herein.

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Abstract

一种显示面板、驱动方法、驱动电路及显示装置（1000），其中，显示面板包括：多个像素电路（100），像素电路（100）包括：第一发光控制单元（101），电连接于第一节点（N1）和第二节点（N2）之间；第二发光控制单元（102），电连接于第三节点（N3）和第四节点（N4）之间；驱动单元（103），分别与第二节点（N2）、第三节点（N3）和第五节点（N5）电连接；第一数据写入单元（104），电连接于第三节点（N3）和第六节点（N6）之间，包括氧化物晶体管，隔离单元（105）电连接于第五节点（N5）和第六节点（N6）之间，包括多晶硅晶体管；发光单元（106）一端与第四节点（N4）电连接，另一端用于接收第二驱动信号（VSS）。

Description

显示面板、驱动方法、驱动电路及显示装置
相关申请的交叉引用
本申请要求于2023年11月30日提交的申请号为202311622386.5的中国专利申请的优先权，其全部内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、驱动方法、驱动电路及显示装置。
背景技术
随着半导体显示技术的日渐成熟，如AMOLED(Active-matrix organic light-emitting diode，有源矩阵有机发光二极管)和OLED(Organic Light-Emitting Diode，有机发光二极管)等，而针对现今多样化的市场需求，对显示屏幕的帧率、分辨率以及耐用性等方面都提出了更高的要求。
采用LTPS(Low Temperature Poly-Silicon，低温多晶硅)和氧化物技术相结合的工艺制作的像素电路，由于兼顾氧化物晶体管低漏电以及LTPS工艺成熟性高的特点从而得到广泛应用。但是，由于氧化物晶体管对温度、电压波动都比较敏感，因此容易发生特性偏移的问题，导致像素电路中的驱动电流发生变化，引起显示屏幕明暗不均，降低显示屏幕的显示效果。
发明内容
本公开提供的显示面板、驱动方法、驱动电路及显示装置，能够改善像素电路中氧化物晶体管的特性偏移导致的显示屏幕明暗不均的现象。
本公开实施例第一方面提供一种显示面板，包括多个像素电路，所述像素电路包括：
第一发光控制单元，所述第一发光控制单元电连接于第一节点和第二节点之间，所述第一节点用于接收第一驱动信号；
第二发光控制单元，所述第二发光控制单元电连接于第三节点和第四节点之间；
驱动单元，所述驱动单元分别与所述第二节点、所述第三节点和第五节点电连接；
第一数据写入单元，所述第一数据写入单元电连接于所述第三节点和第六节点之间，所述第一数据写入单元包括氧化物晶体管；
隔离单元，所述隔离单元电连接于所述第五节点和所述第六节点之间，所述隔离单元包括多晶硅晶体管；
发光单元，所述发光单元的一端与所述第四节点电连接，另一端用于接收第二驱动信号；
其中，所述第一数据写入单元和所述隔离单元存在同时导通的第一时间段，且在所述第一时间段之后所述隔离单元先于所述第一数据单元断开。
在一些实施方式中，所述第一数据写入单元的氧化物晶体管在所述第一时间段处于饱和区。
在一些实施方式中，所述第一数据写入单元的氧化物晶体管为N型；
所述隔离单元的多晶硅晶体管为P型；
其中，在所述第一时间段之前，所述氧化物晶体管的栅极信号的上升沿位于所述多晶硅晶体管的栅极信号的下降沿之前；
在所述第一时间段之后，所述氧化物晶体管的栅极信号的下降沿位于所述多晶硅晶体管的 上升沿之后。
在一些实施方式中，所述像素电路还包括：
第一复位单元，所述第一复位单元与所述第六节点电连接，所述第一复位单元用于向所述第六节点传输第一复位信号；
其中，所述第一数据写入单元和所述第一复位单元存在同时导通的第二时间段，且在所述第二时间段之前所述第一复位单元先于所述第一数据写入单元导通，在所述第二时间段之后所述第一复位单元先于所述第一数据写入单元关断，所述第二时间段与所述第一时间段无交叠。
在一些实施方式中，在所述第二时间段之前，所述隔离单元和所述第一复位单元存在同时导通的至少一个第三时间段，且在所述第三时间段之前，所述第一复位单元先于所述隔离单元导通。
在一些实施方式中，所述像素电路还包括：
第二数据写入单元，所述第二数据写入单元与所述第二节点电连接，所述第二数据写入单元用于向所述第二节点传输数据信号；
其中，所述第二数据写入单元与所述隔离单元的开关状态相同。
在一些实施方式中，所述像素电路还包括：
第二复位单元，所述第二复位单元与所述第四节点电连接，所述第二复位单元用于向所述第四节点传输第二复位信号；
第三复位单元，所述第三复位单元与所述第二节点电连接，所述第三复位单元用于向所述第二节点传输第三复位信号；
电容，所述电容的一端电连接于所述第一节点，另一端电连接于所述第五节点。
在一些实施方式中，所述第一复位单元包括氧化物晶体管；和/或，
所述第二数据写入单元包括多晶硅晶体管；和/或，
所述第二复位单元包括多晶硅晶体管；和/或，
所述第三复位单元包括多晶硅晶体管；和/或，
所述第一发光控制单元包括多晶硅晶体管；和/或，
所述第二发光控制单元包括多晶硅晶体管；和/或，
所述驱动单元包括多晶硅晶体管。
在一些实施方式中，在所述驱动单元为P型多晶硅晶体管的情况下，所述第三复位信号的电势大于所述第一驱动信号的电势；
在所述驱动单元为N型多晶硅晶体管的情况下，所述第三复位信号的电势小于所述第一驱动信号的电势。
在一些实施方式中，所述第一发光控制单元先于所述第二发光控制单元导通至少一个行扫描时长。
本公开实施例第二方面提供一种显示面板的驱动方法，应用于如第一方面中任一项所述的显示面板，所述驱动方法包括：
控制所述第一数据写入单元和所述隔离单元导通，以使所述第一数据写入单元和所述隔离单元存在同时导通的所述第一时间段，向所述驱动单元传输写入数据；
在所述第一时间段之后，控制先断开所述隔离单元，后断开所述第一数据写入单元；
控制所述第一发光控制单元和所述第二发光控制单元导通，以使所述发光单元在所述第一驱动信号和所述第二驱动信号的作用下发光。
在一些实施方式中，在所述像素电路包括第一复位单元，且所述第一数据写入单元和所述第一复位单元存在同时导通的第二时间段的情况下，所述驱动方法还包括：
在所述第二时间段之前，控制所述第一复位单元先导通；
在所述第二时间段之后，控制所述第一复位单元先断开；
其中，所述第二时间段持续至少一个行扫描时长。
在一些实施方式中，在所述第二时间段之前，所述隔离单元和所述第一复位单元存在同时导通的至少一个第三时间段，所述驱动方法还包括：
在所述第二时间段之前，控制所述第一复位单元导通，以向所述第六节点传输第一复位信号；
在所述第一复位单元导通后，控制所述隔离单元导通至少一个所述第三时间段，以将所述第一复位信号传输至所述第五节点，其中，所述第三时间段持续至少一个行扫描时长。
在一些实施方式中，所述驱动方法还包括：
在控制所述第一发光控制单元和所述第二发光控制单元导通之前，控制所述第一发光控制单元相比于所述第二发光控制单元先导通至少一个行扫描时长。
本公开实施例第三方面提供一种驱动电路，用于如第二方面中任一项所述的显示面板的驱动方法。
本公开实施例第四方面提供一种显示装置，包括如第一方面中任一项所述的显示面板；和/或，如第三方面所述的驱动电路。
综上，本公开提供的显示面板，包括多个像素电路，像素电路包括：第一发光控制单元，第一发光控制单元电连接于第一节点和第二节点之间，第一节点用于接收第一驱动信号；第二发光控制单元，第二发光控制单元电连接于第三节点和第四节点之间；驱动单元，驱动单元分别与第二节点、第三节点和第五节点电连接；第一数据写入单元，第一数据写入单元电连接于第三节点和第六节点之间，第一数据写入单元包括氧化物晶体管；隔离单元，隔离单元电连接于第五节点和第六节点之间，隔离单元包括多晶硅晶体管发光单元，发光单元的一端与第四节点电连接，另一端用于接收第二驱动信号；其中，第一数据写入单元和隔离单元存在同时导通的第一时间段，且在第一时间段之后隔离单元先于第一数据单元断开。本公开通过在第一数据写入单元和驱动单元之间设置隔离单元，隔离单元包括多晶硅晶体管，在需要停止向第五节点写入电荷的情况下，先截止隔离单元中的多晶硅晶体管，再截止第一数据写入单元的氧化物晶体管。而多晶硅晶体管特别是低温多晶硅晶体管，具有成熟的制作工艺，其半导体层采用多晶硅制成，多晶硅的稳定性更强，对电子束缚力更强，不易受到外界环境影响，而氧化物晶体管稳定性较弱，在长时间的运行下，器件温度上升，电子活动加剧，对电子束缚力进一步降低，所以在晶体管的栅源电压发生波动的情况下，特别容易引起半导体层与氧化层之间的缺陷处电荷积累，产生充放电，造成阈值电压偏移，导致写入驱动晶体管的栅极节点的电位发生改变，从而最终形成的显示屏幕明暗不均。因此，本公开先将隔离单元中的多晶硅晶体管截止，利用多晶硅晶体管稳定性强的特点，在栅源 电压发生波动的情况下，阈值电压不易发生偏移，从而在截止的瞬间，写入驱动晶体管的栅极节点的电位差异大幅减小，继而驱动晶体管所产生的驱动电流还原度高，发光单元的亮度不会产生变暗或变亮的问题，能够改善显示屏幕明暗不均的技术问题，提高显示画面的均一性。
相应的，本公开提供的驱动方法、驱动电路及显示装置也同样具有上述技术效果。
附图说明
图1为本公开实施例提供的一种像素电路的示意性结构框图；
图2为本公开实施例提供的一种氧化物晶体管阈值电压与OLED亮度的关系图；
图3为本公开实施例提供的一种像素电路的示意性结构图；
图4为本公开实施例提供的一种像素电路的示意性信号时序图；
图5为本公开实施例提供的另一种像素电路的示意性结构框图；
图6为本公开实施例提供的另一种像素电路的示意性结构图；
图7为本公开实施例提供的另一种像素电路的示意性信号时序图；
图8为本公开实施例提供的又一种像素电路的示意性结构框图；
图9为本公开实施例提供的又一种像素电路的示意性结构图；
图10为本公开实施例提供的又一种像素电路的示意性信号时序图；
图11为本公开实施例提供的再一种像素电路的示意性结构图；
图12为本公开实施例提供的再一种像素电路的示意性信号时序图；
图13为本公开实施例提供的一种驱动方法的示意性流程图；
图14为本公开实施例提供的一种驱动电路连接关系的示意性结构框图；
图15为本公开实施例提供的一种显示装置的示意性结构图。
其中，图1、图3、图5、图6、图8、图9、图11、图14和图15中部件名称与标号对应关系如下：
1000显示装置；100像素电路，200发光阵列驱动电路，300第一栅极阵列驱动电路，400
第二栅极阵列驱动电路；101第一发光控制单元，102第二发光控制单元，103驱动单元，104第一数据写入单元，105隔离单元，106发光单元，107第一复位单元，108第二数据写入单元，109第二复位单元，110第三复位单元；N1第一节点，N2第二节点，N3第三节点，N4第四节点，N5第五节点，N6第六节点，T5多晶硅晶体管，T6氧化物晶体管，VDD第一驱动信号，VSS第二驱动信号，Vinit1第一复位信号，Vinit2第二复位信号，Vinit3第三复位信号，Data数据信号，T5多晶硅晶体管，T4氧化物晶体管，Ngate第一栅极驱动信号，Pgate第二栅极驱动信号，Reset_n第一复位驱动信号，Reset_p第二复位驱动信号，EM发光控制信号，EM1第一发光控制信号，EM2第二发光控制信号。
具体实施方式
本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那 些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。
本公开实施例第一方面提供一种显示面板，包括多个像素电路，图1为本公开实施例提供的一种像素电路的示意性结构框图，如图1所示，像素电路100包括：第一发光控制单元101，第一发光控制单元101电连接于第一节点N1和第二节点N2之间，第一节点N1用于接收第一驱动信号VDD；第二发光控制单元，第二发光控制单元电连接于第三节点N3和第四节点N4之间；驱动单元103，驱动单元103分别与第二节点N2、第三节点N3和第五节点N5电连接；第一数据写入单元104，第一数据写入单元104电连接于第三节点N3和第六节点N6之间，第一数据写入单元104包括氧化物晶体管；隔离单元105，隔离单元105电连接于第五节点N5和第六节点N6之间，隔离单元105包括多晶硅晶体管；发光单元106，发光单元106的一端与第四节点N4电连接，另一端用于接收第二驱动信号VSS；其中，第一数据写入单元104和隔离单元105存在同时导通的第一时间段，且在第一时间段之后隔离单元105先于第一数据单元断开。
需要说明的是，第一发光控制单元101用于控制第一节点N1和第二节点N2之间的导通和截止，在第一节点N1和第二节点N2导通的情况下，第一驱动信号VDD写入第二节点N2。第二发光控制单元102用于控制第三节点N3和第四节点N4之间的导通和截止。驱动单元103用于在第五节点N5的作用下，控制第二节点N2和第三节点N3之间的导通和截止。在第一发光控制单元101、第二发光控制单元102以及驱动单元103都导通的情况下，发光单元106在第一驱动信号VDD和第二驱动信号VSS作用下发光。其中，隔离单元105用于控制第五节点N5和第六节点N6之间的导通和截止，第一数据写入单元104用于控制第三节点N3和第六节点N6之间的导通和截止，第一时间段表示隔离单元105和第一数据写入单元104同时导通的时间段，在第一时间段，第三节点N3的电位能够通过第一数据写入单元104和隔离单元105写入第五节点N5，第一时间段之后，先将隔离单元105截止，再将第一数据写入单元104截止。而且，隔离单元105包括多晶硅晶体管，第一数据写入单元104包括氧化物晶体管。
可以理解的是，氧化物晶体管如IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)具有低漏电的特性，像素电路100中可以采用氧化物晶体管作为控制信号写入驱动晶体管栅极的隔离开关，能够防止驱动晶体管在导通状态下，栅极电容的电荷流失，继而保证驱动晶体管的导通状态稳定性。但是由于氧化物晶体管目前的工艺成熟度不高，以及氧化物性质比较活泼的特性，导致氧化物晶体管的阈值电压特性容易发生偏移，特别是在电压发生波动的情况。这样，在氧化物晶体管的截止瞬间，阈值电压会产生正向偏移或反向偏移。示例性的，图2为本公开实施例提供的一种氧化物晶体管阈值电压与OLED亮度的关系图，图2种横坐标ΔV_th表示氧化物晶体管阈值电压的波动，单位为V(伏特)，纵坐标ΔIoled/Ioled表示OLED亮度变化百分比。如图2所示，在氧化物晶体管发生正向偏移的情况下，氧化物晶体管阈值电压增大，导致写入驱动管栅极的电荷量增加，驱动晶体管的栅源电压绝对值减小，驱动晶体管产生的驱动电流减小，OLED的亮度比正常情况要暗；反之，在氧化物晶体管发生反向偏移的情况下，氧化物晶体管阈值电压减小，导 致写入驱动管栅极的电荷量减少，驱动晶体管的栅源电压绝对值增大，驱动晶体管产生的驱动电流增大，OLED的亮度比正常情况要亮。因此，基于氧化物晶体管阈值电压的偏移情况，显示屏幕会产生明暗不均的横纹现象。
本公开实施例通过在第一数据写入单元104和驱动单元103之间设置隔离单元105，隔离单元105包括多晶硅晶体管，在第一时间段之后，也就是需要停止向第五节点N5写入电荷的情况下，先截止隔离单元105中的多晶硅晶体管，再截止第一数据写入单元104的氧化物晶体管。而多晶硅晶体管特别是低温多晶硅晶体管，具有成熟的制作工艺，其半导体层采用多晶硅制成，多晶硅的稳定性更强，对电子束缚力更强，不易受到外界环境影响，而氧化物晶体管稳定性较弱，在长时间的运行下，器件温度上升，电子活动加剧，对电子束缚力进一步降低，所以在晶体管的栅源电压发生波动的情况下，特别容易引起半导体层与氧化层之间的缺陷处电荷积累，产生充放电，造成阈值电压偏移，导致写入驱动晶体管的栅极节点的电位发生改变，从而最终形成的显示屏幕明暗不均。因此，本公开实施例先将隔离单元105中的多晶硅晶体管截止，利用多晶硅晶体管稳定性强的特点，在栅源电压发生波动的情况下，阈值电压不易发生偏移，从而在截止的瞬间，写入驱动晶体管的栅极节点的电位差异大幅减小，继而驱动晶体管所产生的驱动电流还原度高，发光单元的亮度不会产生变暗或变亮的问题，能够改善显示屏幕明暗不均的技术问题，提高显示画面的均一性。需要说明的是，第一发光控制单元101、第二发光控制单元102、隔离单元105和第一数据写入单元104可以通过显示面板中的驱动芯片或是处理器进行控制，具体的控制方式不做限定。
示例性的，图3为本公开实施例提供的一种像素电路的示意性结构图，如图3所示，第一发光控制单元101包括晶体管T1，第二发光控制单元102包括晶体管T2，驱动单元103包括晶体管T3，第一数据写入单元104包括氧化物晶体管T4，隔离单元105包括多晶硅晶体管T5，发光单元106包括OLED。其中，氧化物晶体管T4以N型晶体管示例，晶体管T1、晶体管T2、晶体管T3和多晶硅晶体管T5以P型晶体管示例。
图4为本公开实施例提供的一种像素电路的示意性信号时序图，结合图3和图4所示，在发光控制信号EM的高电位作用下，晶体管T1和晶体管T2截止，在第一栅极驱动信号Ngate的高电位作用下，氧化物晶体管T4导通，在第二栅极驱动信号Pgate的低电位作用下，多晶硅晶体管T5导通，氧化物晶体管T4和多晶硅晶体管T5同时导通的第一时间段为图4中的T时段。在t时间段，第三节点N3的电位通过第六节点N6写入第五节点N5，第五节点N5的电位存入晶体管T3的栅极电容中。t时间段之后，在第二栅极驱动信号Pgate的低电位作用下，多晶硅晶体管T5截止，待多晶硅晶体管T5截止后，氧化物晶体管T4可以截止。
容易理解的是，多晶硅晶体管T5与氧化物晶体管T4之间的截止间隔时间可以根据实际进行确定，保证多晶硅晶体管T5完全截止后，氧化物晶体管T4再截止即可。
根据一些实施例，图1和图3中第一数据写入单元104的氧化物晶体管在第一时间段处于饱和区。
需要说明的是，在第一数据写入单元104中的氧化物晶体管处于饱和区时，源漏电流受栅极电位影响很小，因此，在上述第一时间段向第五节点N5写入数据的时候，能够防止第一栅极驱动信号Ngate发生波动造成写入的数据改变，从而能够提高写入驱动单元103中驱动晶体管栅极 电容的电荷量准确性，继而提高驱动电流的精确性，能够使OLED的亮度还原准确。
根据一些实施例，第一数据写入单元104的氧化物晶体管为N型；隔离单元105的多晶硅晶体管为P型；其中，在第一时间段之前，氧化物晶体管的栅极信号的上升沿位于多晶硅晶体管的栅极信号的下降沿之前；在第一时间段之后，氧化物晶体管的栅极信号的下降沿位于多晶硅晶体管的上升沿之后。
示例性的，结合图3和图4所示，在第一时间段即图4中T时刻之前，第一数据单元的氧化物晶体管T4在第一栅极驱动信号Ngate的上升沿开始导通，隔离单元105的多晶硅晶体管T5在第二栅极驱动信号Pagate的下降沿开始导通，且第一栅极驱动信号Ngate的上升沿先于第二栅极驱动信号Pagate的下降沿；在T时刻之后，隔离单元105的多晶硅晶体管T5在第二栅极驱动信号Pagate的上升沿截止，第一数据单元104的氧化物晶体管T4在第一栅极驱动信号Ngate的下降沿截止，且，第一栅极驱动信号Ngate的下降沿后于第二栅极驱动信号Pagate的上升沿。通过将氧化物晶体管T4与多晶硅晶体管T5的导通和截止错开，能够避免氧化物晶体管T4在电压波动瞬间引起的阈值电压偏移，导致写入第五节点N5的电位发生改变。
根据一些实施例，图5为本公开实施例提供的另一种像素电路的示意性结构框图，如图5所示，像素电路100还包括：第一复位单元107，第一复位单元107与第六节点N6电连接，第一复位单元107用于向第六节点N6传输第一复位信号；其中，第一数据写入单元104和第一复位单元107存在同时导通的第二时间段，且在第二时间段之前所述第一复位单元107先于第一数据写入单元104导通，在第二时间段之后第一复位单元107先于第一数据写入单元104关断，第二时间段与第一时间段无交叠。
需要说明的是，第一复位单元107用于在控制信号的作用下向第六节点N6的传输第一复位信号Vinit1。在第一数据写入单元104和第一复位单元107同时导通的第二时间段，第一复位信号Vinit1写入第三节点N3。由于在第一时间段，第一数据写入单元104和隔离单元105同时导通，以向第五节点N5写入第三节点N3的电位，因此，在第一时间段，第一复位单元107不能向第三节点N3写入第一复位信号Vinit1，第一时间段不能与第二时间段存在交叠。
示例性的，图6为本公开实施例提供的另一种像素电路的示意性结构图，如图6所示，以晶体管T6为N型为例，第一复位单元107包括晶体管T6，晶体管T6的栅极接收第一复位驱动信号Reset_n，源极或漏极之一与第六节点N6电连接，另一极接收第一复位信号Vinit1。
图7为本公开实施例提供的另一种像素电路的示意性信号时序图，结合图6和图7所示，在T3时间段即上述第二时间段，第一复位驱动信号Reset_n处于高电位，晶体管T6导通，第一栅极驱动信号Ngate处于高电位，氧化物晶体管T4导通，第一复位信号Vinit1写入第三节点N3，以对第三节点N3进行置位。
在t3阶段之前，晶体管T6先导通，对第六节点N6进行预充电，以对氧化物晶体管T4的栅源电压进行调整去除上一帧显示画面中残留电荷造成的影响。
在t3阶段之后，先断开晶体管T6，能够避免第一复位信号Vinit1持续写入第六节点N6，以影响后续阶段中对第五节点N5的置位。
需要说明的是，由于第三节点N3与驱动单元103中的晶体管T3相连接，对第三节点N3置位，能够对晶体管T3的阈值电压进行调整，消除在上一帧显示画面中晶体管T3阈值电压的偏移， 从而提高驱动电流的精确性，继而能够使OLED的亮度还原准确。
根据一些实施例，在第二时间段之前，隔离单元105和第一复位单元107存在同时导通的至少一个第三时间段，且在第三时间段之前，第一复位单元107先于隔离单元105导通。
示例性的，结合图6和图7所示，在t2时间段，第二栅极驱动信号Pgate处于至少一个低电位的时间段，如图7中t2’时间段，在t2’时间段第一复位驱动信号Reset_n处于高电位，隔离单元105中的多晶硅晶体管T5和第一复位单元107中的晶体管T6同时导通，第一复位信号Vinit1通过多晶硅晶体管T5写入第五节点N5。
需要说明的是，将第五节点N5的电位置为第一复位信号Vinit1，能够清除第五节点N5之前残留的电荷，对驱动单元103中的晶体管T3的栅极应力进行调整以控制晶体管T3的阈值电压，消除在上一帧显示画面中晶体管T3阈值电压的偏移，从而使驱动电流的精确度提高，OLED的亮度还原性提高，继而可以改善显示屏幕的残像问题。
晶体管T6先于多晶硅晶体管T5导通，先对第六节点N6进行置位，从而可以清除第六节点N6中的残留电荷，消除对多晶硅晶体管T5的影响，提高第一复位信号Vinit1写入的准确性。
第三时间段可以存在多个，通过多次对第五节点N5的电位进行置位，能够更好地清除第五节点N5之前残留的电荷，对晶体管T3的阈值电压可以进行多次调整，提高调整效果。
需要说明的是，对第五节点N5的残留电荷进行清除也同样能够减少对多晶硅晶体管T5的特性影响。
根据一些实施例，如图5所示，像素电路100还包括：第二数据写入单元108，第二数据写入单元108与第二节点N2电连接，第二数据写入单元108用于向第二节点N2传输数据信号Data；其中，第二数据写入单元108与隔离单元105的开关状态相同。
需要说明的是，像素电路100还包括第二数据写入单元108，第二数据写入单元108与第二节点N2电连接。第二数据写入单元108导通后，数据信号Data通过驱动单元103、第一数据写入单元104和隔离单元105写入第五节点N5。由于第二数据写入单元108和隔离单元105串联于同一支路中，并且，第二数据写入单元108和隔离单元105功能上绑定，因此，第二数据写入单元108与隔离单元105的开关状态可以相同，从而能够简化显示面板的控制逻辑，降低驱动功耗。而且，在第一复位单元107对第六节点N6置位后，再利用第二数据写入单元108向第五节点N5写入数据信号Data，能够避免第六节点N6残留的电荷对隔离单元105和第一数据写入单元104导通状态的影响，从而提高数据信号Data写入的准确性。
示例性的，如图6所示，以P型晶体管作为示例，第二数据写入单元108包括晶体管T7，晶体管T7的栅极接收第二栅极驱动信号Pgate，源极和漏极中的一者接收数据信号Data，源极和漏极中的另一者与第二节点N2电连接。
结合图6和图7所示，在T2阶段中的第三时间段t2’，晶体管T7和多晶硅晶体管T5在第二栅极驱动信号Pgate的低电位作用下，晶体管T7和多晶硅晶体管T5同时导通，晶体管T6在第一复位驱动信号Reset_n的作用下导通，将第六节点N6的电位置为第一复位信号Vinit1。在该阶段，先对第六节点N6进行置位，以清除其中的残留电荷，消除上一帧显示画面的影响。
在t4阶段，晶体管T7和多晶硅晶体管T5在第二栅极驱动信号Pgate的低电位作用下，在第一时间段，晶体管T7和多晶硅晶体管T5同时导通，数据信号Data通过晶体管T3、晶体管 T2和晶体管T9写入第五节点N5。
在一些示例中，第二数据写入单元108和隔离单元105均受控于同一个驱动电路，因此，能够节约显示面板中的栅线，从而可以减少显示面板中非显示区域的宽度。
根据一些实施例，图8为本公开实施例提供的又一种像素电路的示意性结构框图，如图8所示，像素电路100还包括：第二复位单元109，第二复位单元109与第四节点N4电连接，第二复位单元109用于向第四节点N4传输第二复位信号Vinit2；第三复位单元110，第三复位单元110与第二节点N2电连接，第三复位单元110用于向第二节点N2传输第三复位信号Vinit3；电容Cst，电容Cst的一端电连接于第一节点N1，另一端电连接于第五节点N5。
需要说明的是，第二复位单元109在导通的情况下，将第二复位信号Vinit2写入第四节点N4。第三复位单元110在导通的情况下，将第三复位信号Vinit3写入第二节点N2。电容Cst的两端分别于第一节点N1和第五节点N5电连接，用于存储驱动晶体管T3导通的电荷。
示例性的，图9为本公开实施例提供的又一种像素电路的示意性结构图，如图9所示，以P型晶体管作为示例，第二复位单元109包括晶体管T8，晶体管T8的栅极接收第二复位驱动信号Reset_p，源极和漏极中的一者连接于第四节点N4，源极和漏极中的另一者接收第二复位信号Vinit2。第三复位单元110包括晶体管T9，晶体管T9的栅极也可以接收第二复位驱动信号Reset_p，源极或漏极之一连接于第二节点N2，另一极接收第三复位信号Vinit3。
图10为本公开实施例提供的又一种像素电路的示意性信号时序图，结合图9和图10对本公开实施例提供的像素电路100的各个工作阶段进行说明：
t1阶段，第二复位驱动信号Reset_p处于低电位，晶体管T8和晶体管T9导通，其余晶体管处于截止状态，第二复位信号Vinit2和第三复位信号Vinit3分别写入第二节点N2和第四节点N4，以清除上一帧显示画面后残留的电荷。
t2阶段，第一复位驱动信号Reset_n处于高电位，晶体管T6处于导通状态，在该阶段，多晶硅晶体管T5在第二栅极驱动信号Pgate的作用下，可以导通一次或多次，如t2’时间段。在t2’时间段，第一复位信号Vinit1通过晶体管T6和多晶硅晶体管T5写入第五节点N5，以清除第五节点N5之前残留的电荷，能够对驱动单元103中的晶体管T3的栅极应力进行调整以清除上一帧显示画面中对其阈值电压的影响。，从而使驱动电流的精确度提高，OLED的亮度还原性提高，继而可以改善显示屏幕的残像问题。设置多个t2’时间段，能够提高对晶体管T3的栅极应力调整的效果。
t3阶段，第一复位驱动信号Reset_n处于高电位，第一栅极驱动信号Ngate处于高电位，第二栅极驱动信号Pgate处于高电位，晶体管T6和氧化物晶体管T4导通，晶体管T5截止，第一复位信号Vinit1对第三节点N3进行置位，以清除第三节点N3的残留电荷，对晶体管T3的阈值电压进行偏置，以进一步清除显示画面对其阈值电压的影响。
t4阶段，第一栅极驱动信号Ngate处于高电位，第一复位驱动信号Reset_n处于低电位，氧化物晶体管T4导通，晶体管T6截止。第二栅极驱动信号Pgate存在t4’时间段处于低点位，以使多晶硅晶体管T5和晶体管T7导通，晶体管T3在电容Cst作用下导通。在t4’时间段，数据信号Data通过晶体管T7、晶体管T3、晶体管T4以及多晶硅晶体管T5写入电容Cst。
t5阶段，第二复位驱动信号Reset_p处于低电位，晶体管T9和晶体管T8导通，第三复位 信号Vinit3写入第二节点N2和第三节点N3，第二复位信号Vinit2写入第四节点N4。在该阶段，对第三节点N3进行置位，从而在进入晶体管T2导通后，电荷能够迅速转移到OLED的电容，从而提高OLED点亮速率。对第二节点N2和第三节点N3进行置位，能够对晶体管T3的阈值电压进行调整，以提高驱动电流的精确度。
需要说明的是，t5阶段在本公开实施例提供的显示面板中，持续的时长也可以根据实际自行设置，不做具体限定。
t6阶段，发光控制信号EM处于低电平，晶体管T1和晶体管T2导通，晶体管T3在电容Cst作用下导通。OLED在晶体管T3的驱动电流作用下发光，流入OLED的电流大小可以由如下公式确定：
IOLED＝K(Vsg-|Vth|)2    (1)
其中，K表示与晶体管T3有关工艺设计常数，Vsg表示晶体管T3的源栅电压，Vsg表示晶体管T3的阈值电压，IOLED表示驱动电流。公式(1)中的Vsg可以变换为：
Vsg＝VDD-(Vdata-|Vth|)   (2)
其中，VDD表示第一驱动信号VDD的电势，Vdata表示数据信号Data的电势。
结合公式(1)和公式(2)可以得到公式(3)：
IOLED＝K(VDD-Vdata)2   (3)
需要说明的是，经过t1至t6阶段，本公开实施例提供的显示面板完成对一帧显示画面的驱动过程。
根据一些实施例，如图9所示，第一复位单元107包括氧化物晶体管；和/或，第二数据写入单元108包括多晶硅晶体管；和/或，第二复位单元109包括多晶硅晶体管；和/或，第三复位单元110包括多晶硅晶体管；和/或，第一发光控制单元101包括多晶硅晶体管；和/或第二发光控制单元102包括多晶硅晶体管；和/或，驱动单元103包括多晶硅晶体管。
示例性的，图9中，晶体管T1、晶体管T2、晶体管T3、晶体管T7、晶体管T8和晶体管T9可以为多晶硅晶体管。晶体管T6可以为氧化物晶体管。
需要说明的是，多晶硅晶体管目前工艺成熟，且半导体层采用多晶硅材料制成，从而半导体层对电子的束缚力强，，所以多晶硅晶体管的特性比较稳定，阈值电压不容易受到外界环境影响，但是多晶硅晶体管相比于氧化物晶体管容易漏电。因此，将晶体管T1、晶体管T2、晶体管T3、晶体管T7、晶体管T8和晶体管T9这些与电容Cst没有直接连接的晶体管设置为多晶硅晶体管，能够避免多晶硅晶体管漏电缺陷，并且多晶硅晶体管电子迁移率比较高，导电效果好，与数据信号如VDD、Data等直接相连，能够减小损耗。
需要说明的是，由于晶体管T6串联于多晶硅晶体管T5和电容Cst的支路，存在漏电的风险，因此，将晶体管T6设置为氧化物晶体管，以减少漏电风险。
根据一些实施例，如图9所示，在驱动单元103为P型多晶硅晶体管的情况下，第三复位信号Vinit3的电势大于第一驱动信号VDD的电势；在驱动单元103为N型多晶硅晶体管的情况下，第三复位信号Vinit3的电势小于第一驱动信号VDD的电势。
示例性的，在驱动单元103为P型多晶硅晶体管的情况下，其阈值电压小于零，因此，为了保证晶体管T3导通，所以，可以将晶体管T3的源极或漏极电势调高一些，即第三复位信号Vinit3的电势大于第一驱动信号VDD的电势，使晶体管T3处于正向偏置，从而能够对第二节点N2和第三节点N3均进行置位。
示例性的，在驱动单元103为N型多晶硅晶体管的情况下，其阈值电压大于零，因此，为了保证晶体管T3导通，所以，可以将晶体管T3的源极或漏极电势调低一些，即第三复位信号Vinit3的电势小于第一驱动信号VDD的电势，使晶体管T3处于正向偏置，从而能够对第二节点N2和第三节点N3均进行置位。
根据一些实施例，如图1、图5、图8所示，第一发光控制单元101先于第二发光控制单元102导通至少一个行扫描时长。
示例性的，图11为本公开实施例提供的再一种像素电路的示意性结构图，如图11所示，以P型晶体管作为示例，第一发光控制单元101包括晶体管T1，第二发光控制单元102包括晶体管T2，晶体管T1和晶体管T2的栅极分别接收第一发光控制信号EM1和第二发光控制信号EM2。
图12为本公开实施例提供的再一种像素电路的示意性信号时序图，结合图11和图12所示，t1至t5阶段，第一发光控制信号EM1和第二发光控制信号EM2均处于高电位，晶体管T1和晶体管T2截止，其余与前述相同，不再赘述。
在t6阶段，第一发光控制信号EM1处于低电位，晶体管T1导通，第二发光控制信号EM2处于高电位，晶体管T2截止，可以对第二节点N2进行预充电。
在t7阶段，晶体管T1和晶体管T2均导通，OLED发光。
需要说明的是，在t6阶段，通过对第二节点N2进行预充电，在后续的t7阶段，第二节点N2的预充电电荷能够快速转移到OLED的电容中去，从而提高OLED的发光速率。而且，t6阶段持续至少一个行扫描时长，以保证预充电的充分。该行扫描时长可以理解为相邻帧的显示画面之间的时间间隔。
需要说明的是，第一发光控制信号EM1和第二发光控制信号EM2的脉冲宽度可以相同，时序上相差一个行扫描时长，从而在使用驱动电路提供第一发光控制信号EM1和第二发光控制信号EM2的情况下，每两行像素电路100可以共用一个驱动电路，继而能够减少显示面板的非显示区域宽度。
本公开实施例第二方面提供一种显示面板的驱动方法，应用于如第一方面中任一项的显示面板，图13为本公开实施例提供的一种驱动方法的示意性流程图，如图13所示，上述驱动方法包括：
S110，控制第一数据写入单元104和隔离单元105导通，以使第一数据写入单元104和隔离单元105存在同时导通的第一时间段，向驱动单元103传输写入数据。
参考图1，控制第一数据写入单元104和隔离单元105在第一时间段同时导通，从而能够通过第三节点N3、第六节点N6以及第五节点向驱动单元103传输写入数据。如图3、图6、图9和图11所示，第一数据写入单元104包氧化物晶体管T4，隔离单元105包括多晶硅晶体管T5，驱动单元103可以包括晶体管T3。
需要说明的是，第一时间段表示的是第一数据写入单元104和隔离单元105同时导通的时 段，如图4中的t时间段所示，但是并不限定为第一数据写入单元104和隔离单元105同时导通同时截止。
S120，在第一时间段之后，控制先断开隔离单元105，后断开第一数据写入单元104。
示例性的，经过第一时间段之后，向驱动单元103传输写入数据之后，可以断开第三节点N3至第五节点N5这条支路。
需要说明的是，多晶硅晶体管的制作工艺成熟，且半导体层采用多晶硅材料制作，对电子的束缚力强，，晶体管的特性较为稳定，阈值电压不容易受到外界环境影响。而氧化物晶体管的半导体层由氧化物制成，特性较为不稳定，阈值电压容易发生偏移，特别是在电压波动的情况。参考图3、图6、图9和图11，在第一时间段之后，先断开隔离单元105中的多晶硅晶体管T5，再断开第一数据写入单元104中的氧化物晶体管T4，因此，流入第五节点N5的电流不会由于氧化物晶体管T4可能发生的阈值电压偏移产生突变，导致驱动单元103中的驱动晶体管栅源电压增大或者减小，从而驱动单元103产生的驱动电流不会变化，OLED的亮度不会产生变暗或变亮的问题，继而改善显示屏幕的明暗不均的技术问题。
S130，控制第一发光控制单元101和第二发光控制单元102导通，以使发光单元106在第一驱动信号和第二驱动信号的作用下发光。
示例性的，截止隔离单元105后，再控制第一发光控制单元101和第二发光控制单元102导通，发光单元106在第一驱动信号VDD和第二驱动信号VSS的作用下发光。
需要说明的是，本公开实施例提供的驱动方法同样适用于图6和图7的实施例、图9和图10的实施例以及图11和图12的实施例。
根据一些实施例，如图5所示，在像素电路100包括第一复位单元107，且第一数据写入单元104和第一复位单元107存在同时导通的第二时间段的情况下，驱动方法还包括：在第二时间段之前，控制第一复位单元先导通；在第二时间段之后，控制第一复位单元107先断开；其中，第二时间段持续至少一个行扫描时长。
示例性的，结合图6和图7所示，第一复位单元107包括晶体管T6，上述第二时间段对应图7中的t3阶段，在t3阶段，第一复位信号Vinit1通过晶体管T6和氧化物晶体管T4对第三节点N3置位，以清除上一帧显示画面中的残留电荷，能够对晶体管T3的阈值电压进行调整以提高驱动电流的精确度。第二时间段持续至少一个行扫描时长，从而能够对第三节点N3电荷以充分清除。
在t3阶段之前，晶体管T6先导通，能够使晶体管T6进行预热，以使晶体管T6在t3阶段导通更充分，为向第五节点N5写入数据进行准备。
在t3阶段之后，先断开晶体管T6，能够避免晶体管T6在电压波动的情况下形成阈值电压偏移，提高后续向第五节点N5写入数据的精确性。
需要说明的是，本公开实施例提供的驱动方法同样适用于图9和图10的实施例、图11和图12的实施例。
根据一些实施例，在第二时间段之前，隔离单元105和第一复位单元107存在同时导通的至少一个第三时间段，驱动方法还包括：在第二时间段之前，控制第一复位单元107导通，以向第六节点传输第一复位信号；在第一复位单元107导通后，控制隔离单元105导通至少一个第三 时间段，以将第一复位信号传输至第五节点，其中，第三时间段持续至少一个行扫描时长。
示例性的，结合图6和图7所示，t2’时间段表示上述第三时间段。在t2’时间段将第一复位驱动信号Reset_n处于高电位，隔离单元105中的多晶硅晶体管T5和第一复位单元107中的晶体管T6同时导通，第一复位信号Vinit1通过多晶硅晶体管T5写入第五节点N5，能够清除第五节点N5之前残留的电荷，对驱动单元103中的晶体管T3的栅极应力进行调整以清除上一帧显示画面中对其阈值电压的影响，从而提高驱动电流的精确度，继而可以改善显示屏幕的残像问题。第三时间段可以存在多个，通过多次对第五节点N5的电位进行置位，能够更好地清除第五节点N5之前残留的电荷，从而可以进一步降低晶体管T3阈值电压的偏移可能性。
需要说明的是，本公开实施例提供的驱动方法同样适用于图9和图10的实施例、图11和图12的实施例。
根据一些实施例，驱动方法还包括：在控制第一发光控制单元101和第二发光控制单元102导通之前，控制第一发光控制单元101相比于第二发光控制单元102先导通至少一个行扫描时长。
示例性的，结合图11和图12所示，第一发光控制单元101可以包括晶体管T1，第二发光控制单元102可以包括晶体管T2，晶体管T1的栅极接收第一发光控制信号EM1，晶体管T2的栅极接收第二发光控制信号EM2。
晶体管T2和晶体管T1同时导通对应图12中的t7阶段，t7阶段OLED进入发光状态。在t7阶段之前，即图2中的T6阶段，晶体管T1在第一发光控制信号EM1的作用下导通，晶体管T2在第二发光控制信号EM2的作用下截止，第一驱动信号VDD能够写入第二节点N2和第三节点N3，对驱动单元103中的晶体管T3进行预充电。
需要说明的是，在t6阶段，通过对第二节点N2进行预充电，在后续的t7阶段，第二节点N2的预充电电荷能够快速转移到OLED的电容中去，从而提高OLED的发光速率。而且，t6阶段持续至少一个行扫描时长，以保证预充电的充分。该行扫描时长可以理解为相邻帧的显示画面之间的时间间隔。
本公开实施例第三方面提供一种驱动电路，用于执行如第二方面中任一项的显示面板的驱动方法。
示例性的，图14为本公开实施例提供的一种驱动电路连接关系的示意性结构框图，如图14所示，驱动电路可以包括EOA(Emission gate ON Array，发光阵列驱动电路)电路和GOA(Gate ON Array，栅极阵列驱动)电路。以图3为例，EOA电路为发光阵列驱动电路200，用于向像素电路100提供发光控制信号EM。GOA1电路为第一栅极阵列驱动电路300，用于向像素电路100提供第一栅极驱动信号，如图3中的Ngate。GOA2电路为第二栅极阵列驱动电路400，用于向像素电路100提供第二栅极驱动信号，如图3中的Pgate。
需要说明的是，驱动电路可以在显示面板中的驱动芯片控制下向像素电路100传输控制信号，也可以在其他控制方式下，如远程控制器等，具体不做限定。
本公开实施例第四方面提供一种显示装置，图15为本公开实施例提供一种显示装置的示意性结构图，如图15所示，上述显示装置1000包括如第一方面中任一项的显示面板；和/或，如第三方面的驱动电路。
示例性的，本公开实施例提供的显示装置1000可以应用于车载显示、智能手机、电脑、 医疗显示器、电视、智能穿戴显示等场景中，本公开实施例不作具体限定。
可以理解的是，本公开实施例提供的显示装置1000，包括第一方面中任一项的显示面板，所以也具有上述显示面板的一切有益效果，不再赘述。
以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修该，或者对其中部分技术特征进行等同替换；而这些修该或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (16)

  1. 一种显示面板，包括多个像素电路，所述像素电路包括：
    第一发光控制单元，所述第一发光控制单元电连接于第一节点和第二节点之间，所述第一节点用于接收第一驱动信号；
    第二发光控制单元，所述第二发光控制单元电连接于第三节点和第四节点之间；
    驱动单元，所述驱动单元分别与所述第二节点、所述第三节点和第五节点电连接；
    第一数据写入单元，所述第一数据写入单元电连接于所述第三节点和第六节点之间，所述第一数据写入单元包括氧化物晶体管；
    隔离单元，所述隔离单元电连接于所述第五节点和所述第六节点之间，所述隔离单元包括多晶硅晶体管；
    发光单元，所述发光单元的一端与所述第四节点电连接，另一端用于接收第二驱动信号；
    其中，所述第一数据写入单元和所述隔离单元存在同时导通的第一时间段，且在所述第一时间段之后所述隔离单元先于所述第一数据单元断开。
  2. 根据权利要求1所述的显示面板，其中，所述第一数据写入单元的氧化物晶体管在所述第一时间段处于饱和区。
  3. 根据权利要求1所述的显示面板，其中，所述第一数据写入单元的氧化物晶体管为N型；
    所述隔离单元的多晶硅晶体管为P型；
    在所述第一时间段之前，所述氧化物晶体管的栅极信号的上升沿位于所述多晶硅晶体管的栅极信号的下降沿之前；
    在所述第一时间段之后，所述氧化物晶体管的栅极信号的下降沿位于所述多晶硅晶体管的上升沿之后。
  4. 根据权利要求1所述的显示面板，所述像素电路还包括：
    第一复位单元，所述第一复位单元与所述第六节点电连接，所述第一复位单元用于向所述第六节点传输第一复位信号；
    所述第一数据写入单元和所述第一复位单元存在同时导通的第二时间段，且在所述第二时间段之前所述第一复位单元先于所述第一数据写入单元导通，在所述第二时间段之后所述第一复位单元先于所述第一数据写入单元关断，所述第二时间段与所述第一时间段无交叠。
  5. 根据权利要求4所述的显示面板，其中，在所述第二时间段之前，所述隔离单元和所述第一复位单元存在同时导通的至少一个第三时间段，且在所述第三时间段之前，所述第一复位单元先于所述隔离单元导通。
  6. 根据权利要求4所述的显示面板，所述像素电路还包括：
    第二数据写入单元，所述第二数据写入单元与所述第二节点电连接，所述第二数据写入单元用于向所述第二节点传输数据信号；
    所述第二数据写入单元与所述隔离单元的开关状态相同。
  7. 根据权利要求6所述的显示面板，所述像素电路还包括：
    第二复位单元，所述第二复位单元与所述第四节点电连接，所述第二复位单元用于向所述第四节点传输第二复位信号；
    第三复位单元，所述第三复位单元与所述第二节点电连接，所述第三复位单元用于向所述第 二节点传输第三复位信号；
    电容，所述电容的一端电连接于所述第一节点，另一端电连接于所述第五节点。
  8. 根据权利要求7所述的显示面板，其中，所述第一复位单元包括氧化物晶体管；和/或，
    所述第二数据写入单元包括多晶硅晶体管；和/或，
    所述第二复位单元包括多晶硅晶体管；和/或，
    所述第三复位单元包括多晶硅晶体管；和/或，
    所述第一发光控制单元包括多晶硅晶体管；和/或，
    所述第二发光控制单元包括多晶硅晶体管；和/或，
    所述驱动单元包括多晶硅晶体管。
  9. 根据权利要求8所述的显示面板，其中，在所述驱动单元为P型多晶硅晶体管的情况下，所述第三复位信号的电势大于所述第一驱动信号的电势；
    在所述驱动单元为N型多晶硅晶体管的情况下，所述第三复位信号的电势小于所述第一驱动信号的电势。
  10. 根据权利要求1至9中任一项所述的显示面板，其中，所述第一发光控制单元先于所述第二发光控制单元导通至少一个行扫描时长。
  11. 一种显示面板的驱动方法，应用于如权利要求1至10中任一项所述的显示面板，所述驱动方法包括：
    控制所述第一数据写入单元和所述隔离单元导通，以使所述第一数据写入单元和所述隔离单元存在同时导通的所述第一时间段，向所述驱动单元传输写入数据；
    在所述第一时间段之后，控制先断开所述隔离单元，后断开所述第一数据写入单元；
    控制所述第一发光控制单元和所述第二发光控制单元导通，以使所述发光单元在所述第一驱动信号和所述第二驱动信号的作用下发光。
  12. 根据权利要求11所述的显示面板的驱动方法，在所述像素电路包括第一复位单元，且所述第一数据写入单元和所述第一复位单元存在同时导通的第二时间段的情况下，所述驱动方法还包括：
    在所述第二时间段之前，控制所述第一复位单元先导通；
    在所述第二时间段之后，控制所述第一复位单元先断开；
    其中，所述第二时间段持续至少一个行扫描时长。
  13. 根据权利要求12所述的显示面板的驱动方法，在所述第二时间段之前，所述隔离单元和所述第一复位单元存在同时导通的至少一个第三时间段，所述驱动方法还包括：
    在所述第二时间段之前，控制所述第一复位单元导通，以向所述第六节点传输第一复位信号；
    在所述第一复位单元导通后，控制所述隔离单元导通至少一个所述第三时间段，以将所述第一复位信号传输至所述第五节点，其中，所述第三时间段持续至少一个行扫描时长。
  14. 根据权利要求11至13中任一项所述的显示面板的驱动方法，还包括：
    在控制所述第一发光控制单元和所述第二发光控制单元导通之前，控制所述第一发光控制单元相比于所述第二发光控制单元先导通至少一个行扫描时长。
  15. 一种驱动电路，用于执行如权利要求11至14中任一项所述的显示面板的驱动方法。
  16. 一种显示装置，包括如权利要求1至10中任一项所述的显示面板；和/或，
    如权利要求15所述的驱动电路。
PCT/CN2024/126156 2023-11-30 2024-10-21 显示面板、驱动方法、驱动电路及显示装置 Pending WO2025112978A1 (zh)

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CN110648629A (zh) * 2019-10-31 2020-01-03 厦门天马微电子有限公司 显示面板及其制作方法、显示装置
CN114641862A (zh) * 2020-09-21 2022-06-17 京东方科技集团股份有限公司 显示基板、显示装置
CN112634833A (zh) * 2021-01-07 2021-04-09 武汉华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示面板
CN113903288A (zh) * 2021-04-30 2022-01-07 友达光电股份有限公司 驱动电路
CN114023262A (zh) * 2021-11-25 2022-02-08 武汉华星光电半导体显示技术有限公司 像素驱动电路及显示面板
CN114495802A (zh) * 2022-03-22 2022-05-13 京东方科技集团股份有限公司 像素驱动电路、驱动方法及显示面板

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