Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/60—Impurity distributions or concentrations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/82—Heterojunctions
  • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates
  • H10D64/112—Field plates comprising multiple field plate segments
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

• An embodiment of the present invention relates to a semiconductor device.
• Semiconductor devices such as transistors and diodes that use nitride semiconductors are known to have higher operating voltages and higher current densities than conventional semiconductor devices. In addition, efforts are being made to provide field plates to reduce the electric field.
• the problem that this invention aims to solve is to provide a semiconductor device that can withstand high voltage while suppressing an increase in on-resistance.
• the semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a third electrode, an electrode portion, and a region.
• the second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a larger band gap than the first nitride semiconductor layer.
• the first electrode is provided on the second nitride semiconductor layer.
• the second electrode is provided on the second nitride semiconductor layer.
• the third electrode is provided on the second nitride semiconductor layer between the first electrode and the second electrode.
• the electrode portion is electrically connected to at least one of the first electrode, the second electrode, and the third electrode, and is disposed above the third electrode.
• the region is a region in the second nitride semiconductor layer into which negative fixed charges are introduced and which is separated from the third electrode.
• FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
• FIG. 4 is a cross-sectional view showing a detailed configuration example of a first region 32 .
• 13 is a cross-sectional view taken into consideration the manufacturing margin of the first region 32.
• FIG. FIG. 2 is a diagram showing the density of two-dimensional electron gas and the relaxation effect of an electric field.
• FIG. 11 is a schematic cross-sectional view of a semiconductor device 1 according to a second embodiment.
• FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 according to this embodiment.
• This semiconductor device 1 is a HEMT (High Electron Mobility Transistor) that uses a nitride semiconductor such as GaN (gallium nitride), AlGaN (aluminum gallium nitride), or InGaN (indium gallium nitride).
• the semiconductor device 1 according to this embodiment has a lateral device structure that uses a nitride semiconductor.
• the semiconductor device 1 includes a substrate 2, a buffer layer 4, a first nitride semiconductor layer 6, a second nitride semiconductor layer 8, a source electrode (an example of a first electrode) 10, a gate electrode (an example of a third electrode) 12, a drain electrode (an example of a second electrode) 14, a gate field plate electrode portion 16 (an example of a first electrode portion), a field plate electrode portion (an example of a second electrode portion) 18, a source field plate electrode portion (an example of a third electrode portion) 20, a drain field plate electrode portion 22 (an example of a fourth electrode portion), an insulating film 24, a first insulating layer 26, a second insulating layer 28, a third insulating layer 30, a first region 32, and a second region 34.
• the X direction, the Y direction perpendicularly intersecting the X direction, and the Z direction perpendicularly intersecting the X direction and the Y direction are defined.
• the Z direction is the direction in which the substrate 2, the buffer layer 4, the first nitride semiconductor layer 6, and the second nitride semiconductor layer 8 are stacked.
• the upward direction of the drawings in this specification may be referred to as "top” and the downward direction of the drawings as “bottom.” In this specification, the concepts of "top” and “bottom” are not necessarily terms that indicate a relationship with the direction of gravity.
• the substrate 2 for example, a Si (silicon) substrate or a sapphire substrate is used.
• the buffer layer 4 is provided on the substrate 2.
• the buffer layer 4 reduces the lattice mismatch with the substrate 2.
• the substrate 2 and the buffer layer 4 are sometimes referred to as an underlayer.
• the first nitride semiconductor layer 6 is provided on the buffer layer 4.
• the first nitride semiconductor layer 6 is, for example, undoped Al x Ga 1-xN (0 ⁇ X ⁇ 1). More specifically, the first nitride semiconductor layer 6 is, for example, undoped GaN.
• the first nitride semiconductor layer 6 functions as a channel layer.
• the film thickness of the first nitride semiconductor layer 6 is, for example, 1 ⁇ m or more and 10 ⁇ m or less.
• the second nitride semiconductor layer 8 is provided on the first nitride semiconductor layer 6.
• the band gap of the second nitride semiconductor layer 8 is configured to be larger than the band gap of the first nitride semiconductor layer 6.
• the second nitride semiconductor layer 8 is, for example, undoped Al Y Ga 1-Y N (0 ⁇ Y ⁇ 1, X ⁇ Y). More specifically, the second nitride semiconductor layer 8 is, for example, undoped Al 0.2 Ga 0.8 N.
• the second nitride semiconductor layer 8 functions as a barrier layer.
• the film thickness of the second nitride semiconductor layer 8 is, for example, 15 nm to 50 nm, and preferably 30 nm.
• a heterojunction interface is provided between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8.
• a two-dimensional electron gas (2DEG) is formed at the heterojunction interface and becomes carriers.
• the substrate 2, the buffer layer 4, the first nitride semiconductor layer 6, and the second nitride semiconductor layer 8 are provided parallel to a plane including an X axis parallel to the X direction and a Y axis parallel to the Y direction, that is, an XY plane.
• the interface between the substrate 2 and the buffer layer 4, the interface between the buffer layer 4 and the first nitride semiconductor layer 6, and the interface between the first nitride semiconductor layer 6 and the second nitride semiconductor layer 8 are provided parallel to the XY plane.
• the Y direction is the direction in which carriers flow in the semiconductor device 1, which is a HEMT. In other words, the Y direction is the gate length direction of the semiconductor device 1.
• the X direction is the gate width direction of the semiconductor device 1.
• the source electrode 10 is provided on the second nitride semiconductor layer 8.
• the source electrode 10 functions as a source electrode of the semiconductor device 1.
• the source electrode 10 is configured to include, for example, a layered structure of titanium (Ti) and aluminum (Al).
• the drain electrode 14 is provided on the second nitride semiconductor layer 8.
• the drain electrode 14 functions as the drain electrode of the semiconductor device 1.
• the drain electrode 14 is configured to include, for example, a laminated structure of titanium (Ti) and aluminum (Al).
• the distance between the source electrode 10 and the drain electrode 14 is, for example, 5 ⁇ m or more and 30 ⁇ m or less.
• the insulating film 24 is provided on the second nitride semiconductor layer 8, between the source electrode 10 and the drain electrode 14.
• the insulating film 24 is in direct contact with the second nitride semiconductor layer 8.
• the insulating film 24 is composed of an insulating material.
• the insulating material is silicon nitride (SiN).
• the material contained in the insulating film 24 is not limited to this.
• silicon oxide (SiO), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), aluminum nitride (AlN), aluminum oxide (AlO), etc. may be used.
• the film thickness of the insulating film 24 in the Z direction is, for example, 20 nm to 30 nm.
• the gate electrode 12 is provided on the second nitride semiconductor layer 8 between the source electrode 10 and the drain electrode 14. More specifically, the gate electrode 12 is provided on the insulating film 24 between the second nitride semiconductor layer 8 and the first insulating layer 26.
• the gate electrode 12 includes, for example, a layered structure of nickel (Ni) and gold (Au), titanium nitride (TiN) or polycrystalline silicon (Poly-Si). The bottom surface of the gate electrode 12 is in contact with the insulating film 24.
• the first insulating layer 26 is provided on the insulating film 24 and on the gate electrode 12.
• the first insulating layer 26 is composed of, for example, silicon nitride (SiN).
• the material contained in the first insulating layer 26 is not limited to this.
• the first insulating layer 26 may be composed of, for example, silicon oxide (SiO), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), aluminum nitride (AlN), aluminum oxide (AlO), etc.
• the film thickness of the first insulating layer 26 in the Z direction is, for example, 200 nm to 300 nm.
• the gate field plate electrode portion 16 has a portion that extends along the upper surface of the first insulating layer 26, and one end is electrically connected to the gate electrode 12. That is, one end of the gate field plate electrode portion 16 is electrically connected to the upper surface of the gate electrode 12.
• the gate field plate electrode portion 16 extends upward through the first insulating layer 26 and extends in the gate length direction above the first insulating layer 26.
• the form of the gate field plate electrode portion 16 is not limited to this.
• the gate field plate electrode portion 16 is used to alleviate the electric field in the semiconductor device 1.
• the gate field plate electrode portion 16 has a structure that includes, for example, Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or a layered structure of titanium (Ti) and aluminum (Al).
• the field plate electrode portion 18 has a portion that extends along the upper surface of the first insulating layer 26 between the gate field plate electrode portion 16 and the drain electrode 14. That is, the field plate electrode portion 18 is provided on the first insulating layer 26 between the insulating film 24 and the second insulating layer 28.
• the field plate electrode portion 18 is electrically connected to, for example, the source electrode 10 using, for example, a wiring provided in the gate width direction (not shown).
• the field plate electrode portion 18 is used to alleviate the electric field in the semiconductor device 1.
• the field plate electrode portion 18 has a structure that includes, for example, Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or a layered structure of titanium (Ti) and aluminum (Al).
• the second insulating layer 28 is provided on the first insulating layer 26, on the gate field plate electrode portion 16, and on the field plate electrode portion 18.
• the second insulating layer 28 is composed of, for example, silicon dioxide (SiO2), which is a silicon oxide. Alternatively, it may be composed of silicon oxide such as silicon monoxide (SiO), silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), aluminum nitride (AlN), aluminum oxide (AlO), etc.
• the material contained in the second insulating layer 28 is not limited to this.
• the source field plate electrode portion 20 has one end electrically connected to the source electrode 10, and has a portion extending along the upper surface of the first insulating layer 26 on the gate field plate electrode portion 16 and on the field plate electrode portion 18. That is, one end of the source field plate electrode portion 20 is provided, for example, on the source electrode 10 and is electrically connected to the source electrode 10.
• the source field plate electrode portion 20 is provided on the source electrode 10, on the gate electrode 12, on the gate field plate electrode portion 16, on the field plate electrode portion 18, on the insulating film 24, and on the second insulating layer 28 between the first insulating layer 26 and the third insulating layer 30.
• the source field plate electrode portion 20 is used to alleviate the electric field in the semiconductor device 1.
• the source field plate electrode portion 20 is, for example, a structure including a laminated structure of Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or titanium (Ti) and aluminum (Al).
• the drain wiring electrode portion 22 has one end electrically connected to the drain electrode 14.
• the drain wiring electrode portion 22 is provided, for example, on the second insulating layer 28.
• the drain field plate electrode portion 22 is used to alleviate the electric field in the semiconductor device 1.
• the drain field plate electrode portion 22 has a structure including, for example, Al (aluminum), Cu (copper), W (tungsten), TiN (titanium nitride), or a layered structure of titanium (Ti) and aluminum (Al).
• the first region 32 and the second region 34 are configured in the second nitride semiconductor layer 8 according to the positions of the ends E16, 18 of the electrode portions 16, 18 on the drain electrode 14 side, and are negatively charged regions separated from the gate electrode 12. That is, the first region 32 and the second region 34 are regions in the second nitride semiconductor layer 8 into which negative fixed charges have been introduced and which are separated from the gate electrode 12.
• the ranges of the first region 32 and the second region 34 in the y direction are, for example, 0.3 um or more and 0.6 um or less, respectively.
• the first region 32 is formed at the end E16 of the gate field plate electrode portion 16 of the second nitride semiconductor layer 8 on the drain electrode 14 side.
• the first region 32 is a region into which a halogen element has been introduced.
• the halogen element is, for example, fluorine (F) or chlorine (Cl). That is, the first region 32 is a halogen-implanted region into which a negative fixed charge has been introduced by annealing.
• the annealing process diffuses the halogen element in the gate length direction (y direction), so that the charge changes gradually and the electric field also changes smoothly.
• the halogen element is introduced by, for example, a CDE (Chemical Dry Etching) method using a gas containing CF4.
• the gate field plate electrode portion 16 reduces the electric field concentration at the end of the gate electrode 12.
• electric field concentration remains at the end E16 of the gate field plate electrode portion 16 on the drain electrode 14 side. Therefore, the first region 32 is used to reduce the electric field concentration that occurs at the end E16. This further improves the breakdown voltage of the semiconductor device 1.
• the second region 34 is formed at the end E18 of the field plate electrode portion 18 of the second nitride semiconductor layer 8 on the drain electrode 14 side.
• the second region 34 is a region into which a halogen element has been introduced.
• the halogen element is, for example, fluorine (F) or chlorine (Cl). That is, the second region 34 is a halogen-implanted region into which a negative fixed charge has been introduced by annealing.
• the annealing process diffuses the halogen element in the gate length direction (y direction), so that the charge changes gradually and the electric field also changes smoothly.
• the halogen element is introduced by, for example, a CDE (Chemical Dry Etching) method using a gas containing CF4.
• the field plate electrode portion 18 reduces the electric field concentration.
• electric field concentration remains at the end E18 of the field plate electrode portion 18 on the drain electrode 14 side. Therefore, the second region 34 is used to reduce the electric field concentration that occurs at the end E18. This further improves the breakdown voltage of the semiconductor device 1.
• the range of the first region 32 and the second region 34 is limited to the range shown in FIG. 2.
• FIG. 2 is a cross-sectional view showing a detailed configuration example of the first region 32.
• the second region 34 also has a similar configuration.
• the first region 32 is configured to be flush with the upper surface of the second nitride semiconductor layer 8, for example, on the insulating film 24 side.
• the range in which the first region 32 is configured is set based on the peak position of the electric field generated by the gate field plate electrode portion 16.
• This peak position is the end E16 on the drain electrode 14 side of the gate field plate electrode portion 16. This peak rises sharply at the end E16 and decreases while tailing towards the drain electrode 14 side.
• the length of the first region 32 along the surface of the second nitride semiconductor layer 8 is, for example, 0.4 ⁇ m from the end E16 on the drain electrode 14 side. This width is set according to the area where the electric field is concentrated.
• the first region 32 is positioned away from the gate electrode 12 so that the negative fixed charge of the first region 32 does not affect the switching operation of the gate electrode 12.
• the depth is within a range that does not reach the two-dimensional electron gas (2DEG).
• the depth of the first region 32 is within the range of the second nitride semiconductor layer 8.
• the concentration of the halogen element introduced can be changed according to the electric field generated by the field plate electrode portion 18.
• the concentration of the halogen element introduced in the first region 32 is approximately the maximum concentration of the two-dimensional electron gas (2DEG). Since the activation rate of the first region 32 and the second region 34 is 50% or less, even if a halogen element is injected at a concentration approximately equal to the two-dimensional electron gas (2DEG), the reduction in the two-dimensional electron gas in the injected portion is 50% or less, and the effect on the on-resistance is also suppressed.
• FIG. 3 is a cross-sectional view of the first region 32 taking into consideration the manufacturing margin.
• FIG. 3 uses the example of the first region 32 for explanation, but the configuration of the second region 34 is similar.
• the electric field peak is maximum at the end E16, so if the first region 32 moves away from the end E16 toward the drain electrode 14, the effect of mitigating the electric field is reduced. Therefore, for example, the first region 32 is configured to be extended toward the gate electrode by approximately 0.2 um to accommodate the manufacturing margin. This prevents the first region 32 from moving away from the end E16 toward the drain electrode 14.
• FIG. 4 is a diagram showing the density of the two-dimensional electron gas and the relaxation effect of the electric field.
• Schematic diagram Ed is a diagram showing the density of the two-dimensional electron gas during operation of the semiconductor device 1.
• the density is shown at three levels: “low”, “medium”, and “high”.
• the density of the two-dimensional electron gas increases as the level increases from “low”, “medium” to "high”.
• Line L10 shows the electric field strength in the absence of the first region 32 and the second region 34.
• Line L12 shows the electric field strength in the presence of the first region 32 and the second region 34.
• the vertical axis represents the electric field strength, and the horizontal axis corresponds to the Y coordinate.
• the density of the two-dimensional electron gas is at a "high" level between the drain side end of the source field plate electrode portion 20 and the gate side end of the drain field plate electrode portion 22. It is at a “medium” level between the end E16 on the drain electrode 14 side of the gate field plate electrode portion 16 and the end of the field plate electrode portion 18 on the gate electrode 12 side. Similarly, it is at a “medium” level between the end E18 on the drain electrode 14 side of the field plate electrode portion 18 and the drain side end of the source field plate electrode portion 20. Furthermore, the lower part of the gate electrode 12 is at a "low" level.
• a voltage (drain voltage) is applied between the drain electrode 14 and the gate electrode 12.
• the electric field strength tends to concentrate at the end E16 of the gate field plate electrode portion 16 on the drain electrode 14 side, and at the end E18 of the field plate electrode portion 18 on the drain electrode 14 side, as shown by line L10.
• a first region 32 and a second region 34 having a negative fixed charge are formed at the ends of end E16 and end E18 on the drain electrode 14 side, so that the electric field concentrated at end E16 and end E18 is alleviated, as shown by line L12.
• the first region 32 and the second region 34 alleviate the concentration of the electric field generated at end E16 and end E18, further improving the breakdown voltage of the semiconductor device 1.
• the semiconductor device 1 has electrode portions 16, 18 electrically connected to at least one of the source electrode 10, gate electrode 12, and drain electrode 14, disposed above the gate electrode 12, and has ends E16, E18 located closer to the drain electrode 14 than the end of the gate electrode 12 on the drain electrode 14 side, and the first region 32 and the second region 34 are configured as negatively charged regions separated from the gate electrode 12 according to the positions of ends E16, E18 in the second nitride semiconductor layer 8. This reduces the effect of the negative charge on the gate electrode 12, while mitigating the concentration of the electric field generated at ends E16 and E18, thereby further improving the breakdown voltage of the semiconductor device 1.
• the semiconductor device 1 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that the introduction concentration of the halogen element in the region where the halogen element is introduced is changed according to the magnitude of the peak of the electric field.
• the differences from the semiconductor device 1 according to the first embodiment will be described below.
• FIG. 5 is a schematic cross-sectional view of the semiconductor device 1 according to the second embodiment.
• a third region 36 is further configured at the end E20 on the drain side of the source field plate electrode portion 20, and a fourth region 38 is further configured at the end E22 of the drain wiring electrode portion 22, which is different from the semiconductor device 1 according to the first embodiment.
• the introduction concentration of the halogen element in the first region 32, the second region 34, the third region 36, and the fourth region 38 is changed according to the magnitude of the peak of the electric field.
• the magnitude of the peak of the electric field increases in the order of end E22, end E20, end E16, and end E18, and therefore the introduction concentration of the halogen element also increases in the order of fourth region 38, third region 36, first region 32, and second region 34.
• at least one of the first region 32, second region 34, third region 36, and fourth region 38 according to this embodiment corresponds to the region.
• the concentration of the electric field generated at the ends E22, E20, E16, and E18 is alleviated to the same extent, and the concentration of the halogen element introduced is suppressed, thereby suppressing the effect on the on-resistance of the semiconductor device 1.
• the gate field plate electrode portion 16, the field plate electrode portion 18, the source field plate electrode portion 20, and the drain wiring electrode portion 22 have portions that extend in the direction (y direction) along the upper surface of the second nitride semiconductor layer 8, and the first region 32, the second region 34, the third region 36, and the fourth region 38 are configured according to the positions of the ends E16, E18, E20, and E22 on the side closer to the second electrode. This allows the electric field generated at the positions of the ends E16, E18, E20, and E22 to be alleviated, and the semiconductor device 1 can be made to have a high withstand voltage.
• the introduction concentration of the halogen element is changed according to the magnitude of the electric field strength generated at the positions of the ends E16, E18, E20, and E22, the introduction of the halogen element can be suppressed, and therefore the semiconductor device 1 can be made to have a high withstand voltage while suppressing an increase in on-resistance.

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• 2023
  • 2023-09-20 JP JP2025547041A patent/JPWO2025062526A1/ja active Pending
  • 2023-09-20 WO PCT/JP2023/034091 patent/WO2025062526A1/ja active Pending
  • 2023-09-20 CN CN202380095641.7A patent/CN120826998A/zh active Pending
• 2025
  • 2025-08-28 US US19/313,718 patent/US20250386538A1/en active Pending

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