WO2025057931A1 - コンデンサおよびその製造方法 - Google Patents

コンデンサおよびその製造方法 Download PDF

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Publication number
WO2025057931A1
WO2025057931A1 PCT/JP2024/032343 JP2024032343W WO2025057931A1 WO 2025057931 A1 WO2025057931 A1 WO 2025057931A1 JP 2024032343 W JP2024032343 W JP 2024032343W WO 2025057931 A1 WO2025057931 A1 WO 2025057931A1
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Prior art keywords
dielectric film
film
insulating substrate
main surface
external connection
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PCT/JP2024/032343
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English (en)
French (fr)
Japanese (ja)
Inventor
悠人 山本
直樹 岩地
晃生 増成
起輝 西嶋
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to JP2025545682A priority Critical patent/JPWO2025057931A1/ja
Priority to DE112024002888.8T priority patent/DE112024002888T5/de
Priority to CN202480048192.5A priority patent/CN121548870A/zh
Publication of WO2025057931A1 publication Critical patent/WO2025057931A1/ja
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)

Definitions

  • the present invention relates to a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film, and a method for manufacturing the same.
  • Patent Document 1 Japanese Patent Application Publication No. 2003-249417
  • Patent Document 2 Japanese Patent Application Publication No. 2008-130778
  • Patent Document 3 Japanese Patent Application Publication No. 2009-49212
  • Patent Document 3 disclose a capacitor having a capacitance forming portion made up of a conductive structure consisting of multiple pillars, a dielectric film covering the surface of the structure, and a conductive film covering the dielectric film.
  • Patent Document 4 discloses a capacitor in which a conductive structure is formed from a porous metal body instead of multiple pillars.
  • the porous metal body that constitutes the structure is composed of a sintered body of metal particles, and both the dielectric layer and the conductive film are formed by the atomic layer deposition (ALD) method.
  • ALD atomic layer deposition
  • a capacitor having a capacitance forming part with an uneven outermost surface such as the capacitor disclosed in Patent Document 4
  • film stresses occurring in the dielectric film and conductive film after mounting, or externally applied stresses may concentrate on the outer edge of the capacitance forming part, causing damage such as cracks in that part.
  • damage such as cracks in that part.
  • Such damaged parts are prone to short circuits, resulting in a loss of functionality as a capacitor.
  • the present invention has therefore been made to solve the above-mentioned problems, and aims to improve the reliability after mounting in a capacitor having a capacitance forming portion consisting of a conductive structure, a dielectric film, and a conductive film, and further to make it possible to manufacture such a capacitor.
  • the capacitor according to the present invention comprises an insulating substrate having a main surface, a capacitance forming portion provided on the main surface, and a first external connection wiring and a second external connection wiring connected to the capacitance forming portion.
  • the capacitance forming portion includes a conductive uneven or porous structure connected to the first external connection wiring, a dielectric film covering the surface of the structure, and a conductive film covering a portion of the dielectric film and connected to the second external connection wiring.
  • the outermost surface of the capacitance forming portion has an uneven shape.
  • the dielectric film has an exposed portion that is not covered by the conductive film, and a non-exposed portion that is covered by the conductive film.
  • the outer edge of the capacitance forming portion in a direction parallel to the main surface is defined by the exposed portion.
  • a method for manufacturing a capacitor according to a second aspect of the present invention includes the following steps. (a) an insulating substrate having a major surface is provided; (b) forming a first external connection wiring on the insulating substrate; (c) forming a conductive irregular or porous structure on the main surface; (d) forming a first dielectric film so as to cover a surface of the structure, with the structure and the first external connection wiring connected to each other; (e) forming a second dielectric film having adhesion to a conductive film so as to cover a surface of the first dielectric film while the first dielectric film is formed; (f) forming a third dielectric film having no adhesion to the conductive film so as to cover the surface of an outer edge portion of the second dielectric film in a direction parallel to the main surface of the second dielectric film while the second dielectric film is formed; (g) with the third dielectric film formed, the conductive film is formed so as to cover the surface of the second dielectric film in the portion not covered by the third di
  • a method for manufacturing a capacitor according to a third aspect of the present invention includes the following steps. (a) an insulating substrate having a major surface is provided; (b) forming a first external connection wiring on the insulating substrate; (c) forming a conductive irregular or porous structure on the main surface; (d) forming a first dielectric film so as to cover a surface of the structure, with the structure and the first external connection wiring connected to each other; (e) forming a resist film so as to cover an outer edge portion of the first dielectric film in a direction parallel to the main surface while the first dielectric film is formed; (f) with the resist film formed, a process of forming a second dielectric film having adhesion to a conductive film so as to cover the resist film and the first dielectric film in a portion not covered by the resist film.
  • the present invention improves the reliability of a capacitor having a capacitance forming portion made of a conductive structure, a dielectric film, and a conductive film after mounting, and also makes it possible to manufacture such a capacitor.
  • FIG. 1A and 1B are a schematic front view and a schematic plan view of a capacitor in accordance with a first embodiment
  • FIG. 2 is a schematic cross-sectional view of the capacitor shown in FIG. 3 is an enlarged cross-sectional view of a main part of the capacitance forming portion shown in FIG. 2
  • 4 is a flow diagram showing a method for manufacturing a capacitor according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view for explaining step S5 of the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S6 of the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S7 of the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S8 of the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S9 of the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S10 of the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S11 of the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S12 of the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S13 in the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S14 in the manufacturing flow shown in FIG. 4.
  • 5 is a schematic cross-sectional view for explaining step S15 of the manufacturing flow shown in FIG. 4.
  • FIG. 11 is a schematic cross-sectional view of a capacitor according to a first modified example.
  • FIG. 11 is a schematic cross-sectional view of a capacitor according to a second modified example.
  • FIG. 11 is a schematic cross-sectional view of a capacitor according to a second embodiment.
  • 20 is an enlarged cross-sectional view of a main part of the capacitance forming portion shown in FIG. 19 .
  • FIG. 11 is a flow diagram showing a method for manufacturing a capacitor according to a second embodiment. 22 is a schematic cross-sectional view for explaining step S9B1 of the manufacturing flow shown in FIG. 21.
  • FIG. 22 is a schematic cross-sectional view for explaining step S9B2 of the manufacturing flow shown in FIG. 21. 22 is a schematic cross-sectional view for explaining step S10 of the manufacturing flow shown in FIG. 21.
  • FIG. 11 is a schematic cross-sectional view of a capacitor according to a third embodiment. 26 is an enlarged cross-sectional view of a main part of the capacitance forming portion shown in FIG. 25 .
  • FIG. 11 is a flow diagram showing a method for manufacturing a capacitor according to a third embodiment.
  • 28 is a schematic cross-sectional view for explaining step S12 of the manufacturing flow shown in FIG. 27. 28 is a schematic cross-sectional view for explaining step S9B1 of the manufacturing flow shown in FIG. 27.
  • FIG. 28 is a schematic cross-sectional view for explaining step S14 of the manufacturing flow shown in FIG. 27.
  • 28 is a schematic cross-sectional view for explaining step S10 of the manufacturing flow shown in FIG. 27.
  • FIG. 11 is a schematic cross-sectional view of a capacitor according to a fourth embodiment.
  • 33 is an enlarged cross-sectional view of a main portion of the capacitance forming portion shown in FIG. 32 .
  • FIG. 13 is a flow diagram showing a method for manufacturing a capacitor according to a fourth embodiment.
  • a schematic cross-sectional view showing the state after step S5 of the manufacturing flow shown in Figure 34 is completed.
  • 35 is a schematic cross-sectional view for explaining step S5D of the manufacturing flow shown in FIG. 34.
  • FIG. 13 is a schematic cross-sectional view of a capacitor according to a fifth embodiment. 38 is an enlarged cross-sectional view of a main portion of the capacitance forming portion shown in FIG. 37 .
  • FIG. 13 is a flow diagram showing a method for manufacturing a capacitor according to a fifth embodiment.
  • FIG. 13 is a schematic cross-sectional view of a capacitor according to a sixth embodiment. 41 is an enlarged cross-sectional view of a main part of the capacitance forming portion shown in FIG. 40;
  • FIG. 13 is a flow diagram showing a method for manufacturing a capacitor according to a sixth embodiment.
  • FIG. 13 is a schematic cross-sectional view of a capacitor according to a seventh embodiment.
  • FIG. 13 is a schematic cross-sectional view of a capacitor according to a seventh embodiment.
  • FIG. 13 is a flow diagram showing a method for manufacturing a capacitor according to a seventh embodiment.
  • FIG. 13 is a schematic cross-sectional view of a capacitor according to an eighth embodiment.
  • FIG. 13 is a schematic cross-sectional view of a capacitor according to a ninth embodiment.
  • Fig. 1(A) is a schematic front view of a capacitor according to a first embodiment.
  • Fig. 1(B) is a schematic plan view of the capacitor as viewed from the direction of arrow IB shown in Fig. 1(A).
  • Fig. 2 is a schematic cross-sectional view of the capacitor taken along line II-II shown in Fig. 1(B).
  • Figs. 3(A) and 3(B) are enlarged cross-sectional views of essential parts of regions IIIA and IIIB, respectively, of the capacitance forming portion shown in Fig. 2.
  • capacitor 1A has a flat, roughly rectangular parallelepiped shape, with both the bottom and top surfaces configured as mounting surfaces for a wiring board or the like.
  • Capacitor 1A mainly comprises an insulating substrate 10, a capacitance forming portion 20, and a sealing portion 30. Of these, capacitance forming portion 20 is provided so as to face insulating substrate 10. Capacitance forming portion 20 is located inside capacitor 1A by being sealed by insulating substrate 10 and sealing portion 30 provided on insulating substrate 10.
  • the insulating substrate 10 is provided with a first via conductor 13 and a first bump 16.
  • the first via conductor 13 and the first bump 16 constitute one of a pair of external connection wirings for electrically connecting the capacitance forming portion 20 located inside the capacitor 1A to an external circuit.
  • the pair of external connection wirings includes a first external connection wiring as an anode and a second external connection wiring as a cathode, and the first via conductor 13 and the first bump 16 constitute a part of the first external connection wiring.
  • the second external connection wiring is composed of an extraction electrode 18, a second via conductor 14, and a second bump 17, which will be described later.
  • the insulating substrate 10 is a flat plate-shaped member having a first main surface 10a as a main surface and a second main surface 10b located on the opposite side to the first main surface 10a.
  • a substrate having electrical insulation properties and preferably a substrate mainly composed of an inorganic material. More specifically, as the insulating substrate 10, a substrate mainly composed of any of Si, Al2O3 , ZrO2 , BN, Si3N4 , AlN , MgO, Mg2SiO4 , BaTiO3 , SrTiO3 , and CaTiO3 can be used.
  • the thickness and size of the insulating substrate 10 are not particularly limited, but it is preferable to use an alumina substrate that is rectangular in plan view, for example, with a thickness of 5 ⁇ m to 75 ⁇ m and a side length of 500 ⁇ m to 2000 ⁇ m.
  • the insulating substrate 10 has a first through hole 11.
  • the first through hole 11 penetrates the insulating substrate 10 so as to reach from the first main surface 10a to the second main surface 10b.
  • the first through hole 11 is filled with a first via conductor 13.
  • the shape of the first via conductor 13 is, for example, approximately cylindrical.
  • the first via conductor 13 constitutes part of the first external connection wiring described above. When viewed along the normal direction of the first main surface 10a of the insulating substrate 10, the first via conductor 13 is provided within the region in which the capacitance forming portion 20 is arranged.
  • the first via conductor 13 can be made of various wiring materials, but is preferably made of a metal material with particularly high electrical conductivity.
  • the material of the first via conductor 13 can be, for example, a metal material whose main material is any of Ni, Ag, Cu, Au, Pt, Mo, and W.
  • the material of the first via conductor 13 can be changed as appropriate to suit the mounting environment of the capacitor 1A according to this embodiment.
  • the first via conductor 13 is made of Ni.
  • the axial length and size of the first via conductor 13 are not particularly limited and are set appropriately according to the thickness and size of the insulating substrate 10.
  • the axial length of the first via conductor 13 is preferably, for example, 5 ⁇ m or more and 75 ⁇ m or less, and the diameter is preferably, for example, 15 ⁇ m or more and 150 ⁇ m or less.
  • the first via conductor 13 is made of Ni and has an axial length of 75 ⁇ m and a diameter of 150 ⁇ m.
  • a first bump 16 is provided on the second main surface 10b of the insulating substrate 10 so as to cover the first via conductor 13.
  • the first bump 16 serves as a bonding material for mounting the capacitor 1A on a wiring board or the like, and for electrically connecting the capacitance forming portion 20 of the capacitor 1A to an external circuit.
  • the first bump 16 is provided so as to protrude from the second main surface 10b of the insulating substrate 10.
  • the shape of the first bump 16 is approximately semispherical.
  • the first bump 16 constitutes part of the first external connection wiring described above.
  • the first bump 16 can be made of various wiring materials, but is preferably made of a metal material with particularly high electrical conductivity.
  • the material of the first bump 16 can be, for example, a metal material whose main component is any of Ni, Ag, Cu, Au, and Sn. In this embodiment, the first bump 16 is made of Au.
  • the size of the first bump 16 is not particularly limited and is set appropriately according to the size of the first via conductor 13.
  • connection conductor 15 is provided on the first main surface 10a of the insulating substrate 10 so as to cover the first via conductor 13. This allows the connection conductor 15 to be electrically connected to the first via conductor 13.
  • connection conductor 15 is, for example, composed of a conductive layer having a predetermined thickness.
  • the connection conductor 15 is composed of a single conductive layer and is provided so as to cover the entire surface of the first main surface 10a.
  • the connection conductor 15 constitutes part of the first external connection wiring described above.
  • the connecting conductor 15 can be made of various wiring materials, but is preferably made of a metal material with particularly high electrical conductivity.
  • the material of the connecting conductor 15 can be, for example, a metal material whose main component is any of Ni, Ag, Cu, Au, Pt, Mo, Ti, Cr, and W.
  • the connecting conductor 15 may also be made of an alloy material whose main components are two or more selected from these metal materials.
  • connection conductor 15 are not particularly limited, and the size is set appropriately according to the size of the insulating substrate 10.
  • the connection conductor 15 is made of Ni and has a thickness of 200 nm.
  • the first external connection wiring which serves as the anode of the pair of external connection wirings, is composed of the first via conductor 13, the connection conductor 15, and the first bump 16.
  • the capacitance forming portion 20 is disposed opposite the first main surface 10a of the insulating substrate 10, and includes a conductive structure 21, a first dielectric film 22a covering the surface of the structure 21, and a conductive film 23 covering part of the surface of the first dielectric film 22a.
  • the outermost surface of the capacitance forming portion 20 has an uneven shape.
  • the structure 21 is uneven and is composed of multiple conductive pillars 21a standing upright from the first main surface 10a of the insulating substrate 10 via the connecting conductors 15.
  • the multiple pillars 21a are formed by a LIGA (Lithographie Galvanoformung Abformung) process that combines X-ray lithography and electroforming. Note that the method of forming the multiple pillars 21a is not particularly limited to this, and can be changed as appropriate.
  • LIGA Lithographie Galvanoformung Abformung
  • the structure 21 is located on the connection conductor 15 and is joined to the connection conductor 15. Therefore, the first external connection wiring serving as the anode described above is connected to the capacitance forming portion 20 via the connection conductor 15.
  • the pillars 21a constituting the structure 21 can be made of various conductive metal materials, but are preferably made of a metal material whose main component is any of Ni, Mo, W, Al, Ti, Ta, Nb, Cu, Pt, Au, and Ag.
  • the pillars 21a may also be made of an alloy material whose main components are two or more selected from these metal materials. In this embodiment, the pillars 21a are made of Ni.
  • the number and size of the pillars 21a constituting the structure 21 are not particularly limited, and are set appropriately according to the size of the insulating substrate 10.
  • the pillars 21a are generally cylindrical with a length of 500 ⁇ m or less and a diameter of 1 ⁇ m or more. Note that in FIG. 1(B), a total of 116 pillars 21a arranged in a staggered pattern are shown, and in FIG. 2, 11 of these pillars 21a are shown, but these numbers and arrangements are merely examples, and can be changed in various ways.
  • the first dielectric film 22a can be made of various insulating materials, for example, metal oxides such as AlOx , SiOx, HfOx , TiOx , TaOx, ZrOx , SiAlOx , HfAlOx , ZrAlOx , AlTiOx , SrTiOx , HfSiOx , ZrSiOx , TiZrOx , TiZrOx, TiZrWOx , SrTiOx , BaTiOx , PbTiOx , BaSrTiOx , BaCaTiOx , metal nitrides such as AlNx , SiNx , AlScNx , AlOxNy , SiOxNy , HfOxN It can be composed of metal oxynitrides such as SiC x O y N z .
  • metal oxides such as AlOx , SiO
  • the first dielectric film 22a with any of AlO x (for example, Al 2 O 3 ) , SiO x (for example, SiO 2 ), HfO x , TiO x , SiAlO x , HfAlO x , ZrAlO x , HfSiO x and ZrSiO x .
  • AlO x for example, Al 2 O 3
  • SiO x for example, SiO 2
  • HfO x TiO x
  • SiAlO x for example, SiO 2
  • HfO x TiO x
  • SiAlO x e.g., HfAlO x
  • ZrAlO x e.g., ZrAlO x
  • HfSiO x and ZrSiO x e.g., ZrSiO x
  • the above chemical formula simply shows the composition of the material and does not limit the composition. That is, x
  • the conductive film 23 covers a portion of the surface of the first dielectric film 22a.
  • the first dielectric film 22a has a non-exposed portion 221 that is covered by the conductive film 23 and an exposed portion 222 that is not covered by the conductive film 23.
  • the first dielectric film 22a except for the portion that defines the outer edge of the capacitance forming portion 20 in the direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in Figure 2), has its surface covered with the conductive film 23, thereby constituting a non-exposed portion 221.
  • the first dielectric film 22a except for the portion that defines the outer edge, has its surface not covered with the conductive film 23, thereby constituting an exposed portion 222.
  • the conductive film 23 can be made of various conductive materials, including metal materials mainly made of any of Ni, Cu, Ru, Al, W, Ti, Ag, Au, Zn, Ta, and Nb, alloy materials mainly made of two or more selected from these metal materials, metal nitrides such as TiN, TiAlN, TiSiN, TaN, NbN, and WN, metal oxynitrides such as TiON and TiAlON, conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)), polypyrrole, and polyaniline, and conductive oxide films such as RuO 2 , ZnO, (Zn,Al)O, and NiO.
  • the conductive film 23 is made of Ru.
  • the conductive film 23 can be preferably formed by CVD, ALD, PLD, plating, bias sputtering, sol-gel, a method using conductive polymer filling, or a method using supercritical fluid, and is particularly preferably formed by ALD.
  • the conductive film 23 may also be composed of a laminated film made up of multiple conductive layers made of different materials. In that case, the film can be formed by another method after being formed by ALD.
  • the thickness of the conductive film 23 is not particularly limited, but is preferably 3 nm or more, and more preferably 10 nm or more.
  • the extraction electrode 18 is positioned so as to cover the surface of the conductive film 23 in the portion covering the non-exposed portion 221 that covers the tip of the columnar body 21a.
  • the extraction electrode 18 does not cover the conductive film 23 in the portion other than the above-mentioned portion, nor the surface of the exposed portion 222.
  • the extraction electrode 18 constitutes part of the second external connection wiring described above.
  • the extraction electrode 18 can be made of various conductive materials, including metal materials whose main component is any of Ni, Cu, Al, Pt, Ti, and TiN, alloy materials whose main components are two or more selected from these metal materials, and metal nitrides such as TiN.
  • the extraction electrode 18 is made of either Cu or Ti.
  • the extraction electrode 18 is formed by, for example, sputtering, vacuum deposition, or CVD.
  • the sealing portion 30 is provided on the first main surface 10a of the insulating substrate 10, and seals the capacitance forming portion 20 together with the insulating substrate 10.
  • the sealing portion 30 defines an outer surface 30a located on the opposite side of the capacitance forming portion 20 from the insulating substrate 10. More specifically, the sealing portion 30 is located so as to cover a part of the upper part and the sides of the capacitance forming portion 20, which is provided so as to face the first main surface 10a of the insulating substrate 10, and the upper part and the sides of the extraction electrode 18.
  • the sealing portion 30 can be made of various insulating materials, but is preferably made of an insulating material having excellent weather resistance.
  • the material of the sealing portion 30 can be a resin material such as polyimide resin, polybenzoxazole resin, polyethylene terephthalate resin, benzocyclobutene resin, or epoxy resin.
  • the resin material can contain various additives, and may contain SiO2 filler, Al2O3 filler, or the like to adjust the thermal expansion coefficient.
  • the sealing portion 30 is made of epoxy resin.
  • a moisture-resistant protective film 40 may be formed between the capacitance forming portion 20 and the sealing portion 30.
  • the moisture-resistant protective film 40 can be formed, for example, before forming the sealing portion 30, by providing an inorganic insulator made of SiN, SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 or the like so as to cover the capacitance forming portion 20 by a CVD method, an ALD method or the like, or by providing an organic insulator having water repellency such as a fluorine-based resin or a silane coupling agent resin so as to cover the capacitance forming portion 20.
  • the moisture-resistant protective film 40 does not necessarily need to be formed up to the inside of the capacitance forming portion 20, and it is sufficient if it is formed so as to cover only the outer surface.
  • the sealing portion 30 can be formed by various coating methods, such as a method using a vacuum laminator, a method using an air dispenser, a method using a jet dispenser, a screen printing method, a vacuum printing method, an electrostatic coating method, an inkjet method, a photolithography method, etc.
  • the thickness and size of the sealing portion 30 are not particularly limited, and the size is set appropriately according to the size of the insulating substrate 10.
  • the thickness of the sealing portion 30 is preferably, for example, 5 ⁇ m or more and 50 ⁇ m or less, and the size is preferably such that it covers the entire first main surface 10a of the insulating substrate 10.
  • a second through hole 12 is provided on the outer surface 30a of the sealing portion 30.
  • the second through hole 12 penetrates the sealing portion 30 so as to reach from the outer surface 30a to the upper surface 18a of the extraction electrode 18.
  • the second through hole 12 is filled with a second via conductor 14.
  • the shape of the second via conductor 14 is, for example, approximately cylindrical.
  • the second via conductor 14 constitutes part of the second external connection wiring described above. When viewed along the normal direction of the first main surface 10a of the insulating substrate 10, the second via conductor 14 is provided within the region in which the capacitance forming portion 20 is arranged.
  • the second via conductor 14 can be made of various wiring materials, but is preferably made of a metal material with particularly high electrical conductivity.
  • the material of the second via conductor 14 can be, for example, a metal material whose main material is any of Ni, Ag, Cu, Au, Pt, Mo, and W.
  • the material of the second via conductor 14 can be changed as appropriate to suit the mounting environment of the capacitor 1A according to this embodiment.
  • the second via conductor 14 is made of Ni.
  • the axial length and size of the second via conductor 14 are not particularly limited, and are set appropriately according to the thickness and size of the sealing portion 30.
  • the axial length of the second via conductor 14 is preferably, for example, 5 ⁇ m or more and 75 ⁇ m or less, and the diameter is preferably, for example, 15 ⁇ m or more and 150 ⁇ m or less.
  • the second via conductor 14 is made of Ni, has an axial length of 75 ⁇ m, and a diameter of 150 ⁇ m.
  • a second bump 17 is provided on the outer surface 30a of the sealing portion 30 so as to cover the second via conductor 14.
  • the second bump 17 serves as a bonding material for mounting the capacitor 1A on a wiring board or the like, and for electrically connecting the capacitance forming portion 20 of the capacitor 1A to an external circuit.
  • the second bump 17 is provided so as to protrude from the outer surface 30a of the sealing portion 30.
  • the shape of the second bump 17 is approximately semispherical.
  • the second bump 17 constitutes part of the second external connection wiring described above.
  • the second bump 17 can be made of various wiring materials, but is preferably made of a metal material with particularly high electrical conductivity.
  • the material of the second bump 17 can be, for example, a metal material whose main component is any of Ni, Ag, Cu, Au, and Sn.
  • the second bump 17 is made of Au.
  • the size of the second bump 17 is not particularly limited and is set appropriately according to the size of the second via conductor 14.
  • the second external connection wiring which serves as the cathode of the pair of external connection wirings, is composed of the extraction electrode 18, the second via conductor 14, and the second bump 17. Furthermore, the second external connection wiring thus configured is located inside the outer edge of the capacitance forming portion 20 in a direction parallel to the first main surface 10a of the insulating substrate 10. This makes it possible to improve the reliability of the capacitor 1A after mounting, the details of which will be described later.
  • the capacitance forming portion 20 consisting of the conductive structure 21, the first dielectric film 22a, and the conductive film 23 is sealed by the insulating substrate 10 and the sealing portion 30, and the electrical connection of the capacitance forming portion 20 is realized by a pair of external connection wiring.
  • FIG. 4 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment.
  • FIGS. 5 to 16 are schematic cross-sectional views for explaining each step of the manufacturing flow shown in FIG. 4. Next, an example of a specific manufacturing method for manufacturing the capacitor 1A according to this embodiment described above will be described with reference to FIGS. 4 to 16.
  • the manufacturing method of capacitor 1A shown below is a method in which an assembly of in-process capacitors is produced by performing processing all at once up to a mid-point in the manufacturing process, the assembly is then cut into individual pieces, and the individual pieces are further processed to mass-produce multiple capacitors 1A simultaneously.
  • step S1 a green sheet is produced.
  • Al2O3 powder and glass powder are weighed, and these Al2O3 powder and glass powder are mixed with an organic solvent such as toluene or ethanol, and a binder such as polyvinyl butyral. Then, this mixture is formed into a sheet, and a green sheet that is the base of an insulating substrate is produced. After the green sheet is produced, it is cut to prepare a plurality of green sheets.
  • step S2 first through holes are formed in some of the green sheets.
  • first through holes 11 are provided at predetermined positions in the green sheets, and the first through holes 11 will be filled later with first via conductors that are part of the anode.
  • the method of forming the first through holes 11 is not particularly limited, but for example, the first through holes 11 can be formed by irradiating the green sheet with laser light.
  • the first through holes 11 may also be formed by processing using a mechanical puncher or sandblasting.
  • step S3 a first via conductor is formed in the green sheet in which the first through hole is formed.
  • a conductive paste is applied to the green sheet so as to fill the first through hole 11.
  • the method for applying the conductive paste is not particularly limited, but for example, screen printing can be used.
  • step S4 the green sheets are fired.
  • a green sheet that does not have a first through hole is superimposed on the green sheet to which the conductive paste has been applied in step S3, and these superimposed green sheets are pressed together.
  • the laminate of green sheets after this pressing is then degreased, and the laminate of green sheets after the degreased process is fired.
  • a green sheet that does not have the first through holes 11 is stacked on the other main surface opposite the one main surface of the green sheet on which the conductive paste is applied.
  • a uniaxial press can be used, for example, to press the green sheets together.
  • the green sheets are fired, for example, in the air, at temperatures of 700°C to 1000°C.
  • the insulating substrate in question is a so-called multi-substrate in which insulating substrates that will ultimately be included in each of a number of capacitors are connected in a matrix form, but in FIG. 5, attention is focused on only one of these insulating substrates, 10, and its surrounding area is omitted and shown with dashed lines.
  • the first via conductor 13 may be provided after firing an insulating substrate that does not have through holes or the like.
  • the first through holes 11 may be provided in the fired insulating substrate by, for example, sandblasting, wet etching, dry etching, or the like, and then the conductive paste may be applied and fired.
  • the first via conductor 13 may be formed by sputtering, vapor deposition, plating, or the like.
  • step S5 a connection conductor is formed to cover one of the pair of main surfaces of the insulating substrate. More specifically, a conductive paste is applied onto the first main surface 10a, which is one of the main surfaces of the insulating substrate 10.
  • the method for applying the conductive paste is not particularly limited, but for example, screen printing can be used.
  • a mold for forming a structure is formed to be used for forming the structure.
  • a mold for forming a structure 101 is formed on one of the pair of main surfaces of the connection conductor 15 that is located on the side opposite the insulating substrate 10 as viewed from the connection conductor 15.
  • the mold 101 for forming a structure is formed through the following procedure. First, X-rays are irradiated through an X-ray mask toward the photosensitive resin. Next, the photosensitive resin irradiated with X-rays is developed. As a result, only the photosensitive resin exposed to X-rays remains selectively, forming a microstructure. Note that the photosensitive resin used here is not limited to the so-called negative photosensitive resin in which the parts exposed to X-rays remain selectively as described above, but may be a so-called positive photosensitive resin in which the parts exposed to X-rays selectively dissolve.
  • the microstructure formed in the above manner has an overall shape of a roughly rectangular parallelepiped.
  • the microstructure has a plurality of pores 102 that penetrate the microstructure so as to reach from one of the pair of main surfaces to the other.
  • the pores 102 have a uniform diameter of microns.
  • This microstructure constitutes the mold 101 for forming a structure.
  • step S7 a number of conductive pillars that constitute the structure are formed. More specifically, pillars 21a are formed so as to fill a number of pores 102 provided in the structure-forming mold 101. The formed pillars 21a are joined at their lower parts to the connection conductor 15. The pillars 21a can be formed, for example, by electrolytic plating.
  • step S8 the mold for forming the structure is peeled off.
  • electroplating is performed on the mold, and the mold is peeled off from the electrodeposit formed thereby (so-called electrocasting), so that the structure 21, which is composed of multiple columns 21a and has an overall uneven shape, is exposed on the first main surface 10a of the insulating substrate 10.
  • a first dielectric film is formed.
  • a first dielectric film 22a is formed so as to cover the surfaces of the connection conductor 15 and the structure 21.
  • the method for forming the first dielectric film 22a is not particularly limited, but preferably the ALD method is used. If the ALD method is used, the raw material for the first dielectric film 22a can be supplied as a gas, making it possible to select the material and adjust the film thickness at the atomic layer level.
  • the first dielectric film 22a is formed using this ALD method, it is preferable to use a source gas that has a high vapor pressure, is easy to gasify, has high thermal stability, and is highly reactive. From this viewpoint, for example, when forming an AlO x film, it is preferable to use TMA (trimethylaluminum) as the source, and when forming a SiO x film, it is preferable to use TDMAS (trisdimethylaminosilane) as the source. In this embodiment, the first dielectric film 22a is formed using the ALD method.
  • TMA trimethylaluminum
  • TDMAS trisdimethylaminosilane
  • the first dielectric film 22a is formed at a temperature of, for example, 150°C or higher and 400°C or lower, although this varies depending on the film formation method and film formation material.
  • step S10 a conductive film is formed. More specifically, a conductive film 23 is formed so as to cover the first dielectric film 22a formed in step S9.
  • the method for forming the conductive film 23 is not particularly limited, but preferably the ALD method is used.
  • the raw material for the conductive film 23 can be supplied as a gas, which makes it possible to select the material and adjust the film thickness at the atomic layer level.
  • the conductive film 23 is formed at a temperature condition of, for example, 150°C or higher and 600°C or lower, although this varies depending on the film formation method and film formation material.
  • a capacitance forming portion 20 is formed on the first main surface 10a of the insulating substrate 10, the capacitance forming portion 20 being made of a conductive structure 21, a first dielectric film 22a, and a conductive film 23 and having an uneven outermost surface.
  • an extraction electrode is formed. More specifically, an extraction electrode 18 is formed so as to cover the surface of the conductive film 23 formed in step S10 except for the portion that defines the bottom side of the concave portion of the capacitance forming portion 20.
  • the method for forming the extraction electrode 18 is not particularly limited, but preferably a sputtering method is used. By using a sputtering method, the time required to form the extraction electrode 18 can be shortened compared to other formation methods.
  • a resist film is formed. More specifically, a resist film 24 is formed so as to cover the lead-out electrode 18 in a portion that covers the conductive film 23 other than the portion that defines the outer edge portion of the capacitance forming portion 20 in a direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in Figure 12).
  • the method for forming the resist film 24 is not particularly limited to this.
  • a photosensitive liquid resist is evenly applied to a predetermined surface of the extraction electrode 18 by spin coating, and this is locally exposed to light using a photomask.
  • unnecessary photosensitive liquid resist is removed by immersing in a developer, and the remaining photosensitive liquid resist is dried in an oven or the like, thereby forming the resist film 24.
  • step S13 a part of the conductive film and a part of the extraction electrode are removed. More specifically, the part of the extraction electrode 18 that is not covered by the resist film 24 formed in step S12 and the corresponding part of the conductive film 23 are removed. Examples of the removal method include wet etching, dry etching, and atomic layer etching (ALE), etc.
  • ALE atomic layer etching
  • the first dielectric film 22a has a non-exposed portion 221 that is covered by the conductive film 23 and an exposed portion 222 that is not covered by the conductive film 23.
  • step S14 the resist film is removed by being peeled off. More specifically, the resist film 24 is peeled off using a stripping solution or the like.
  • a sealing portion is formed. More specifically, a sealing portion 30 is provided on the first main surface 10a of the insulating substrate 10 on which the capacitance forming portion 20 is provided, so as to cover the capacitance forming portion 20 and the extraction electrode 18.
  • the sealing portion 30 is formed, for example, by so-called compression molding. More specifically, a resin sheet is placed on the first main surface 10a of the insulating substrate 10, and in this state, a vacuum laminator is used to draw a vacuum, thereby adhering the resin sheet to the first main surface 10a of the insulating substrate 10. In this state, the resin sheet is then heated to 50°C to 100°C to laminate the capacitance forming portion 20, and then further heated to 100°C to 200°C to fully harden, thereby forming the sealing portion 30. Note that the method of forming the sealing portion 30 is not limited to the above-mentioned compression molding, and may also be performed by so-called transfer molding.
  • the capacitance forming portion 20 and the extraction electrode 18 are sealed by the insulating substrate 10 and the sealing portion 30, preventing moisture from entering the capacitance forming portion 20 and the extraction electrode 18 from the outside and ensuring moisture resistance.
  • the capacitance forming portion 20 is covered by the sealing portion 30, and the capacitance forming portion 20 is physically protected by the sealing portion 30. Note that the curing conditions shown above are merely examples and can be changed in various ways.
  • step S16 a second via conductor is formed in the sealing portion.
  • a second through hole 12 is formed in the sealing portion 30 so as to reach from the outer surface 30a to the upper surface 18a of the extraction electrode 18.
  • a second via conductor 14 is formed so as to fill the second through hole 12.
  • the second via conductor 14 can be formed, for example, by electrolytic plating.
  • the portion other than the second through hole 12 is covered with an ultraviolet-curable resin film serving as a mask (not shown), and electrolytic plating is performed in this state, so that only the inside of the second through hole 12 can be covered with a plating film.
  • the ultraviolet-curable resin film serving as a mask is removed.
  • the second via conductor 14 thus formed is joined to the extraction electrode 18 at its end face on the capacitance forming portion 20 side. As a result, the second via conductor 14 is connected to the capacitance forming portion 20 via the extraction electrode 18.
  • step S17 the insulating substrate is ground and then singulated.
  • the second main surface 10b of the insulating substrate 10, which is located opposite the side on which the sealing portion 30 is provided, is planar cut, and then the insulating substrate 10 is cut into individual capacitors 1A that are connected to each other.
  • a grinding tape (not shown) is applied to the sealing portion 30, and the insulating substrate 10 in the portion that blocks the first via conductor 13 is removed by flat cutting. This causes the end of the first via conductor 13 to be exposed on the second main surface 10b.
  • a groove is formed in the insulating substrate 10, and force is applied to the insulating substrate 10 so as to bend it from the groove, thereby breaking the insulating substrate 10.
  • Methods for forming the groove include diamond scribing, laser scribing, dicing, etc. Also, singulation may be performed by directly cutting the insulating substrate 10 and the sealing portion 30 by scribing or dicing.
  • a first bump is formed on the insulating substrate, and a second bump is formed on the sealing portion. More specifically, as shown in FIG. 2, a first bump 16 is formed on the second main surface 10b of the insulating substrate 10 so as to cover the first via conductor 13 provided in the insulating substrate 10. In addition, a second bump 17 is formed on the outer surface 30a of the sealing portion 30 so as to cover the second via conductor 14 provided in the sealing portion 30.
  • the first bump 16 can be formed, for example, by electrolytic plating.
  • the area other than the area near the exposed first via conductor 13 is covered with an ultraviolet-curable resin film (not shown) as a mask, and electrolytic plating is performed in this state, making it possible to form the first bump 16 so as to protrude from the second main surface 10b.
  • the ultraviolet-curable resin film as a mask is removed. The same applies to the formation of the second bump 17.
  • the method of forming the second via conductor 14, the first bump 16, and the second bump 17 described above can be not only the method using electrolytic plating described above, but also a combination of a screen printing method, an inkjet method, a dispenser method, etc. using a conductive paste and sintering.
  • the conductive paste contains a metal or sintering aid that can be sintered at a low temperature so that sintering can be performed under temperature conditions that do not affect the resin that constitutes the sealing portion 30.
  • the capacitor 1A according to the above-mentioned embodiment 1 is manufactured.
  • a capacitor having a capacitance forming portion 20 with an uneven outermost surface such as capacitor 1A according to this embodiment, damage such as cracks may occur in the outer edge of capacitance forming portion 20 in a direction parallel to first main surface 10a of insulating substrate 10. Therefore, if the capacitance forming portion 20 is structured to actively draw electrical current from this outer edge, a short circuit may occur in the damaged portion, resulting in a loss of functionality of capacitor 1A.
  • the first dielectric film 22a as a dielectric film, other than the portion defining the outer edge portion, constitutes the non-exposed portion 221 whose surface is covered by the conductive film 23. Also, the portion of the first dielectric film 22a that defines the outer edge portion constitutes the exposed portion 222 whose surface is not covered by the conductive film 23.
  • the surface of the capacitance forming portion 20 other than the outer edge portion has a so-called MIM (Metal Insulator Metal) structure
  • MIM Metal Insulator Metal
  • MI Metal Insulator
  • capacitor 1A the reliability of the capacitor after mounting is improved, since the capacitor has a capacitance forming portion made of a conductive structure, a dielectric film, and a conductive film.
  • the second external connection wiring constituted by the extraction electrode 18 and the like is located inside the outer edge of the capacitance forming portion 20 in the direction parallel to the first main surface 10a of the insulating substrate 10. Therefore, the extraction electrode 18 covers a part of the surface of the conductive film 23 in the portion that covers the non-exposed portion 221, thereby being electrically connected thereto, while being located so as not to cover the surface of the exposed portion 222.
  • the first via conductor 13 and the second via conductor 14 are both provided within the area in which the capacitance forming portion 20 is arranged.
  • neither the first external connection wiring nor the second external connection wiring is positioned to the side of the capacitance forming portion 20, so the sealing portion 30 in the portion positioned to the side of the capacitance forming portion 20 can be minimized.
  • the capacitor 1A be configured to be smaller than conventional capacitors, but the volume occupied by the portions of the capacitor 1A other than the capacitance forming portion 20 is reduced, resulting in a higher capacitance.
  • the extraction electrode 18 is formed to cover the surface of the conductive film 23 in a portion other than the portion that defines the bottom side of the concave portion of the capacitance forming portion 20, in other words, the case where the surface of the conductive film 23 in the portion that defines the bottom side of the concave portion of the capacitance forming portion 20 is not covered has been described as an example, but the extraction electrode 18 may also be formed to cover the surface of the conductive film 23 in the portion that defines the bottom side of the concave portion of the capacitance forming portion 20. In this case, the extraction electrode 18 can be formed by, for example, a CVD method or an ALD method.
  • (First Modification) 17 is a schematic cross-sectional view of a capacitor according to a first modified example.
  • a capacitor 1A1 according to a first modified example based on the above-mentioned first embodiment will be described with reference to FIG.
  • the capacitor 1A1 of the first modified example differs from the capacitor 1A of the first embodiment described above in the configuration of the first external connection wiring.
  • the first external connection wiring electrically leads out the capacitance forming portion 20 from the outer surface 30a side of the sealing portion 30, similar to the second external connection wiring.
  • the first through hole 11 is formed in the sealing portion 30 so as to reach from the outer surface 30a of the sealing portion 30 to the upper surface of the connection conductor 15.
  • the first via conductor 13 is formed so as to fill the first through hole 11.
  • the first bump 16 is formed on the outer surface 30a of the sealing portion 30 so as to cover the first via conductor 13 provided in the sealing portion 30.
  • the first via conductor 13 and the second via conductor 14 are positioned so as to penetrate the sealing portion 30 in its thickness direction, so that these via conductors with different polarities are arranged close to each other with their current paths facing in opposite directions. Therefore, the magnetic fields generated in these via conductors by the flow of current act to cancel each other out, so that the so-called ESL (equivalent series inductance) can be reduced.
  • ESL equivalent series inductance
  • the remaining steps of the capacitor 1A1 according to the first modified example can be basically manufactured according to the manufacturing method of the capacitor 1A according to the first embodiment described above.
  • capacitor 1A1 in the cross section of capacitor 1A1 shown in FIG. 17, two first external connection wirings are shown positioned to sandwich capacitance forming portion 20, but the arrangement of the first external connection wirings when capacitor 1A1 is viewed in a plan view is not particularly limited to this and can be changed as appropriate.
  • (Second Modification) 18 is a schematic cross-sectional view of a capacitor according to a second modified example.
  • a capacitor 1A2 according to the second modified example based on the above-described first embodiment will now be described with reference to FIG.
  • the capacitor 1A2 of the second modified example differs from the capacitor 1A of the first embodiment described above in the configuration of the second external connection wiring.
  • the capacitance forming portion 20 is electrically connected by the second external connection wiring from the second main surface 10b side of the insulating substrate 10, in the same manner as the first external connection wiring.
  • the second through hole 12 is formed in the insulating substrate 10, the connection conductor 15, and the capacitance forming portion 20 so as to reach from the second main surface 10b of the insulating substrate 10 to the underside of the extraction electrode 18.
  • the second via conductor 14 is formed so as to fill the second through hole 12.
  • the second via conductor 14 is connected to the capacitance forming portion 20 via the extraction electrode 18.
  • the second bump 17 is formed on the second main surface 10b of the insulating substrate 10 so as to cover the second via conductor 14 provided on the insulating substrate 10.
  • the first dielectric film 22a and the conductive film 23 cover not only the surface of the structure 21, but also the surfaces of the insulating substrate 10 and the connecting conductor 15 in the portion that defines the second through hole 12. More specifically, at the boundary between the second via conductor 14 and the base material of the insulating substrate 10, the base material of the insulating substrate 10 is covered by the first dielectric film 22a, and the first dielectric film 22a is covered by the conductive film 23, which is further covered by the second via conductor 14. Similarly, at the boundary between the extraction electrode 18 and the connecting conductor 15, the connecting conductor 15 is covered by the first dielectric film 22a, and the first dielectric film 22a is covered by the conductive film 23, which is further covered by the extraction electrode 18.
  • the first via conductor 13 and the second via conductor 14 are positioned so as to penetrate the insulating substrate 10 in its thickness direction, so that these via conductors with opposite polarity are arranged close to each other with their current paths facing in opposite directions. Therefore, the magnetic fields generated in these via conductors by the flow of current act to cancel each other out, making it possible to reduce the ESL.
  • the capacitor 1A2 according to the second modified example can be manufactured by, for example, forming the second through hole 12 described above between the formation of the mold 101 for forming the structure and the formation of the first dielectric film 22a (i.e., between steps S8 and S9), and forming the second via conductor 14 described above between the grinding of the insulating substrate 10 and the formation of the second bump 17 (i.e., between steps S17 and S18), with the remaining steps basically following the manufacturing method of the capacitor 1A according to the first embodiment described above.
  • FIG. 19 is a schematic cross-sectional view of a capacitor according to embodiment 2.
  • Fig. 20(A) and Fig. 20(B) are enlarged cross-sectional views of essential parts of regions XXA and XXB, respectively, of the capacitance forming portion shown in Fig. 19.
  • a capacitor 1B according to the present embodiment will be described with reference to Figs. 19 and 20.
  • the capacitor 1B of this embodiment differs from the capacitor 1A of the above-described first embodiment in the configuration of the capacitance forming portion 20B.
  • the capacitance forming portion 20B has a conductive structure 21, a dielectric film including a first dielectric film 22a, a second dielectric film 22b and a third dielectric film 22c, and a conductive film 23B.
  • the first dielectric film 22a covers the surface of the structure 21.
  • the second dielectric film 22b covers the entire surface of the first dielectric film 22a.
  • the third dielectric film 22c and the conductive film 23B each cover a portion of the surface of the second dielectric film 22b.
  • the second dielectric film 22b is a so-called adhesive film having adhesiveness to the conductive film 23B.
  • the second dielectric film 22b may be made of an ionic material, and may be made of, for example, metal oxides such as HfO x , TiO x , and YO x , or metal nitrides such as TiN x . Among them, it is preferable to make the second dielectric film 22b of any of HfO 2 , Y 2 O 3 , TiO 2 , and TiN.
  • the above chemical formula simply indicates the composition of the material, and does not limit the composition. That is, x added to O and N may be any value greater than 0, and the abundance ratio of each element including the metal element is arbitrary.
  • the second dielectric film 22b may be made of a laminated film made of a plurality of dielectric layers made of different materials. In this embodiment, the second dielectric film 22b is made of TiO 2 .
  • the second dielectric film 22b can be preferably formed by a gas phase method such as vacuum deposition, CVD, sputtering, ALD, PLD, or a method using a supercritical fluid, and is particularly preferably formed by the ALD method.
  • a gas phase method such as vacuum deposition, CVD, sputtering, ALD, PLD, or a method using a supercritical fluid, and is particularly preferably formed by the ALD method.
  • the thickness of the second dielectric film 22b is not particularly limited, but is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less.
  • the third dielectric film 22c covers a portion of the surface of the second dielectric film 22b. More specifically, the third dielectric film 22c covers the surface of a portion of the second dielectric film 22b that defines the outer edge in a direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 19) and the surface of a portion that corresponds to the tip of the columnar body 21a.
  • the third dielectric film 22c is a so-called inhibiting film that does not have adhesion to the conductive film 23B.
  • the third dielectric film 22c can be made of, for example, metal oxides such as AlO x and SiO x , or SiC.
  • the above chemical formula simply indicates the composition of the material, and does not limit the composition. That is, x attached to O may be any value greater than 0, and the abundance ratio of each element including the metal element is arbitrary.
  • the third dielectric film 22c may be made of a laminated film made of multiple dielectric layers made of different materials. In this embodiment, the third dielectric film 22c is made of SiO 2 .
  • the third dielectric film 22c can be preferably formed by a gas phase method such as vacuum deposition, CVD, sputtering, ALD, PLD, or a method using a supercritical fluid, and is particularly preferably formed by the ALD method.
  • a gas phase method such as vacuum deposition, CVD, sputtering, ALD, PLD, or a method using a supercritical fluid, and is particularly preferably formed by the ALD method.
  • the thickness of the third dielectric film 22c is not particularly limited, but is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less.
  • the conductive film 23B covers a portion of the surface of the second dielectric film 22b.
  • the conductive film 23B covers the surface of the portion of the second dielectric film 22b that is not covered by the third dielectric film 22c.
  • the conductive film 23B selectively covers only the surface of the second dielectric film 22b.
  • the conductive film 23B has undercoat dependency on the second dielectric film 22b.
  • the conductive film 23B is made of Ru.
  • the cycle until film formation is shorter than when the film is formed on a non-ionic material.
  • the conductive film 23B made of Ru is made to have base dependence with respect to the second dielectric film 22b made of an ionic material.
  • the dielectric film has a non-exposed portion 221B that is covered by the conductive film 23B, and an exposed portion 222B that is not covered by the conductive film 23B.
  • the portion of the second dielectric film 22b that is not covered by the third dielectric film 22c i.e., the portion of the second dielectric film 22b excluding the portion that defines the outer edge in the direction parallel to the first main surface 10a of the insulating substrate 10 and the portion that corresponds to the tip of the columnar body 21a
  • the first dielectric film 22a and the second dielectric film 22b form the non-exposed portion 221B.
  • the portion of the second dielectric film 22b that is covered by the third dielectric film 22c does not have its surface covered by the conductive film 23B.
  • the first dielectric film 22a, the second dielectric film 22b and the third dielectric film 22c form the exposed portion 222B.
  • the outer edge of the capacitance forming portion 20B in the direction parallel to the first main surface 10a is defined by the exposed portion 222B composed of the first dielectric film 22a, the second dielectric film 22b, and the third dielectric film 22c. Therefore, the outer edge of the surface of the capacitance forming portion 20B has an MI structure.
  • FIG. 21 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment
  • FIGS. 22 to 24 are schematic cross-sectional views for explaining each step of the manufacturing flow shown in FIG. 21.
  • the manufacturing method of capacitor 1B is largely similar to the manufacturing method of capacitor 1A. Therefore, in the following, we will omit the explanation of the steps in the manufacturing method of capacitor 1B that are common to the manufacturing method of capacitor 1A, and will only explain the steps that are different from the manufacturing method of capacitor 1A.
  • a second dielectric film is formed in step S9B1. More specifically, a second dielectric film 22b is formed so as to cover the entire surface of the first dielectric film 22a.
  • a third dielectric film is formed. More specifically, a third dielectric film 22c is formed so as to cover the surface of a portion of the second dielectric film 22b that defines the outer edge in a direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in Figure 23) and the surface of a portion that corresponds to the tip of the columnar body 21a.
  • the method for forming the third dielectric film 22c and the second dielectric film 22b described above is not particularly limited, but preferably, the ALD method is used. If the ALD method is used, the raw materials for the second dielectric film 22b and the third dielectric film 22c can be supplied as gas, making it possible to select the material and adjust the film thickness at the atomic layer level.
  • this ALD method When using this ALD method to form the second dielectric film 22b, it is preferable to use a source gas that has a high vapor pressure and is easy to gasify, as well as high thermal stability and high reactivity.
  • the second dielectric film 22b and the third dielectric film 22c are formed at a temperature of, for example, 150°C or higher and 400°C or lower, although this varies depending on the film formation method and film formation material.
  • a conductive film is formed. More specifically, conductive film 23B is formed so as to cover the surface of the portion of second dielectric film 22b formed in step S9B1 that is not covered by third dielectric film 22c. This is because second dielectric film 22b has adhesion to conductive film 23B, while third dielectric film 22c does not have adhesion to conductive film 23B, and conductive film 23B has undercoat dependency on second dielectric film 22b.
  • a capacitance forming portion 20B is formed on the first main surface 10a of the insulating substrate 10, the capacitance forming portion 20B being made up of a conductive structure 21, a first dielectric film 22a, a second dielectric film 22b, a third dielectric film 22c, and a conductive film 23B and having an uneven outermost surface.
  • the capacitor 1B according to the above-mentioned embodiment 2 is manufactured by going through all steps S1 to S11, steps S15 to S18, and steps S9B1 and S9B2, including the steps described individually above.
  • the capacitor 1B according to this embodiment configured in this way also has the same effect as that described in the first embodiment, and the reliability after mounting is improved in a capacitor having a capacitance forming portion made of a conductive structure, a dielectric film, and a conductive film.
  • FIG. 25 is a schematic cross-sectional view of a capacitor according to embodiment 3.
  • Fig. 26(A) and Fig. 26(B) are enlarged cross-sectional views of essential parts of regions XXVIA and XXVIB, respectively, of the capacitance forming portion shown in Fig. 25.
  • a capacitor 1C according to this embodiment will be described with reference to Figs. 25 and 26.
  • the capacitor 1C of this embodiment differs from the capacitor 1A of the above-described first embodiment in the configuration of the capacitance forming portion 20C.
  • the capacitance forming portion 20C has a conductive structure 21, a dielectric film including a first dielectric film 22a and a second dielectric film 22b, and a conductive film 23C.
  • the conductive film 23C has undercoat dependency with respect to the second dielectric film 22b, similar to the conductive film 23B in the second embodiment described above.
  • the first dielectric film 22a covers the surface of the structure 21.
  • the second dielectric film 22b covers a portion of the surface of the first dielectric film 22a. More specifically, the second dielectric film 22b covers the surface of the first dielectric film 22a except for the portions that define the outer edge portion in the direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 25).
  • the conductive film 23C covers the entire surface of the second dielectric film 22b.
  • the dielectric film has a non-exposed portion 221C that is covered by the conductive film 23C, and an exposed portion 222C that is not covered by the conductive film 23C.
  • the entire surface of the second dielectric film 22b is covered with a conductive film 23C.
  • the first dielectric film 22a and the second dielectric film 22b form a non-exposed portion 221C.
  • the portion of the first dielectric film 22a that is covered by the second dielectric film 22b does not have its surface covered by the conductive film 23B.
  • the first dielectric film 22a forms an exposed portion 222C.
  • the outer edge of the capacitance forming portion 20C in a direction parallel to the first main surface 10a is defined by the exposed portion 222C formed by the first dielectric film 22a. Therefore, the outer edge of the surface of the capacitance forming portion 20C has an MI structure.
  • FIG. 27 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment
  • FIGS. 28 to 31 are schematic cross-sectional views for explaining each step of the manufacturing flow shown in FIG. 27.
  • the manufacturing method of capacitor 1C is largely similar to the manufacturing method of capacitor 1A. Therefore, in the following, we will omit the explanation of the steps in the manufacturing method of capacitor 1C that are common to the manufacturing method of capacitor 1A, and will only explain the steps that are different from the manufacturing method of capacitor 1A.
  • a resist film is formed in step S12. More specifically, a resist film 24 is formed so as to cover the surface of the portion of the first dielectric film 22a that defines the outer edge in the direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in Figure 28).
  • a second dielectric film is formed. More specifically, a second dielectric film 22b is formed so as to cover the surface of the resist film 24 and the surface of the portion of the first dielectric film 22a that is not covered by the resist film 24C.
  • step S14 the resist film is peeled off. More specifically, the resist film 24 is removed by being peeled off together with the second dielectric film 22b that covers its surface.
  • a conductive film is formed. More specifically, a conductive film 23C is formed so as to cover the surface of the second dielectric film 22b remaining on the surface of the first dielectric film 22a after the resist film 24 is peeled off in step S14. This is because the second dielectric film 22b has adhesion to the conductive film 23C, and the conductive film 23C has undercoat dependency on the second dielectric film 22b.
  • a capacitance forming portion 20C consisting of a conductive structure 21, a first dielectric film 22a, a second dielectric film 22b, and a conductive film 23C and having an uneven outermost surface is formed on the first main surface 10a of the insulating substrate 10, as shown in FIG. 25.
  • the capacitor 1C according to the above-mentioned embodiment 3 is manufactured by going through all steps S1 to S12, steps S14 to S18, and step S9B1, including the steps described individually above.
  • the capacitor 1C according to this embodiment which is configured in this manner, also provides the same effects as those described in the first embodiment above, and improves the reliability after mounting in a capacitor that has a capacitance forming portion made of a conductive structure, a dielectric film, and a conductive film.
  • FIG. 32 is a schematic cross-sectional view of a capacitor according to embodiment 4.
  • Figs. 33(A) and 33(B) are enlarged cross-sectional views of essential parts of regions XXXIIIA and XXXIIIB, respectively, of the capacitance forming portion shown in Fig. 32.
  • a capacitor 1D according to the present embodiment will be described with reference to Figs. 32 and 33.
  • the capacitor 1D of this embodiment differs from the capacitor 1A of the above-described first embodiment in the configuration of the capacitance forming portion 20D.
  • the capacitance forming portion 20D has a conductive structure 21D, a first dielectric film 22aD as a dielectric film, and a conductive film 23D.
  • the structure 21D is provided on the first main surface 10a of the insulating substrate 10 via the connecting conductor 15, and is porous and made of a conductive metal porous body 21b having multiple fine holes inside.
  • the porous metal body 21b has a plurality of fine holes formed therein, at least some of which are not closed by the porous metal body itself, and preferably a majority or all of the plurality of fine holes formed therein are not closed by the porous metal body itself.
  • a porous metal body is formed, for example, of a sintered body of metal particles.
  • the metal porous body 21b is located on the first main surface 10a of the insulating substrate 10 except for the edge portion. As a result, the metal porous body 21b is also located on the connection conductor 15 provided on the first main surface 10a, and is joined to the connection conductor 15. Therefore, the first external connection wiring serving as the anode described above is connected to the capacitance forming portion 20D via the connection conductor 15.
  • the metal porous body 21b can be made of various conductive metal materials, but it is preferable to make it of a metal material whose main component is any of Ni, Mo, W, Al, Ti, Ta, Nb, Cu, Pt, Au, and Ag.
  • the metal porous body 21b may also be made of an alloy material whose main components are two or more selected from these metal materials.
  • the thickness and size of the metal porous body 21b are not particularly limited, and the size is set appropriately according to the size of the insulating substrate 10.
  • the metal porous body 21b is made of Ni and has a thickness of 0.2 mm.
  • the metal porous body 21b is preferably composed of a sintered body of metal particles.
  • the metal particles may be of various shapes, such as spherical, elliptical, flat, plate-like, and needle-like.
  • the particle size of the metal particles is not particularly limited, but the average particle size is preferably 600 nm or less, and more preferably 20 nm or more and 500 nm or less.
  • the first dielectric film 22aD not only covers the surface of the metal porous body 21b in the portion located on the outermost side of the capacitance forming portion 20D, but also covers the surface of the metal porous body 21b in the portion located inside the capacitance forming portion 20D that is defined by the above-mentioned fine pores that are not closed by the metal porous body itself.
  • the conductive film 23D covers the surface of the first dielectric film 22aD except for the portion that defines the outer edge of the capacitance forming portion 20D in the direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 32).
  • the first dielectric film 22aD has a non-exposed portion 221D that is covered by the conductive film 23D and an exposed portion 222D that is not covered by the conductive film 23D.
  • the first dielectric film 22aD has a surface that is not covered by the conductive film 23D, except for the portion that defines the outer edge of the capacitance forming portion 20D in the direction parallel to the first main surface 10a of the insulating substrate 10, and thereby constitutes a non-exposed portion 221D.
  • the first dielectric film 22aD has a surface that is not covered by the conductive film 23D, and thereby constitutes an exposed portion 222D.
  • the outer edge of the capacitance forming portion 20D in a direction parallel to the first main surface 10a is defined by the exposed portion 222D formed by the first dielectric film 22aD. Therefore, the outer edge of the surface of the capacitance forming portion 20D has an MI structure.
  • FIG. 34 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment
  • FIGS. 35 and 36 are schematic cross-sectional views for explaining each step of the manufacturing flow shown in FIG. 34.
  • the manufacturing method of capacitor 1D is largely similar to the manufacturing method of capacitor 1A. Therefore, in the following, we will omit the explanation of the steps in the manufacturing method of capacitor 1D that are common to the manufacturing method of capacitor 1A, and will only explain the steps that are different from the manufacturing method of capacitor 1A.
  • the manufacturing method of capacitor 1D differs from the manufacturing method of capacitor 1A (see Figure 4, etc.) in that step S5D is performed instead of steps S6 to S8.
  • step S5D As shown in FIG. 34 and FIG. 36.
  • conductive metal particles, an organic solvent such as terpineol, and an ethyl cellulose varnish are weighed and mixed, and a conductive paste is made from the mixture using a rolling machine.
  • the conductive paste made in this way is applied to the first main surface 10a of the insulating substrate 10 and dried.
  • the conductive paste is applied in multiple layers, so that it has a predetermined thickness and is applied onto the insulating substrate 10 so that it has a rectangular pattern shape as a whole when viewed from above.
  • Each piece of conductive paste applied onto the insulating substrate 10 becomes the metal porous body 21b described above.
  • the insulating substrate 10 after applying the conductive paste is degreased, and then the conductive paste is fired at temperatures between 400°C and 900°C in a reducing atmosphere, for example, a mixture of nitrogen and hydrogen.
  • a reducing atmosphere for example, a mixture of nitrogen and hydrogen.
  • the atmosphere can be set to an equilibrium oxygen partial pressure or lower for the metal selected as the main component of the metal porous body 21b.
  • the steps after the metal porous body 21b is formed in this manner are essentially the same as steps S9 to S18 in the manufacturing method of the capacitor 1A. Through these steps, the capacitor 1D according to the above-mentioned embodiment 4 is manufactured.
  • the metal porous body 21b is composed of a sintered body of metal particles.
  • the metal particles are metallically bonded to each other, improving the mechanical strength of the capacitance forming portion 20D, and the bonding area between the metal particles is also increased. This makes it possible to achieve a so-called low ESR (equivalent series resistance). Furthermore, there is also the effect that a metal porous body having open pores can be formed relatively easily.
  • capacitor 1D according to this embodiment with the characteristic configuration shown in capacitor 1A1 according to the first modified example based on embodiment 1 described above, in which the capacitance forming portion is electrically led out by the first external connection wiring from the outer surface side of the sealed portion in the same manner as the second external connection wiring. It is also of course possible to combine capacitor 1D with the characteristic configuration shown in capacitor 1A2 according to the second modified example based on embodiment 1 described above, in which the capacitance forming portion is electrically led out by the second external connection wiring from the second main surface side of the insulating substrate in the same manner as the first external connection wiring.
  • the thickness of the sealing portion 30 is measured, for example, by observing a cross section perpendicular to the extension direction of the first main surface 10a of the insulating substrate 10 using an optical microscope.
  • the longitudinal direction of the capacitor 1D is Lx
  • the lateral direction is Ly
  • the thickness direction of the capacitor 1D i.e., the normal direction to the first main surface 10a
  • the capacitor 1D is polished so that the Lx-Lz cross section of the capacitor 1D at the center in the Ly direction is exposed.
  • the polishing process is performed so that the exposed cross section is located within an error range of ⁇ 100 ⁇ m in the Ly direction based on the central position.
  • the exposed cross section near the outer surface 30a is observed using an optical microscope at a magnification of 1000x.
  • the observation range of the cross section in the Lx direction is within ⁇ 50 ⁇ m from the center position of the cross section in the Lx direction.
  • the thickness of the sealing portion 30 in the Lz direction is measured at 10 points equally spaced in the Lx direction, and the average value is calculated.
  • the average value calculated in this manner is the thickness of the sealing portion 30.
  • FIG. 33(A) three of the thicknesses of the sealing portion 30 in the Lz direction measured at these 10 points are illustrated as line segment lengths e1, e2, and e3.
  • FIG. 37 is a schematic cross-sectional view of a capacitor according to embodiment 5.
  • Fig. 38(A) and Fig. 38(B) are enlarged cross-sectional views of main parts of regions XXXVIIIA and XXXVIIIB, respectively, of the capacitance forming portion shown in Fig. 37.
  • a capacitor 1D according to the present embodiment will be described with reference to Figs. 37 and 38.
  • the capacitor 1E of this embodiment differs from the capacitor 1B of the second embodiment described above in the configuration of the capacitance forming portion 20E.
  • the capacitance forming portion 20E has a conductive structure 21E, a dielectric film including a first dielectric film 22aE, a second dielectric film 22bE and a third dielectric film 22cE, and a conductive film 23E.
  • the structure 21E and the first dielectric film 22aE have the same configuration as the structure 21D and the first dielectric film 22aD in the fourth embodiment described above.
  • the second dielectric film 22bE covers the entire surface of the first dielectric film 22aE.
  • the third dielectric film 22cE covers a portion of the surface of the second dielectric film 22bE. More specifically, the third dielectric film 22cE covers the surface of a portion of the second dielectric film 22bE that defines the outer edge portion in a direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 37) and the surface of the end portion on the outer surface 30a side of the sealing portion 30 in the normal direction of the first main surface 10a (i.e., the end portion in the upward direction in FIG. 37).
  • the conductive film 23E covers the surface of the portion of the second dielectric film 22bE that is not covered by the third dielectric film 22cE.
  • the dielectric film has a non-exposed portion 221E that is covered by the conductive film 23E and an exposed portion 222E that is not covered by the conductive film 23E.
  • the portion of the second dielectric film 22bE that is not covered by the third dielectric film 22cE has its surface covered by the conductive film 23E.
  • the first dielectric film 22aE and the second dielectric film 22bE form the non-exposed portion 221E.
  • the portion of the second dielectric film 22bE that is covered by the third dielectric film 22cE has its surface not covered by the conductive film 23E.
  • the first dielectric film 22aE, the second dielectric film 22bE, and the third dielectric film 22cE form an exposed portion 222E.
  • the outer edge of the capacitance forming portion 20E in the direction parallel to the first main surface 10a is defined by the exposed portion 222E composed of the first dielectric film 22aE, the second dielectric film 22bE, and the third dielectric film 22cE. Therefore, the outer edge of the surface of the capacitance forming portion 20E has an MI structure.
  • FIG. 39 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment.
  • the method for manufacturing capacitor 1E differs from the method for manufacturing capacitor 1B (see FIG. 21) in that step S5D is performed instead of steps S6 to S8.
  • Step S5D was described in detail in the description of the method for manufacturing capacitor 1D, so a detailed description of each step of the method for manufacturing capacitor 1E will be omitted here.
  • capacitor 1E according to this embodiment with the characteristic configuration shown in capacitor 1A1 according to the first modified example based on embodiment 1 described above, in which the capacitance forming portion is electrically led out by the first external connection wiring from the outer surface side of the sealed portion in the same manner as the second external connection wiring. It is also of course possible to combine capacitor 1E with the characteristic configuration shown in capacitor 1A2 according to the second modified example based on embodiment 1 described above, in which the capacitance forming portion is electrically led out by the second external connection wiring from the second main surface side of the insulating substrate in the same manner as the first external connection wiring.
  • Fig. 40 is a schematic cross-sectional view of a capacitor according to embodiment 6.
  • Fig. 41(A) and Fig. 41(B) are enlarged cross-sectional views of essential parts of region XLIA and region XLIB, respectively, of the capacitance forming portion shown in Fig. 40.
  • a capacitor 1F according to the present embodiment will be described with reference to Figs. 40 and 41.
  • the capacitor 1F of this embodiment differs from the capacitor 1C of the above-described embodiment 3 in the configuration of the capacitance forming portion 20F.
  • the capacitance forming portion 20F has a conductive structure 21F, a dielectric film including a first dielectric film 22aF and a second dielectric film 22bF, and a conductive film 23F.
  • the structure 21F and the first dielectric film 22aF have the same configuration as the structure 21D and the first dielectric film 22aD in the fourth embodiment described above.
  • the second dielectric film 22bF covers a portion of the surface of the first dielectric film 22aF. More specifically, the second dielectric film 22bF covers the surface of the first dielectric film 22aF except for the portions that define the outer edge portion in the direction parallel to the first main surface 10a of the insulating substrate 10 (i.e., both ends in the left-right direction in FIG. 40).
  • the conductive film 23F covers the entire surface of the second dielectric film 22bF.
  • the dielectric film has a non-exposed portion 221F that is covered by the conductive film 23F, and an exposed portion 222F that is not covered by the conductive film 23F.
  • the entire surface of the second dielectric film 22bF is covered with the conductive film 23F.
  • the first dielectric film 22aF and the second dielectric film 22bF form the non-exposed portion 221F.
  • the portion of the first dielectric film 22aF that is covered by the second dielectric film 22bF does not have its surface covered by the conductive film 23F.
  • the first dielectric film 22aF forms an exposed portion 222F.
  • the outer edge of the capacitance forming portion 20F in a direction parallel to the first main surface 10a is defined by the exposed portion 222F formed by the first dielectric film 22aF. Therefore, the outer edge of the surface of the capacitance forming portion 20F has an MI structure.
  • FIG. 42 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment. As shown in FIG. 42, the method for manufacturing capacitor 1F differs from the method for manufacturing capacitor 1C (see FIG. 27) in that step S5D is performed instead of steps S6 to S8. Step S5D was described in detail in the description of the method for manufacturing capacitor 1D, so a detailed description of each step of the method for manufacturing capacitor 1F will be omitted here.
  • capacitor 1F according to this embodiment with the characteristic configuration shown in capacitor 1A1 according to the first modified example based on embodiment 1 described above, in which the capacitance forming portion is electrically led out by the first external connection wiring from the outer surface side of the sealed portion in the same manner as the second external connection wiring. It is also of course possible to combine capacitor 1F with the characteristic configuration shown in capacitor 1A2 according to the second modified example based on embodiment 1 described above, in which the capacitance forming portion is electrically led out by the second external connection wiring from the second main surface side of the insulating substrate in the same manner as the first external connection wiring.
  • (Seventh embodiment) 43 is a schematic cross-sectional view of a capacitor according to embodiment 7.
  • a capacitor 1G according to the present embodiment will be described with reference to FIG.
  • the capacitor 1G of this embodiment differs from the capacitor 1D of the above-mentioned embodiment 4 in that the above-mentioned moisture-resistant protective film 40 is used instead of the sealing portion 30.
  • the capacitance forming portion 20D is sealed by the insulating substrate 10 and the moisture-resistant protective film 40. This improves the moisture resistance of the capacitor 1G.
  • the connecting conductor 15 is provided so as to cover the entire surface of the first main surface 10a as described above.
  • the connecting conductor 15 interposed between the insulating substrate 10 and the structure 21D includes an outer portion 15a that is located outside the structure 21D in a direction parallel to the first main surface 10a and extends to reach the edge of the insulating substrate 10.
  • the first dielectric film 22aD also covers the surface of the connecting conductor 15 in the portion that is not joined to the structure 21D.
  • the surface of the outer portion 15a opposite the side facing the insulating substrate 10 is covered by the exposed portion 222D of the first dielectric film 22aD. Therefore, the outer end of the exposed portion 222D reaches the edge of the insulating substrate 10.
  • the first path is a path from the outer surface 40a of the moisture-resistant protective film 40 in the thickness direction of the capacitor 1D (i.e., the normal direction of the first main surface 10a) through the first interface formed by the second via conductor 14 and the moisture-resistant protective film 40, and through the second interface formed by the moisture-resistant protective film 40 and the extraction electrode 18, to the conductive film 23D (see path RT1 in Figure 43).
  • the second path is a path from the outer end of the exposed portion 222D in a direction parallel to the first main surface 10a through the third interface formed by the moisture-resistant protective film 40 and the exposed portion 222D to the conductive film 23D (see path RT2 in Figure 43).
  • the third path is a path from the outer edge of the outer portion 15a in a direction parallel to the first main surface 10a, through the fourth interface formed by the exposed portion 222D and the connecting conductor 15, to the structure 21D (see path RT3 in Figure 43).
  • the second via conductor 14 is arranged so as to satisfy R1>R2 and R1>R3.
  • the shortest distance D (see FIG. 43) between the outermost part of the outer edge of the capacitance forming portion 20D in the direction parallel to the first main surface 10a and the edge of the insulating substrate 10 in that direction is 5 ⁇ m or more and 200 ⁇ m or less. This ensures that the lengths of the distances R2 and R3 are sufficient, which also improves the moisture resistance of the capacitor 1G.
  • FIG. 44 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment. As shown in FIG. 44, the method for manufacturing capacitor 1G differs from the method for manufacturing capacitor 1D (see FIG. 34) in that step S15G is performed instead of step S15.
  • a moisture-resistant protective film 40 is provided on the first main surface 10a of the insulating substrate 10 on which the capacitance forming portion 20D is provided, so as to cover the capacitance forming portion 20D and the extraction electrode 18.
  • the moisture-resistant protective film 40 is formed, for example, by a CVD method, an ALD method, or the like.
  • the characteristic configuration of the capacitor 1G according to this embodiment can also be combined with a structure made up of multiple pillars, as shown in the capacitors 1A to 1C according to embodiments 1 to 3.
  • the moisture-resistant protective film 40 is used has been exemplified, but instead of the moisture-resistant protective film 40, a combination of the sealing portion 30 and the moisture-resistant protective film 40 may be used.
  • Fig. 45 is a schematic cross-sectional view of a capacitor according to embodiment 8.
  • a capacitor 1H according to the present embodiment will be described with reference to Fig. 45.
  • the capacitor 1H of this embodiment differs from the capacitor 1D of the above-mentioned embodiment 4 mainly in that the above-mentioned moisture-resistant protective film 40 is used instead of the sealing portion 30, and in the configuration of the insulating substrate 10H.
  • the capacitance forming portion 20D is sealed by the insulating substrate 10H and the moisture-resistant protective film 40.
  • the insulating substrate 10H has a flat base 10s including a first main surface 10a and a second main surface 10b, and a peripheral wall 10t extending from the periphery of the base 10s.
  • the capacitance forming portion 20D is disposed inside a recess defined by the base portion 10s and the peripheral wall portion 10t. Between the capacitance forming portion 20D and the peripheral wall portion 10t, a moisture-resistant protective film 40 having a predetermined thickness is interposed along a direction parallel to the first main surface 10a.
  • the connecting conductor 15 includes an extension portion 15b that is provided continuously on the first main surface 10a of a portion located outside the structure 21D in a direction parallel to the first main surface 10a, on the inner side surface 10t1 of the peripheral wall portion 10t, and on the top surface 10t2 of the peripheral wall portion 10t.
  • the extension portion 15b reaches the outer end of the top surface 10t2 of the peripheral wall portion 10t in a direction parallel to the first main surface 10a.
  • the first dielectric film 22aD also covers the surface of the connecting conductor 15 in the portion that is not joined to the structure 21D.
  • the surface of the extension portion 15b opposite the side facing the insulating substrate 10 is covered by the exposed portion 222D of the first dielectric film 22aD. Therefore, the outer end of the exposed portion 222D reaches the edge of the insulating substrate 10.
  • capacitor 1H of this embodiment can be manufactured essentially in accordance with the manufacturing method of the capacitor 1G of the seventh embodiment described above.
  • insulating substrate 10H by configuring insulating substrate 10H to be approximately concave, the distance of each of the shortest paths, including the above-mentioned path RT2 and the path from the outer edge of extension portion 15b in a direction parallel to first main surface 10a through the fifth interface formed by exposed portion 222D and connecting conductor 15 to structure 21D (see path RT4 in FIG. 45), is longer than when insulating substrate 10H is flat. As a result, the moisture resistance of capacitor 1H is improved.
  • the position of the top surface 10t2 of the peripheral wall portion 10t in the thickness direction of the capacitor 1H is disposed outside the position of the capacitance forming portion 20D in the thickness direction of the capacitor 1H. This ensures that the shortest path distances of the paths RT2 and RT4 are sufficiently long, resulting in further improvement in the moisture resistance of the capacitor 1H.
  • capacitor 1H can also be combined with a structure consisting of multiple pillars, as shown in capacitors 1A to 1C according to embodiments 1 to 3.
  • the moisture-resistant protective film 40 is used has been exemplified, but instead of the moisture-resistant protective film 40, a combination of the sealing portion 30 and the moisture-resistant protective film 40 may be used.
  • (Embodiment 9) 46 is a schematic cross-sectional view of a capacitor according to embodiment 9.
  • a capacitor 1J according to the present embodiment will be described with reference to FIG.
  • the capacitor 1J of this embodiment differs from the capacitor 1D of the fourth embodiment in that the moisture-resistant protective film 40 described above is used instead of the sealing portion 30, and in the configuration of the insulating substrate 10J.
  • the capacitance forming portion 20D is sealed by the insulating substrate 10J and the moisture-resistant protective film 40.
  • the insulating substrate 10J has a flat base 10s including a first main surface 10a and a second main surface 10b, and a peripheral wall 10t erected from the peripheral edge of the base 10s.
  • the position of the top surface 10t2 of the peripheral wall 10t in the thickness direction of the capacitor 1J is located outside the position of the capacitance forming portion 20D in the thickness direction of the capacitor 1J.
  • the capacitance forming portion 20D is located inside a recess defined by the base 10s and the peripheral wall 10t.
  • the connecting conductor 15 includes an outer portion 15a that is provided continuously on the inner surface 10t1 of the peripheral wall portion 10t and on the top surface 10t2 of the peripheral wall portion 10t.
  • the outer portion 15a is located outside the structure 21D in a direction parallel to the first main surface 10a.
  • the outer portion 15a reaches the outer end of the top surface 10t2 of the peripheral wall portion 10t in a direction parallel to the first main surface 10a.
  • the first dielectric film 22aD also covers the surface of the connecting conductor 15 in the portion that is not joined to the structure 21D.
  • the surface of the outer portion 15a opposite the side facing the insulating substrate 10 is covered by the exposed portion 222D of the first dielectric film 22aD. Therefore, the outer end of the exposed portion 222D reaches the edge of the insulating substrate 10.
  • the outer edge of the capacitance forming portion 20D in a direction parallel to the first main surface 10a is in contact with the exposed portion 222D located on the inner surface 10t1 of the peripheral wall portion 10t.
  • the shortest distance D (see FIG. 46) in the direction between the outermost portion of the capacitance forming portion 20D in the direction parallel to the first main surface 10a and the edge of the insulating substrate 10 in that direction is preferably 5 ⁇ m or more and 200 ⁇ m or less. This ensures that the lengths of the distances R2 and R3 are sufficient, resulting in improved moisture resistance of the capacitor 1J.
  • capacitor 1J of this embodiment can be manufactured essentially in accordance with the manufacturing method of the capacitor 1G of the seventh embodiment described above.
  • capacitor 1J can also be combined with a structure consisting of multiple pillars, as shown in capacitors 1A to 1C according to embodiments 1 to 3.
  • the moisture-resistant protective film 40 is used has been exemplified, but instead of the moisture-resistant protective film 40, a combination of the sealing portion 30 and the moisture-resistant protective film 40 may be used.
  • the dielectric film includes a first dielectric film covering a surface of the structure, a second dielectric film covering the surface of the first dielectric film and having adhesion to the conductive film, and a third dielectric film covering a portion of the surface of the second dielectric film and not having adhesion to the conductive film, the non-exposed portion is constituted by the first dielectric film and the second dielectric film, 2.
  • the dielectric film includes a first dielectric film covering a surface of the structure, and a second dielectric film covering a surface of the first dielectric film and having adhesion to the conductive film, the non-exposed portion is constituted by the first dielectric film and the second dielectric film, 2.
  • Appendix 7 A capacitor as described in any one of claims 1 to 6, wherein the structure is made of at least one conductive material selected from the group consisting of nickel, aluminum, and tantalum.
  • Appendix 8 Providing an insulating substrate having a major surface; forming a first external connection wiring on the insulating substrate; forming a conductive irregular or porous structure on the main surface; forming a first dielectric film so as to cover a surface of the structure in a state in which the structure and the first external connection wiring are connected to each other; a step of forming a capacitance forming portion having an outermost surface formed with the structure, the first dielectric film, and the conductive film, the capacitance forming portion being formed so as to cover a surface of the first dielectric film in a state where the first dielectric film is formed; forming a second external connection wiring connected to the conductive film in a state in which the capacitance forming portion is formed; forming a resist film so as to cover a portion of a surface of the second external connection wiring, the portion corresponding to a portion other than an outer edge portion in a direction parallel to the main surface of the conductive film, in a state in which the conductive film and the second
  • Appendix 13 A method for manufacturing a capacitor according to any one of appendixes 8 to 12, wherein the structure is made of at least one conductive material selected from the group consisting of nickel, aluminum, and tantalum.
  • 1A-1F, 1A1, 1A2 capacitor, 10, 10H, 10J insulating substrate 10a first main surface, 10b second main surface, 10s base, 10t peripheral wall, 10t1 inner surface, 10t2 top surface, 11 first through hole, 12 second through hole, 13 first via conductor, 14 second via conductor, 15 connecting conductor, 15a outer portion, 15b extension, 16 first bump, 17 second bump, 18 lead electrode, 18a upper surface, 20, 20B-20F capacitance forming portion, 21, 21D to 21F: structure, 21a: columnar body, 21b: metal porous body, 22a, 22aD to 22aF: first dielectric film, 22b, 22bE, 22bF: second dielectric film, 22c, 22cE: third dielectric film, 23, 23B to 23F: conductive film, 24, 24C: resist film, 30: sealing portion, 30a: outer surface, 40: moisture-resistant protective film, 40a: outer surface, 101: mold for forming structure, 102: pores, 221, 221B to 221F

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