WO2025018044A1 - チップ抵抗器 - Google Patents

チップ抵抗器 Download PDF

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Publication number
WO2025018044A1
WO2025018044A1 PCT/JP2024/020148 JP2024020148W WO2025018044A1 WO 2025018044 A1 WO2025018044 A1 WO 2025018044A1 JP 2024020148 W JP2024020148 W JP 2024020148W WO 2025018044 A1 WO2025018044 A1 WO 2025018044A1
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Prior art keywords
electrode
disposed
chip resistor
layer
resistor
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PCT/JP2024/020148
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English (en)
French (fr)
Japanese (ja)
Inventor
高徳 篠浦
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202480045962.0A priority Critical patent/CN121488309A/zh
Priority to JP2025533898A priority patent/JPWO2025018044A1/ja
Publication of WO2025018044A1 publication Critical patent/WO2025018044A1/ja
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors
    • H01C1/142—Terminals or tapping points specially adapted for resistors; Arrangements of terminals or tapping points on resistors the terminals or tapping points being coated on the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material

Definitions

  • This disclosure relates to chip resistors.
  • Patent Document 1 JP 2022-105204 A discloses a chip resistor that includes a substrate, a resistor layer, a protective layer, a conductor layer, a back electrode layer, and a plating layer.
  • the chip resistor is mounted on a wiring board via a conductive bonding material such as solder.
  • a chip resistor includes an insulating substrate, a resistor, a back electrode, and a side electrode.
  • the insulating substrate includes a front surface, a back surface, and a side surface.
  • the back surface is disposed on the opposite side to the front surface.
  • the side surface connects the front surface and the back surface.
  • the resistor is disposed on at least one of the front surface and the back surface.
  • the back surface electrode is disposed on the back surface.
  • the side electrode is disposed on the side surface and the back surface electrode.
  • the direction perpendicular to the back surface is the Z direction.
  • the side electrode has a lowermost point.
  • the lowermost point is disposed at a position furthest from the back surface in the Z direction.
  • the side electrode has a lowermost surface.
  • the lowermost surface is a region from the side surface to the lowermost point.
  • the lowermost surface is inclined with respect to the back surface.
  • the lowermost surface has a first region.
  • the first region includes the lowermost point.
  • the inclination angle of the lowermost surface with respect to the back surface is 1° or more and 10° or less.
  • FIG. 1 is a schematic plan view of a chip resistor according to a first embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II shown in FIG.
  • FIG. 3 is a partially enlarged cross-sectional view of region III shown in FIG.
  • FIG. 4 is a partially enlarged cross-sectional view of a modified example of the chip resistor according to the first embodiment.
  • FIG. 5 is a partially enlarged cross-sectional view of a modified example of the chip resistor according to the first embodiment.
  • FIG. 6 is a partial cross-sectional view of a chip resistor after a temperature cycle test in a comparative example.
  • FIG. 7 is a partial cross-sectional view of a chip resistor after a temperature cycle test in an embodiment.
  • FIG. 1 is a schematic plan view of a chip resistor according to a first embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II shown in FIG.
  • FIG. 3 is a
  • FIG. 8 is a schematic cross-sectional view of a chip resistor according to the second embodiment.
  • FIG. 9 is a schematic cross-sectional view of a chip resistor according to the third embodiment.
  • FIG. 10 is a schematic cross-sectional view of a chip resistor according to the fourth embodiment.
  • FIG. 11 is a schematic cross-sectional view of a chip resistor according to the fifth embodiment.
  • FIG. 12 is a schematic cross-sectional view of a chip resistor according to the sixth embodiment.
  • FIG. 13 is a schematic cross-sectional view of a chip resistor according to the seventh embodiment.
  • FIG. 14 is a schematic cross-sectional view of a chip resistor according to the eighth embodiment.
  • FIG. 15 is a schematic cross-sectional view of a chip resistor according to the ninth embodiment.
  • FIG. 16 is a schematic cross-sectional view of a chip resistor according to a tenth embodiment.
  • FIG. 17 is a schematic cross-sectional view of a chip resistor according to an eleventh embodiment.
  • FIG. 18 is a schematic cross-sectional view of a chip resistor according to a twelfth embodiment.
  • Fig. 1 is a schematic plan view of a chip resistor according to embodiment 1.
  • Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1.
  • Fig. 3 is a partially enlarged cross-sectional view of region III in Fig. 2.
  • the chip resistor 1a includes an insulating substrate 10, a resistor 3, an insulating protective film 4, a surface electrode 2a, a back electrode 2b, and a side electrode 5.
  • the insulating substrate 10 is formed of a ceramic material such as alumina (Al 2 O 3 ).
  • the insulating substrate 10 includes a surface 11, a back surface 12, and a side surface 13.
  • the back surface 12 is the surface opposite to the surface 11.
  • the side surface 13 connects the surface 11 and the back surface 12.
  • the side surface 13 includes a first side surface 13a and a second side surface 13b.
  • the second side surface 13b is the surface opposite to the first side surface 13a. In other words, each of the first side surface 13a and the second side surface 13b connects the surface 11 and the back surface 12.
  • the direction perpendicular to the side surface 13 is the X direction.
  • the direction perpendicular to the front surface 11 and the back surface 12 is the Z direction.
  • the direction perpendicular to both the X direction and the Z direction is the Y direction.
  • the X direction is the longitudinal direction of the insulating substrate 10 in FIG. 2.
  • the Z direction is the thickness direction of the insulating substrate 10.
  • the front surface 11 and the back surface 12 are both end faces of the insulating substrate 10 in the thickness direction (Z direction).
  • the back surface 12 is the surface (mounting surface) that faces the circuit board (not shown) when the chip resistor 1a is mounted on the circuit board.
  • the first side surface 13a and the second side surface 13b are both end faces of the insulating substrate 10 in the longitudinal direction (X direction).
  • the resistor 3 is disposed on at least one of the front surface 11 and the back surface 12.
  • the resistor 3 has a first resistor 31 and a second resistor 32.
  • the resistor 3 is, for example, a CuNi resistor.
  • the first resistor 31 is disposed on the surface 11.
  • the center 31c of the first resistor 31 in the longitudinal direction (X direction) of the insulating substrate 10 does not have to coincide with, for example, the center 10c of the insulating substrate 10 in the longitudinal direction of the insulating substrate 10.
  • the second resistor 32 is disposed on the back surface 12.
  • the center 32c of the second resistor 32 in the longitudinal direction (X direction) of the insulating substrate 10 may not coincide with, for example, the center 10c of the insulating substrate 10 in the longitudinal direction of the insulating substrate 10.
  • the center 31c of the first resistor 31 may not coincide with the center 32c of the second resistor 32 in the longitudinal direction (X direction).
  • the surface electrode 2a is disposed on the surface 11.
  • the surface electrode 2a includes a first surface electrode 20 and a second surface electrode 21.
  • the first surface electrode 20 and the second surface electrode 21 are connected to the first resistor 31.
  • the second surface electrode 21 is disposed at a distance from the first surface electrode 20 in the X direction.
  • the first surface electrode 20 is disposed closer to the first side surface 13a than the second surface electrode 21.
  • the second surface electrode 21 is disposed closer to the second side surface 13b than the first surface electrode 20.
  • the first surface electrode 20 and the second surface electrode 21 are disposed so as to sandwich the first resistor 31 in the X direction.
  • the surface electrode 2a is, for example, a Cu electrode or an Ag electrode.
  • the back surface electrode 2b is disposed on the back surface 12.
  • the back surface electrode 2b includes a first back surface electrode 23 and a second back surface electrode 24.
  • the first back surface electrode 23 and the second back surface electrode 24 are connected to the second resistor 32.
  • the second back surface electrode 24 is disposed spaced apart from the first back surface electrode 23 in the X direction.
  • the first back surface electrode 23 is disposed closer to the first side surface 13a than the second back surface electrode 24.
  • the second back surface electrode 24 is disposed closer to the second side surface 13b than the first back surface electrode 23.
  • the first back surface electrode 23 and the second back surface electrode 24 are disposed so as to sandwich the second resistor 32 in the X direction.
  • the back electrode 2b is, for example, a Cu electrode or an Ag electrode.
  • the first back electrode 23 and the second back electrode 24 are formed, for example, from the same conductive material as the first surface electrode 20 and the second surface electrode 21.
  • the front electrode 2a and the back electrode 2b may be composed of multiple layers, for example, two or three layers.
  • the insulating protective film 4 is disposed on the resistor 3.
  • the insulating protective film 4 includes a first insulating protective film 41 and a second insulating protective film 42.
  • the first insulating protective film 41 is disposed on the first resistor 31.
  • the first insulating protective film 41 is also disposed on the first surface electrode 20 and the second surface electrode 21.
  • the second insulating protective film 42 is disposed on the second resistor 32.
  • the second insulating protective film 42 is also disposed on the first back surface electrode 23 and the second back surface electrode 24.
  • the insulating protective film 4 contains, for example, an epoxy resin, a phenolic resin, or a mixture of an epoxy resin and a phenolic resin.
  • the second resistor 32 and the second insulating protective film 42 need only be formed on the rear surface 12, and as described below, the first resistor 31 and the first insulating protective film 41 do not need to be disposed on the front surface 11.
  • the side electrodes 5 are arranged on the side surfaces 13, the front surface electrodes 2a, and the rear surface electrodes 2b.
  • the side electrodes 5 include a first side electrode 51 and a second side electrode 52.
  • the first side electrode 51 is disposed on the first side 13a of the insulating substrate 10, the first surface electrode 20, and the first back surface electrode 23.
  • the first surface electrode 20 is electrically connected to the first back surface electrode 23 through the first side electrode 51.
  • the first side electrode 51 includes a first layer 51a, a second layer 51b, a third layer 51c, and a fourth layer 51d.
  • the first layer 51a is disposed on the first side surface 13a, the first front surface electrode 20, and the first back surface electrode 23 of the insulating substrate 10.
  • the first layer 51a is formed, for example, of a conductive material that is difficult to sulfurize.
  • the first layer 51a is formed, for example, of a Ni-Cr alloy.
  • the first layer 51a is, for example, a sputtered layer.
  • the first layer 51a may be disposed on the first insulating protective film 41 and the second insulating protective film 42, but in the present embodiment 1, the first layer 51a is not disposed on the first insulating protective film 41 and the second insulating protective film 42.
  • the second layer 51b is disposed on the first surface electrode 20, the first back surface electrode 23, and the first layer 51a.
  • the second layer 51b is, for example, a copper layer.
  • the second layer 51b is connected to the first insulating protective film 41 and the second insulating protective film 42.
  • the third layer 51c is disposed on the second layer 51b.
  • the third layer 51c protects the first surface electrode 20, the first back surface electrode 23, the first layer 51a, and the second layer 51b from heat and impact.
  • the third layer 51c is, for example, a nickel layer.
  • the third layer 51c is connected to the first insulating protective film 41 and the second insulating protective film 42.
  • the fourth layer 51d is disposed on the third layer 51c.
  • the fourth layer 51d is formed of a material to which a conductive bonding member 200 (not shown), such as solder, is easily attached.
  • the fourth layer 51d is, for example, a tin layer.
  • the fourth layer 51d is connected to the first insulating protective film 41 and the second insulating protective film 42.
  • the second side electrode 52 is disposed on the second side 13b of the insulating substrate 10, the second surface electrode 21, and the second back surface electrode 24.
  • the second surface electrode 21 is electrically connected to the second back surface electrode 24 through the second side electrode 52.
  • the second side electrode 52 includes a first layer 52a, a second layer 52b, a third layer 52c, and a fourth layer 52d.
  • the first layer 52a is disposed on the second side surface 13b of the insulating substrate 10, the second front surface electrode 21, and the second rear surface electrode 24.
  • the first layer 52a is formed, for example, of a conductive material that is difficult to sulfurize.
  • the first layer 52a is formed, for example, of a Ni-Cr alloy.
  • the first layer 52a is, for example, a sputtered layer.
  • the first layer 52a may be disposed on the first insulating protective film 41 and the second insulating protective film 42, but in this embodiment 1, the first layer 52a is not disposed on the first insulating protective film 41 and the second insulating protective film 42.
  • the second layer 52b is disposed on the second surface electrode 21, the second back surface electrode 24, and the first layer 52a.
  • the second layer 52b is, for example, a copper layer.
  • the second layer 52b is connected to the first insulating protective film 41 and the second insulating protective film 42.
  • the third layer 52c is disposed on the second layer 52b.
  • the third layer 52c protects the second surface electrode 21, the second back surface electrode 24, the first layer 52a, and the second layer 52b from heat and impact.
  • the third layer 52c is, for example, a nickel layer.
  • the third layer 52c is connected to the first insulating protective film 41 and the second insulating protective film 42.
  • the fourth layer 52d is disposed on the third layer 52c.
  • the fourth layer 52d is formed of a material to which the conductive bonding member 200, such as solder, is easily attached.
  • the fourth layer 52d is, for example, a tin layer.
  • the fourth layer 52d is connected to the first insulating protective film 41 and the second insulating protective film 42.
  • the conductive bonding member 200 (not shown) is attached to the fourth layers 51d, 52d and the electrical wiring (not shown) of the wiring board 100 (not shown), and the chip resistor 1a is mounted on the wiring board 100.
  • a feature of the chip resistor 1a according to the present embodiment 1 is that the bottom surface 50s of the side electrode 5 is inclined with respect to the back surface 12.
  • the side electrode 5 has a bottom point P1.
  • the bottom point P1 is located at a position furthest from the back surface 12 in the Z direction.
  • the side electrode 5 has a bottom surface 50s.
  • the bottom surface 50s is a region from the side surface 13 to the bottom point P1.
  • the bottom surface 50s is inclined with respect to the back surface 12.
  • the bottom surface 50s has a first region L1.
  • the first region L1 is a region away from the side surface 13 in the X direction and includes the bottom point P1.
  • the inclination angle ⁇ 1 of the bottom surface 50s with respect to the back surface 12 is 1° or more and 10° or less.
  • the chip resistor 1a When the chip resistor 1a is mounted on the wiring board 100 via the conductive bonding member 200, the chip resistor 1a is mounted so that the back surface 12 is parallel to the mounting surface of the wiring board 100.
  • the chip resistor 1a When the chip resistor 1a is mounted on the wiring board 100 via such a conductive bonding member 200, there is a risk that a crack 400 will occur between the bottom surface 50s and the wiring board 100 due to thermal fatigue such as a temperature cycle.
  • the stress concentration on the conductive bonding member 200 caused by thermal fatigue is mitigated.
  • the occurrence of cracks 400 caused by thermal fatigue between the bottom surface 50s and the wiring board 100 is suppressed.
  • the long-term reliability of the chip resistor 1a is improved.
  • FIGS. 4 and 5 show modified examples of the chip resistor 1a shown in FIGS. 1 to 3.
  • the chip resistors 1b and 1c shown in FIGS. 4 and 5 basically have the same configuration as the chip resistor 1a shown in FIGS. 1 to 3, but differ in that the bottom surface 50s has a plurality of different inclination angles ⁇ .
  • the bottom surface 50s may have a second region L2.
  • the second region L2 is disposed at a position closest to the side surface 13 in the X direction.
  • the inclination angle ⁇ 2 of the bottom surface 50s with respect to the back surface 12 may be 1° or more, but is more preferably 5° or more.
  • the second region L2 of the bottom surface 50s is adjacent to the first region L1.
  • the width of the first region L1 is preferably at least half the distance from the side surface 13 to the lowest point P1.
  • the width of the first region L1 is the distance in the X direction from the lowest point P1 to the point where the first region L1 connects to the second region L2.
  • the bottom surface 50s may have a third region L3.
  • the third region L3 is disposed between the first region L1 and the second region L2 in the X direction. That is, the first region L1 is disposed between the lowest point P1 and the third region L3 in the X direction.
  • the second region L2 is disposed between the side surface 13 and the third region L3 in the X direction.
  • the inclination angle ⁇ 3 of the bottom surface 50s with respect to the back surface 12 is preferably 1° or more and 5° or less.
  • the width of each of the first region L1, the second region L2, and the third region L3 is preferably 1 ⁇ 4 or more and 1 ⁇ 2 or less of the distance from the side surface 13 to the lowest point P1.
  • the chip resistors 1a, 1b, and 1c are mounted on the wiring board 100 so that the bottom surface 50s is inclined relative to the mounting surface of the wiring board 100, the stress concentration on the conductive bonding member 200 caused by temperature cycles is alleviated. In other words, the occurrence of cracks 400 due to thermal fatigue between the bottom surface 50s and the wiring board 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a is improved.
  • the inclination angle ⁇ is the angle between each of the approximation lines A1, A2, and A3 and each of the parallel lines B1, B2, and B3.
  • the inclination angle ⁇ is a narrow angle.
  • the parallel lines B1, B2, and B3 are lines parallel to the back surface 12.
  • the approximation line A1 is a linear line calculated from consecutive points on the bottom surface 50s in the first region L1.
  • the approximation line A2 is a linear line calculated from consecutive points on the bottom surface 50s in the second region L2.
  • the approximation line A3 is a linear line calculated from consecutive points on the bottom surface 50s in the third region L3.
  • the consecutive points are captured from a cross-sectional photograph of the chip resistor 1a.
  • the approximation lines A1, A2, and A3 are calculated from the consecutive points using, for example, the least squares method.
  • the inclination angles ⁇ 1, ⁇ 2, ⁇ 3 are calculated by calculating the angles between the approximation lines A1, A2, A3 calculated in this way and the parallel lines B1, B2, B3, respectively.
  • the surface electrode 2a extends to the side surface 13, there is a risk of burrs being generated on the side surface 13 during the manufacturing stage of the chip resistor 1a. Therefore, it is preferable that the surface electrode 2a does not extend to the side surface 13 when viewed in a plan view from the Z direction.
  • the back electrode 2b does not extend to the side surface 13, stress concentration occurs at the corners of the insulating substrate 10 due to temperature cycling. As a result, there is a risk of cracks 400 occurring at the corners of the insulating substrate 10 due to thermal fatigue. In order to reduce stress concentration at the corners of the insulating substrate 10, it is preferable that the back electrode 2b extends to the side surface 13 in a plan view seen from the Z direction.
  • the width W1 of the sputtered layer in the X direction is 10 nm or more.
  • the width W1 of the first layer 51a in the X direction is 10 nm or more.
  • the width W2 of the side electrode 5 in the X direction is 15 ⁇ m or more.
  • the width W2 of the first side electrode 51 in the X direction is 15 ⁇ m or more.
  • the thickness T1 of the back electrode 2b in the Z direction is 5 ⁇ m or more.
  • the thickness T1 is, for example, the distance from the back surface 12 to the point of the back electrode 2b that is located at the farthest position in the Z direction.
  • the chip resistor 1a includes an insulating substrate 10, a resistor 3, a back electrode 2b, and a side electrode 5.
  • the insulating substrate 10 includes a front surface 11, a back surface 12, and a side surface 13.
  • the back surface 12 is disposed on the opposite side of the front surface 11.
  • the side surface 13 connects the front surface 11 and the back surface 12.
  • the resistor 3 is disposed on at least one of the front surface 11 and the back surface 12.
  • the back surface electrode 2b is disposed on the back surface 12.
  • the side electrode 5 is disposed on the side surface 13 and the back surface electrode 2b.
  • the direction perpendicular to the back surface 12 is the Z direction.
  • the side electrode 5 has a lowest point P1.
  • the lowest point P1 is disposed at a position furthest from the back surface 12 in the Z direction.
  • the side electrode 5 has a lowest surface 50s.
  • the lowest surface 50s is a region from the side surface 13 to the lowest point P1.
  • the lowest surface 50s is inclined with respect to the back surface 12.
  • the lowest surface 50s has a first region L1.
  • the first region L1 includes the lowest point P1.
  • the inclination angle ⁇ 1 of the lowest surface 50s with respect to the rear surface 12 is equal to or greater than 1° and is equal to or smaller than 10°.
  • the direction perpendicular to the side surface 13 is defined as the X direction.
  • the bottom surface 50s has a second region L2.
  • the second region L2 is disposed at a position closest to the side surface 13 in the X direction.
  • the inclination angle ⁇ 2 of the bottom surface 50s with respect to the back surface 12 is 5° or more.
  • the stress concentration on the conductive bonding member 200 caused by temperature cycles is mitigated.
  • the occurrence of cracks 400 due to thermal fatigue between the bottom surface 50s and the wiring board 100 is suppressed.
  • the long-term reliability of the chip resistor 1a can be improved.
  • the bottom surface 50s has a third region L3.
  • the third region L3 is disposed between the first region L1 and the second region L2 in the X direction.
  • the inclination angle ⁇ 3 of the bottom surface 50s with respect to the back surface 12 is 1° or more and 5° or less.
  • the stress concentration on the conductive bonding member 200 caused by temperature cycles is mitigated.
  • the occurrence of cracks 400 due to thermal fatigue between the bottom surface 50s and the wiring board 100 is suppressed.
  • the long-term reliability of the chip resistor 1a can be improved.
  • the width of the first region L1 in the X direction is equal to or greater than 1/2 the distance from the side surface 13 to the lowest point P1. In this way, even if the lowest surface 50s includes multiple inclination angles ⁇ that are different from one another, the stress concentration on the conductive bonding member 200 caused by temperature cycles is mitigated. In other words, the occurrence of cracks 400 due to thermal fatigue between the lowest surface 50s and the wiring board 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a can be improved.
  • the back electrode 2b extends to the side surface 13 in a plan view from the Z direction. This reduces stress concentration at the corners of the insulating substrate 10. As a result, the long-term reliability of the chip resistor 1a can be improved.
  • the thickness T1 of the back electrode 2b in the Z direction is 5 ⁇ m or more. This reduces stress concentration at the corners of the insulating substrate 10. As a result, the long-term reliability of the chip resistor 1a can be improved.
  • the width W2 of the side electrode 5 in the X direction is 15 ⁇ m or more. This reduces stress concentration at the corners of the insulating substrate 10. As a result, the long-term reliability of the chip resistor 1a can be improved.
  • the chip resistor 1a further includes a surface electrode 2a and an insulating protective film 4.
  • the surface electrode 2a is disposed on the surface 11.
  • the insulating protective film 4 includes a first insulating protective film 41 and a second insulating protective film 42.
  • the side surface 13 includes a first side surface 13a and a second side surface 13b.
  • the second side surface 13b is disposed on the opposite side to the first side surface 13a.
  • the resistor 3 includes a first resistor 31 and a second resistor 32.
  • the first resistor 31 is disposed on the surface 11.
  • the second resistor 32 is disposed on the back surface 12.
  • the surface electrode 2a includes a first surface electrode 20 and a second surface electrode 21.
  • the second surface electrode 21 is disposed at a distance from the first surface electrode 20 in the X direction.
  • the back surface electrode 2b includes a first back surface electrode 23 and a second back surface electrode 24.
  • the second back surface electrode 24 is disposed at a distance from the first back surface electrode 23 in the X direction.
  • the side electrode 5 includes a first side electrode 51 and a second side electrode 52.
  • the first side electrode 51 is disposed on the first side 13a, the first back electrode 23, and the first surface electrode 20.
  • the second side electrode 52 is disposed on the second side 13b, the second back electrode 24, and the second surface electrode 21.
  • the first insulating protective film 41 is disposed on the first resistor 31, the first surface electrode 20, and the second surface electrode 21.
  • the second insulating protective film 42 is disposed on the second resistor 32, the first back electrode 23, and the second back electrode 24.
  • the chip resistor 1a is mounted on the wiring board 100 so that the bottom surface 50s is inclined relative to the mounting surface of the wiring board 100, the stress concentration on the conductive bonding member 200 caused by temperature cycles is alleviated. In other words, the occurrence of cracks 400 due to thermal fatigue between the bottom surface 50s and the wiring board 100 is suppressed. As a result, the long-term reliability of the chip resistor 1a can be improved.
  • the temperature cycle test is a test in which the chip resistor is repeatedly placed in a low-temperature environment of -55°C for 30 minutes and then in a high-temperature environment of 150°C for 30 minutes.
  • the temperature cycle test is performed on the chip resistors in Examples 1 to 9 and Comparative Example 1.
  • Tables 1 to 3 show the inclination angles ⁇ of the chip resistors in Examples 1 to 9 and Comparative Example 1.
  • Examples 1 to 4 have the same configuration as the chip resistor 1a according to the first embodiment.
  • Examples 5 to 7 have the same configuration as the chip resistor 1b according to the first embodiment.
  • Examples 8 and 9 have the same configuration as the chip resistor 1c according to the first embodiment.
  • the inclination angle ⁇ 1 in Examples 1 to 9 is 1° or more and 10° or less.
  • the inclination angle ⁇ 2 in Examples 5 to 9 is 5° or more.
  • the inclination angle ⁇ 3 in Examples 8 and 9 is 1° or more and 5° or less.
  • the bottom surface 50s of the chip resistor is parallel to the back surface 12. That is, the inclination angle ⁇ in Comparative Example 1 is 0°.
  • the inclination angles ⁇ shown in Tables 1 to 3 are the inclination angles on the first side surface 13a side.
  • Figures 6 and 7 show the chip resistor after the temperature cycle test.
  • Figure 6 is a partial cross-sectional view of the chip resistor after the temperature cycle test in Comparative Example 1.
  • Figure 7 is a partial cross-sectional view of the chip resistor after the temperature cycle test in Example 1.
  • FIG. 8 is a schematic cross-sectional view of the chip resistor 1a of the second embodiment.
  • FIG. 8 corresponds to FIG. 2.
  • the chip resistor 1a shown in FIG. 8 basically has the same configuration as the chip resistor 1a shown in FIG. 1 to FIG. 3 and can obtain the same effect, but is different in that each of the surface electrode 2a and the back electrode 2b is composed of two layers. This configuration makes it easier to control the inclination angle ⁇ .
  • the resistance values of the surface electrode 2a and the back electrode 2b are reduced. Therefore, the resistance temperature coefficient of the chip resistor 1a is reduced.
  • the resistance value of the chip resistor 1a is small, the measurement accuracy of the resistance value in probing is improved.
  • the first surface electrode 20 includes a first electrode layer 20a and a second electrode layer 20b.
  • the first surface electrode 20 is a laminate of the first electrode layer 20a and the second electrode layer 20b.
  • the first electrode layer 20a is disposed on the surface 11.
  • a portion of the first resistor 31 is disposed on the first electrode layer 20a.
  • the second electrode layer 20b is disposed on the first electrode layer 20a.
  • a portion of the second electrode layer 20b is disposed on the first resistor 31.
  • the second surface electrode 21 includes a first electrode layer 21a and a second electrode layer 21b.
  • the second surface electrode 21 is a laminate of the first electrode layer 21a and the second electrode layer 21b.
  • the first electrode layer 21a is disposed on the surface 11.
  • a portion of the first resistor 31 is disposed on the first electrode layer 21a.
  • the second electrode layer 21b is disposed on the first electrode layer 21a.
  • a portion of the second electrode layer 21b is disposed on the first resistor 31.
  • the first back surface electrode 23 includes a first electrode layer 23a and a second electrode layer 23b.
  • the first back surface electrode 23 is a laminate of the first electrode layer 23a and the second electrode layer 23b.
  • the first electrode layer 23a is disposed on the back surface 12.
  • a portion of the second resistor 32 is disposed on the first electrode layer 23a.
  • the second electrode layer 23b is disposed on the first electrode layer 23a.
  • a portion of the second electrode layer 23b is disposed on the second resistor 32.
  • the second back surface electrode 24 includes a first electrode layer 24a and a second electrode layer 24b.
  • the second back surface electrode 24 is a laminate of the first electrode layer 24a and the second electrode layer 24b.
  • the first electrode layer 24a is disposed on the back surface 12.
  • a portion of the second resistor 32 is disposed on the first electrode layer 24a.
  • the second electrode layer 24b is disposed on the first electrode layer 24a.
  • a portion of the second electrode layer 24b is disposed on the second resistor 32.
  • FIG. 9 is a schematic cross-sectional view of the chip resistor 1a of the third embodiment.
  • FIG. 9 corresponds to FIG. 2.
  • the chip resistor 1a shown in FIG. 9 basically has the same configuration as the chip resistor 1a shown in FIG. 1 to FIG. 3 and can obtain the same effect, but is different in that each of the surface electrode 2a and the back electrode 2b is composed of three layers. This configuration makes it easier to control the inclination angle ⁇ .
  • the resistance values of the surface electrode 2a and the back electrode 2b are reduced. Therefore, the resistance temperature coefficient of the chip resistor 1a is reduced.
  • the resistance value of the chip resistor 1a is small, the measurement accuracy of the resistance value in probing is improved.
  • the first surface electrode 20 includes a first electrode layer 20a, a second electrode layer 20b, and a third electrode layer 20c.
  • the first surface electrode 20 is a laminate of the first electrode layer 20a, the second electrode layer 20b, and the third electrode layer 20c.
  • the first electrode layer 20a is disposed on the surface 11.
  • a portion of the first resistor 31 is disposed on the first electrode layer 20a.
  • the second electrode layer 20b is disposed on the first electrode layer 20a.
  • a portion of the second electrode layer 20b is disposed on the first resistor 31.
  • the third electrode layer 20c is disposed on the second electrode layer 20b.
  • the second surface electrode 21 includes a first electrode layer 21a, a second electrode layer 21b, and a third electrode layer 21c.
  • the second surface electrode 21 is a laminate of the first electrode layer 21a, the second electrode layer 21b, and the third electrode layer 21c.
  • the first electrode layer 21a is disposed on the surface 11.
  • a portion of the first resistor 31 is disposed on the first electrode layer 21a.
  • the second electrode layer 21b is disposed on the first electrode layer 21a.
  • a portion of the second electrode layer 21b is disposed on the first resistor 31.
  • the third electrode layer 21c is disposed on the second electrode layer 21b.
  • the first back surface electrode 23 includes a first electrode layer 23a, a second electrode layer 23b, and a third electrode layer 23c.
  • the first back surface electrode 23 is a laminate of the first electrode layer 23a, the second electrode layer 23b, and the third electrode layer 23c.
  • the first electrode layer 23a is disposed on the back surface 12.
  • a portion of the second resistor 32 is disposed on the first electrode layer 23a.
  • the second electrode layer 23b is disposed on the first electrode layer 23a.
  • a portion of the second electrode layer 23b is disposed on the second resistor 32.
  • the third electrode layer 23c is disposed on the second electrode layer 23b.
  • the second back surface electrode 24 includes a first electrode layer 24a, a second electrode layer 24b, and a third electrode layer 24c.
  • the second back surface electrode 24 is a laminate of the first electrode layer 24a, the second electrode layer 24b, and the third electrode layer 24c.
  • the first electrode layer 24a is disposed on the back surface 12.
  • a portion of the second resistor 32 is disposed on the first electrode layer 24a.
  • the second electrode layer 24b is disposed on the first electrode layer 24a.
  • a portion of the second electrode layer 24b is disposed on the second resistor 32.
  • the third electrode layer 24c is disposed on the second electrode layer 24b.
  • FIG. 10 is a schematic cross-sectional view of the chip resistor 1a of the fourth embodiment.
  • FIG. 10 corresponds to FIG. 2.
  • the chip resistor 1a shown in FIG. 10 basically has the same configuration as the chip resistor 1a shown in FIG. 1 to FIG. 3 and can obtain the same effect, but is different in that the sputter layer is also formed on the insulating protective film 4.
  • the first layers 51a and 52a are disposed on the first insulating protective film 41 and the second insulating protective film 42.
  • the side electrode 5 can be formed on the insulating protective film 4.
  • the region in which the side electrode 5 extends in the X direction can be adjusted.
  • FIG. 11 is a schematic cross-sectional view of the chip resistor 1a of the fifth embodiment.
  • FIG. 11 corresponds to FIG. 8.
  • the chip resistor 1a shown in FIG. 11 basically has the same configuration as the chip resistor 1a shown in FIG. 8 and can obtain the same effect, but is different in that the sputter layer arranged on the front electrode 2a and the back electrode 2b composed of two layers is also formed on the insulating protective film 4.
  • the first layers 51a and 52a are arranged on the first insulating protective film 41 and the second insulating protective film 42.
  • the side electrode 5 can be formed on the insulating protective film 4.
  • the region in which the side electrode 5 extends in the X direction can be adjusted.
  • each of the front electrode 2a and the back electrode 2b is composed of two layers, it is easy to control the inclination angle ⁇ .
  • FIG. 12 is a schematic cross-sectional view of the chip resistor 1a of the sixth embodiment.
  • FIG. 12 corresponds to FIG. 9.
  • the chip resistor 1a shown in FIG. 12 basically has the same configuration as the chip resistor 1a shown in FIG. 9 and can obtain the same effect, but is different in that the sputter layer arranged on the front electrode 2a and the back electrode 2b composed of three layers is also formed on the insulating protective film 4.
  • the first layers 51a and 52a are arranged on the first insulating protective film 41 and the second insulating protective film 42.
  • the side electrode 5 can be formed on the insulating protective film 4.
  • the region in which the side electrode 5 extends in the X direction can be adjusted.
  • each of the front electrode 2a and the back electrode 2b is composed of three layers, it is easy to control the inclination angle ⁇ .
  • Fig. 13 is a schematic cross-sectional view of the chip resistor 1a of the seventh embodiment.
  • Fig. 13 corresponds to Fig. 2.
  • the chip resistor 1a shown in Fig. 13 basically has the same configuration as the chip resistor 1a shown in Figs. 1 to 3 and can obtain the same effect, but differs in that the first resistive body 31 and the first insulating protective film 41 are not disposed on the surface 11. In this way, the resistance value of the chip resistor 1a is stable over the long term.
  • FIG. 14 is a schematic cross-sectional view of the chip resistor 1a of the eighth embodiment.
  • FIG. 14 corresponds to FIG. 8.
  • the chip resistor 1a shown in FIG. 14 basically has the same configuration as the chip resistor 1a shown in FIG. 8 and can obtain the same effect, but is different in that the first resistor 31 and the first insulating protective film 41 are not arranged on the front surface 11.
  • the front surface electrode 2a is composed of one layer
  • the back surface electrode 2b is composed of two layers. Since the back surface electrode 2b is composed of two layers, it is easy to control the inclination angle ⁇ .
  • the resistor 3 is arranged only on the back surface 12, the resistance value of the chip resistor 1a is stable over the long term.
  • FIG. 15 is a schematic cross-sectional view of the chip resistor 1a of the ninth embodiment.
  • FIG. 15 corresponds to FIG. 10.
  • the chip resistor 1a shown in FIG. 15 basically has the same configuration as the chip resistor 1a shown in FIG. 10 and can obtain the same effect, but is different in that the first resistor 31 and the first insulating protective film 41 are not arranged on the front surface 11. Since the resistor 3 is arranged only on the back surface 12, the resistance value of the chip resistor 1a is stable over a long period of time.
  • the first layers 51a and 52a are arranged on the second insulating protective film 42. Therefore, the side electrode 5 can be formed on the insulating protective film 4. As a result, the area in which the side electrode 5 extends in the X direction can be adjusted.
  • FIG. 16 is a schematic cross-sectional view of the chip resistor 1a of the tenth embodiment.
  • FIG. 16 corresponds to FIG. 11.
  • the chip resistor 1a shown in FIG. 16 basically has the same configuration as the chip resistor 1a shown in FIG. 11 and can obtain the same effect, but is different in that the first resistor 31 and the first insulating protective film 41 are not arranged on the front surface 11.
  • the front surface electrode 2a is composed of one layer
  • the back surface electrode 2b is composed of two layers. Since the back surface electrode 2b is composed of two layers, it is easy to control the inclination angle ⁇ .
  • the resistor 3 is arranged only on the back surface 12, the resistance value of the chip resistor 1a is stable over a long period of time.
  • the first layers 51a and 52a are arranged on the second insulating protective film 42. Therefore, the side electrode 5 can be formed on the insulating protective film 4. As a result, the area in which the side electrode 5 extends in the X direction can be adjusted.
  • FIG. 17 is a schematic cross-sectional view of the chip resistor 1a of the eleventh embodiment.
  • FIG. 17 corresponds to FIG. 13.
  • the chip resistor 1a shown in FIG. 17 basically has the same configuration as the chip resistor 1a shown in FIG. 13 and can obtain the same effect, but is different in that the conductive resin layer 60 is disposed on the back electrode 2b and the second insulating protective film 42.
  • the conductive resin layer 60 includes a first conductive resin layer 61 and a second conductive resin layer 62. With such a configuration, it is possible to adjust the region in which the side electrode 5 extends in the X direction. In addition, the conductive resin layer 60 suppresses the occurrence of cracks 400. As a result, the resistance value of the chip resistor 1a is stable over a long period of time.
  • the first conductive resin layer 61 is disposed on the first back electrode 23 and the second insulating protective film 42.
  • the second conductive resin layer 62 is disposed on the second back electrode 24 and the second insulating protective film 42.
  • the second conductive resin layer 62 is electrically insulated from the first conductive resin layer 61 by the second insulating protective film 42.
  • the first conductive resin layer 61 and the second conductive resin layer 62 contain a resin such as an epoxy resin, a phenolic resin, or a mixture of an epoxy resin and a phenolic resin, and conductive particles.
  • the conductive particles are, for example, metal particles such as silver particles or copper particles, carbon particles, or a combination thereof.
  • FIG. 18 is a schematic cross-sectional view of the chip resistor 1a of the twelfth embodiment.
  • FIG. 18 corresponds to FIG. 14.
  • the chip resistor 1a shown in FIG. 18 basically has the same configuration as the chip resistor 1a shown in FIG. 14 and can obtain the same effect, but is different in that the conductive resin layer 60 is disposed on the back electrode 2b and the second insulating protective film 42. With such a configuration, the region in which the side electrode 5 extends in the X direction can be adjusted.
  • the conductive resin layer 60 suppresses the occurrence of cracks 400.
  • the resistance value of the chip resistor 1a is stable over a long period of time.
  • the back electrode 2b is configured of two layers, it is easy to control the inclination angle ⁇ .
  • the first conductive resin layer 61 is disposed on the second electrode layer 23b and the second insulating protective film 42.
  • the second conductive resin layer 62 is disposed on the second electrode layer 24b and the second insulating protective film 42.
  • the second conductive resin layer 62 is electrically insulated from the first conductive resin layer 61 by the second insulating protective film 42.
  • appendices an insulating substrate including a front surface, a back surface disposed on the opposite side to the front surface, and a side surface connecting the front surface and the back surface; A resistor disposed on at least one of the front surface and the back surface; a back surface electrode disposed on the back surface; a side electrode disposed on the side and rear electrodes; If the direction perpendicular to the back surface is defined as the Z direction, the side electrode has a lowest point disposed at a position furthest from the rear surface in the Z direction; the side electrode has a bottom surface which is a region from the side surface to the bottom point, The bottom surface is inclined with respect to the back surface, the lowermost surface has a first region including the lowermost point; A chip resistor, wherein in the first region, an inclination angle of the bottom surface with respect to the back surface is greater than or equal to 1° and less than or equal to 10°.
  • the bottom surface has a second region disposed at a position closest to the side surface in the X direction, 2.
  • the chip resistor according to claim 1 wherein in the second region, an inclination angle of the bottom surface relative to the back surface is 5° or more.
  • the bottom surface has a third region disposed between the first region and the second region in the X direction, 3.
  • the chip resistor according to claim 2, wherein in the third region, an inclination angle of the bottom surface relative to the back surface is greater than or equal to 1° and less than or equal to 5°. (Appendix 4) 3.
  • a width of the first region is equal to or greater than half a distance from the side surface to the lowest point.
  • Appendix 5 5.
  • Appendix 6) 6.
  • Appendix 7) 5.
  • (Appendix 8) a surface electrode disposed on the surface; Further comprising an insulating protective film including a first insulating protective film and a second insulating protective film;
  • the side surface includes a first side surface and a second side surface disposed on an opposite side to the first side surface, the resistor includes a first resistor disposed on the front surface and a second resistor disposed on the back surface, the surface electrodes include a first surface electrode and a second surface electrode disposed apart from the first surface electrode in the X direction;
  • the rear surface electrode includes a first rear surface electrode and a second rear surface electrode arranged apart from the first rear surface electrode in the X direction,
  • the side electrodes include a first side electrode and a second side electrode, the first side electrode is disposed on the first side surface, the first back surface electrode, and the first front surface electrode;
  • the second side electrode is disposed on the second side surface, the second back surface electrode, and the second front surface electrode;
  • the first insulating protection film is disposed on the first

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PCT/JP2024/020148 2023-07-14 2024-06-03 チップ抵抗器 Pending WO2025018044A1 (ja)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55120101A (en) * 1979-03-09 1980-09-16 Matsushita Electric Industrial Co Ltd Method of manufacturing chip resistor
JPH02111005A (ja) * 1988-10-20 1990-04-24 Matsushita Electric Ind Co Ltd チップ型電子部品
JP2002025801A (ja) * 2000-07-10 2002-01-25 Matsushita Electric Ind Co Ltd 電子部品およびその実装体
JP2004056112A (ja) * 2002-05-30 2004-02-19 Matsushita Electric Ind Co Ltd 回路部品、回路部品実装体、および回路部品内蔵モジュールと、回路部品実装体および回路部品内蔵モジュールの製造方法
JP2008084905A (ja) * 2006-09-26 2008-04-10 Taiyosha Electric Co Ltd チップ抵抗器
JP2019160992A (ja) * 2018-03-13 2019-09-19 ローム株式会社 チップ抵抗器、およびチップ抵抗器の製造方法
JP2022116877A (ja) * 2021-01-29 2022-08-10 Koa株式会社 チップ部品

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55120101A (en) * 1979-03-09 1980-09-16 Matsushita Electric Industrial Co Ltd Method of manufacturing chip resistor
JPH02111005A (ja) * 1988-10-20 1990-04-24 Matsushita Electric Ind Co Ltd チップ型電子部品
JP2002025801A (ja) * 2000-07-10 2002-01-25 Matsushita Electric Ind Co Ltd 電子部品およびその実装体
JP2004056112A (ja) * 2002-05-30 2004-02-19 Matsushita Electric Ind Co Ltd 回路部品、回路部品実装体、および回路部品内蔵モジュールと、回路部品実装体および回路部品内蔵モジュールの製造方法
JP2008084905A (ja) * 2006-09-26 2008-04-10 Taiyosha Electric Co Ltd チップ抵抗器
JP2019160992A (ja) * 2018-03-13 2019-09-19 ローム株式会社 チップ抵抗器、およびチップ抵抗器の製造方法
JP2022116877A (ja) * 2021-01-29 2022-08-10 Koa株式会社 チップ部品

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