WO2025004696A1 - マルチレベルインバータ - Google Patents

マルチレベルインバータ Download PDF

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Publication number
WO2025004696A1
WO2025004696A1 PCT/JP2024/020138 JP2024020138W WO2025004696A1 WO 2025004696 A1 WO2025004696 A1 WO 2025004696A1 JP 2024020138 W JP2024020138 W JP 2024020138W WO 2025004696 A1 WO2025004696 A1 WO 2025004696A1
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Prior art keywords
switching element
capacitor
diode
control
switching
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PCT/JP2024/020138
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English (en)
French (fr)
Japanese (ja)
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WO2025004696A9 (ja
Inventor
裕一 中村
アナンタ ヘガデ
孝宗 椛島
朝実良 鈴木
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to EP24831566.5A priority Critical patent/EP4738681A1/en
Priority to JP2025529567A priority patent/JPWO2025004696A1/ja
Priority to CN202480039924.4A priority patent/CN121312054A/zh
Publication of WO2025004696A1 publication Critical patent/WO2025004696A1/ja
Publication of WO2025004696A9 publication Critical patent/WO2025004696A9/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters

Definitions

  • the present disclosure relates to a multilevel inverter, and more particularly to a multilevel inverter having a bootstrap circuit.
  • Patent Document 1 discloses a switching element drive circuit for a three-level neutral point clamped inverter in which first, second, third and fourth switching elements are connected in series between the positive and negative terminals of a DC power supply.
  • the switching element drive circuit includes an element drive power supply with the negative terminal as a potential reference, a fourth element drive section (fourth gate driver), a third diode, a third element drive section (third gate driver), a third capacitor, a second diode, a second element drive section (second gate driver), a second capacitor, a first diode, a first element drive section (first gate driver) and a first capacitor.
  • the fourth element drive section is connected between the positive and negative terminals of the element drive power supply and drives the fourth switching element.
  • the third diode has an anode connected to the positive terminal of the element drive power supply.
  • the third element drive section is connected between the cathode of the third diode and a common connection point of the third and fourth switching elements and drives the third switching element.
  • the third capacitor is connected in parallel to the third element driving unit.
  • the second diode has an anode connected to the cathode of the third diode.
  • the second element driving unit is connected between the cathode of the second diode and the common connection point of the second and third switching elements, and drives the second switching element.
  • the second capacitor is connected in parallel to the second element driving unit.
  • the first diode has an anode connected to the cathode of the second diode.
  • the first element driving unit is connected between the cathode of the first diode and the common connection point of the first and second switching elements, and drives the first switching element.
  • the first capacitor is connected in parallel to the first element driving unit.
  • the objective of this disclosure is to provide a multilevel inverter that can reduce switching losses.
  • a multilevel inverter includes a DC power supply unit, an inverter circuit, and a control device.
  • the DC power supply unit has a positive electrode, a negative electrode, and an intermediate potential point.
  • the inverter circuit is connected between the positive electrode and the negative electrode of the DC power supply unit.
  • the control device controls the inverter circuit.
  • the inverter circuit has a switching circuit, a first clamp diode, and a second clamp diode.
  • the switching circuit has a first switching element, a second switching element, a third switching element, and a fourth switching element.
  • the first switching element, the second switching element, the third switching element, and the fourth switching element are connected in series from the positive electrode side to the negative electrode side in the order of the first switching element, the second switching element, the third switching element, and the fourth switching element.
  • the first clamp diode is connected between a first connection point between the first switching element and the second switching element and the intermediate potential point.
  • the second clamp diode is connected between a second connection point between the third switching element and the fourth switching element and the intermediate potential point.
  • the control device includes a first gate driver, a second gate driver, a third gate driver, a fourth gate driver, a first bootstrap circuit, a second bootstrap circuit, a third bootstrap circuit, a power supply unit, and a control unit.
  • the first gate driver drives the first switching element.
  • the second gate driver drives the second switching element.
  • the third gate driver drives the third switching element.
  • the fourth gate driver drives the fourth switching element.
  • the first bootstrap circuit includes a first capacitor connected in parallel to the first gate driver and a first diode connected in series to the first capacitor.
  • the second bootstrap circuit includes a second capacitor connected in parallel to the second gate driver and a second diode connected in series to the second capacitor.
  • the third bootstrap circuit includes a third capacitor connected in parallel to the third gate driver and a third diode connected in series to the third capacitor.
  • the power supply unit is connected in parallel to the fourth gate driver.
  • the control unit controls the first gate driver, the second gate driver, the third gate driver, and the fourth gate driver.
  • the power supply unit is connected to the third capacitor through the third diode, connected to the second capacitor through the third diode and the second diode, and connected to the first capacitor through the third diode, the second diode, and the first diode.
  • the control unit has a function of performing initial charging control to initially charge the first capacitor, the second capacitor, and the third capacitor at startup.
  • the control unit performs a first control in which only the fourth switching element is turned on, and then only the third switching element and the fourth switching element are turned on, or a second control in which only the third switching element and the fourth switching element are turned on, and then alternately repeats a third control in which only the second switching element and the third switching element are turned on, and a fourth control in which only the third switching element and the fourth switching element are turned on.
  • the multilevel inverter disclosed herein has the effect of making it possible to reduce switching losses.
  • FIG. 1 is a circuit diagram of a system including a multilevel inverter according to an embodiment.
  • FIG. 2 is an explanatory diagram of a current path when the switching circuit is in a first switching state in the multilevel inverter of the embodiment.
  • FIG. 3 is an explanatory diagram of a discharge path and a charge path when the switching circuit is in the first switching state in the multilevel inverter of the embodiment.
  • FIG. 4 is an explanatory diagram of a current path when the switching circuit is in the second switching state in the multilevel inverter of the embodiment.
  • FIG. 5 is an explanatory diagram of a discharge path and a charge path when the switching circuit is in the second switching state in the multilevel inverter of the embodiment.
  • FIG. 6 is an explanatory diagram of a current path when the switching circuit is in the third switching state in the multilevel inverter of the embodiment.
  • FIG. 7 is an explanatory diagram of a discharge path and a charge path when the switching circuit is in the third switching state in the multilevel inverter of the embodiment.
  • FIG. 8 is an explanatory diagram of voltage command values for each phase in the multilevel inverter of the embodiment.
  • FIG. 9 is an illustration of a set of voltage vectors for a multilevel inverter of an embodiment.
  • FIG. 10 is a more detailed illustration of a set of voltage vectors for a multilevel inverter of an embodiment.
  • FIG. 11 is a vector diagram for explaining the operation of the control unit in the multilevel inverter of the embodiment.
  • FIG. 12 is a diagram showing a time chart of the switching state of each phase of the multilevel inverter of the embodiment.
  • FIG. 13 is a diagram showing a time chart of the on/off states of the first to fourth switching elements of the multilevel inverter of the embodiment.
  • FIG. 14 is an explanatory diagram of a charging path of the third capacitor when the control unit turns on only the fourth switching element in the initial charging control in the multilevel inverter of the embodiment.
  • FIG. 15 is an explanatory diagram of a charging path of the second capacitor and a charging path of the third capacitor when the control unit turns on only the third switching element and the fourth switching element in the initial charging control in the multilevel inverter of the embodiment.
  • FIG. 14 is an explanatory diagram of a charging path of the third capacitor when the control unit turns on only the fourth switching element in the initial charging control in the multilevel inverter of the embodiment.
  • FIG. 15 is an explanatory diagram of a charging path of the second capacitor and a charging path of the third capacitor when the
  • FIG. 16 is an explanatory diagram of a charging path of the first capacitor and a charging path of the second capacitor when the control unit turns on only the second switching element and the third switching element in the initial charging control in the multilevel inverter of the embodiment.
  • FIG. 17 is an operational waveform diagram when the control unit performs an initial charging operation in the multilevel inverter of the embodiment.
  • FIG. 1 is a circuit diagram of a system including a multilevel inverter 100 according to an embodiment.
  • the multilevel inverter 100 includes a DC power supply unit 3, a plurality of (three in the example of FIG. 1) inverter circuits 1, and a control device 6.
  • the DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1.
  • the plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3.
  • the control device 6 controls the plurality of inverter circuits 1.
  • the "intermediate potential point M1" is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3.
  • the multilevel inverter 100 is a three-level, three-phase inverter of a diode clamp type.
  • each of the multiple inverter circuits 1 has an output terminal 41.
  • an AC load RA1 is connected to multiple (three in the example of FIG. 1) output terminals 41.
  • the AC load RA1 is, for example, a three-phase servo motor.
  • one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining one is an inverter circuit 1W that outputs a W-phase voltage.
  • Each of the multiple inverter circuits 1 has a switching circuit 10, a first clamp diode D5, and a second clamp diode D6.
  • the potential of the intermediate potential point M1 is clamped by the first clamp diode D5 and the second clamp diode D6 of each inverter circuit 1.
  • Each switching circuit 10 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4.
  • the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series from the positive pole P1 side to the negative pole N1 side of the DC power supply unit 3 in the order of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4.
  • Each switching circuit 10 further includes four diodes D1 to D4.
  • Diode D1 is connected in anti-parallel to the first switching element Q1.
  • Diode D2 is connected in anti-parallel to the second switching element Q2.
  • Diode D3 is connected in anti-parallel to the third switching element Q3.
  • Diode D4 is connected in anti-parallel to the fourth switching element Q4.
  • the first clamp diode D5 is connected between the first connection point 11 between the first switching element Q1 and the second switching element Q2 and the intermediate potential point M1.
  • the second clamp diode D6 is connected between the second connection point 12 between the third switching element Q3 and the fourth switching element Q4 and the intermediate potential point M1.
  • the control device 6 has a plurality of first gate drivers 61 (three in the example of FIG. 1), a plurality of second gate drivers 62 (three in the example of FIG. 1), a plurality of third gate drivers 63 (three in the example of FIG. 1), and a plurality of fourth gate drivers 64 (three in the example of FIG. 1).
  • the control device 6 also has a plurality of first bootstrap circuits 71 (three in the example of FIG. 1), a plurality of second bootstrap circuits 72 (three in the example of FIG. 1), a plurality of third bootstrap circuits 73 (three in the example of FIG. 1), a power supply unit 9, and a control unit 60.
  • the multiple first gate drivers 61 drive the first switching element Q1 of each of the multiple inverter circuits 1.
  • the multiple second gate drivers 62 drive the second switching element Q2 of each of the multiple inverter circuits 1.
  • the multiple third gate drivers 63 drive the third switching element Q3 of each of the multiple inverter circuits 1.
  • the multiple fourth gate drivers 64 drive the fourth switching element Q4 of each of the multiple inverter circuits 1.
  • the first bootstrap circuits 71 correspond one-to-one to the first gate drivers 61.
  • Each of the first bootstrap circuits 71 includes a first capacitor C17 connected in parallel to the corresponding first gate driver 61 and a first diode D17 connected in series to the first capacitor C17.
  • the second bootstrap circuits 72 correspond one-to-one to the second gate drivers 62.
  • Each of the second bootstrap circuits 72 includes a second capacitor C27 connected in parallel to the corresponding second gate driver 62 and a second diode D27 connected in series to the second capacitor C27.
  • the third bootstrap circuits 73 correspond one-to-one to the third gate drivers 63.
  • Each of the third bootstrap circuits 73 includes a third capacitor C37 connected in parallel to the corresponding third gate driver 63 and a third diode D37 connected in series to the third capacitor C37.
  • the power supply unit 9 is connected in parallel to the fourth gate driver 64.
  • the power supply unit 9 is also connected to the third capacitor C37 via the third diode D37.
  • the power supply unit 9 is also connected to the second capacitor C27 via the third diode D37 and the second diode D27.
  • the power supply unit 9 is also connected to the first capacitor C17 via the third diode D37, the second diode D27, and the first diode D17.
  • the control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64.
  • the DC power supply unit 3 has a fourth capacitor C1 and a fifth capacitor C2.
  • the fourth capacitor C1 and the fifth capacitor C2 are connected in series.
  • the DC power supply unit 3 further has a first DC terminal 31 connected to the positive pole P1 and a second DC terminal 32 connected to the negative pole N1.
  • a first end of the fourth capacitor C1 is connected to the first DC terminal 31
  • a second end of the fourth capacitor C1 is connected to the first end of the fifth capacitor C2
  • a second end of the fifth capacitor C2 is connected to the second DC terminal 32.
  • the connection point between the fourth capacitor C1 and the fifth capacitor C2 is the intermediate potential point M1.
  • a DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32.
  • the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3.
  • the capacitance of the fifth capacitor C2 is the same as the capacitance of the fourth capacitor C1.
  • the capacitance of the fifth capacitor C2 is the same as the capacitance of the fourth capacitor C1
  • the switching circuit 10 included in inverter circuit 1U may be referred to as switching circuit 10U
  • the switching circuit 10 included in inverter circuit 1V may be referred to as switching circuit 10V
  • the switching circuit 10 included in inverter circuit 1W may be referred to as switching circuit 10W
  • the output terminal 41 included in inverter circuit 1U may be referred to as output terminal 41U
  • the output terminal 41 included in inverter circuit 1V may be referred to as output terminal 41V
  • the output terminal included in inverter circuit 1W may be referred to as output terminal 41W.
  • the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 have a control terminal, a first main terminal, and a second main terminal.
  • the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, for example, insulated gate bipolar transistors (IGBTs). Therefore, the control terminal, the first main terminal, and the second main terminal of each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are the gate terminal, the collector terminal, and the emitter terminal, respectively.
  • IGBTs insulated gate bipolar transistors
  • the control terminal of the first switching element Q1 of each switching circuit 10 is connected to a corresponding first gate driver 61 of the multiple first gate drivers 61.
  • the control terminal of the second switching element Q2 of each switching circuit 10 is connected to a corresponding second gate driver 62 of the multiple second gate drivers 62.
  • the control terminal of the third switching element Q3 of each switching circuit 10 is connected to a corresponding third gate driver 63 of the multiple third gate drivers 63.
  • the control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to a corresponding fourth gate driver 64 of the multiple fourth gate drivers 64.
  • the first main terminal of the first switching element Q1 is connected to the positive pole P1 of the DC power supply unit 3, and the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2. Also, in each switching circuit 10, the second main terminal of the second switching element Q2 is connected to the first main terminal of the third switching element Q3. Also, in each switching circuit 10, the second main terminal of the third switching element Q3 is connected to the first main terminal of the fourth switching element Q4, and the second main terminal of the fourth switching element Q4 is connected to the negative pole N1 of the DC power supply unit 3.
  • the third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10U is connected to the output terminal 41U.
  • the third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10V is connected to the output terminal 41V.
  • the third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10W is connected to the output terminal 41W.
  • the third connection point 13 of the inverter circuit 1U is connected to, for example, the U phase of the AC load RA1 via the output terminal 41U.
  • the third connection point 13 of the inverter circuit 1V is connected to, for example, the V phase of the AC load RA1 via the output terminal 41V.
  • the third connection point 13 of the inverter circuit 1W is connected to, for example, the W phase of the AC load RA1 via the output terminal 41W.
  • the anode of diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1.
  • the anode of diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2.
  • the anode of diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3.
  • the anode of diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.
  • the diode D1 may be replaced by a parasitic diode of the IGBT that constitutes the first switching element Q1.
  • the diode D2 may be replaced by a parasitic diode of the IGBT that constitutes the second switching element Q2.
  • the diode D3 may be replaced by a parasitic diode of the IGBT that constitutes the third switching element Q3.
  • the diode D4 may be replaced by a parasitic diode of the IGBT that constitutes the fourth switching element Q4.
  • the cathode of the first clamp diode D5 is connected to the first connection point 11 between the first switching element Q1 and the second switching element Q2.
  • the anode of the first clamp diode D5 is connected to the intermediate potential point M1 of the DC power supply unit 3.
  • the intermediate potential point M1 is connected to ground, the potential of the intermediate potential point M1 is 0V.
  • the potential of the positive electrode P1 is Vdc/2
  • the potential of the negative electrode N1 is -Vdc/2.
  • the cathode of the second clamp diode D6 is connected to the intermediate potential point M1.
  • the anode of the second clamp diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.
  • the multiple first gate drivers 61 correspond one-to-one to the multiple first switching elements Q1. Each of the multiple first gate drivers 61 is connected to a control terminal of the corresponding first switching element Q1. Each of the multiple first gate drivers 61 drives the corresponding first switching element Q1.
  • the multiple first gate drivers 61 are connected to the control unit 60.
  • the control unit 60 outputs multiple first control signals S1 (see FIG. 2) that correspond one-to-one to the multiple first gate drivers 61.
  • Each of the multiple first gate drivers 61 controls the on/off of the first switching element Q1 based on the given first control signal S1.
  • the second gate drivers 62 correspond one-to-one to the second switching elements Q2. Each of the second gate drivers 62 is connected to a control terminal of the corresponding second switching element Q2. Each of the second gate drivers 62 drives the corresponding second switching element Q2.
  • the second gate drivers 62 are connected to the control unit 60.
  • the control unit 60 outputs second control signals S2 (see FIG. 2) that correspond one-to-one to the second gate drivers 62.
  • Each of the second gate drivers 62 controls the on/off of the second switching element Q2 based on the second control signal S2 provided.
  • the multiple third gate drivers 63 correspond one-to-one to the multiple third switching elements Q3. Each of the multiple third gate drivers 63 is connected to the control terminal of the corresponding third switching element Q3. Each of the multiple third gate drivers 63 drives the corresponding third switching element Q3.
  • the multiple third gate drivers 63 are connected to the control unit 60.
  • the control unit 60 outputs multiple third control signals S3 (see FIG. 2) that correspond one-to-one to the multiple third gate drivers 63.
  • Each of the multiple third gate drivers 63 controls the on/off of the third switching element Q3 based on the provided third control signal S3.
  • the multiple fourth gate drivers 64 correspond one-to-one to the multiple fourth switching elements Q4. Each of the multiple fourth gate drivers 64 is connected to the control terminal of the corresponding fourth switching element Q4. Each of the multiple fourth gate drivers 64 drives the corresponding fourth switching element Q4.
  • the multiple fourth gate drivers 64 are connected to the control unit 60.
  • the control unit 60 outputs multiple fourth control signals S4 (see FIG. 2) that correspond one-to-one to the multiple fourth gate drivers 64.
  • Each of the multiple fourth gate drivers 64 controls the on/off of the fourth switching element Q4 based on the provided fourth control signal S4.
  • Each of the multiple first bootstrap circuits 71 supplies a voltage to a corresponding one of the multiple first gate drivers 61.
  • Each of the multiple first bootstrap circuits 71 has a first resistor R17 in addition to a first capacitor C17 and a first diode D17.
  • each first bootstrap circuit 71 the anode of the first diode D17 is connected to the positive terminal of the power supply unit 9 via the second diode D27 and the third diode D37.
  • the cathode of the first diode D17 is connected to the first end of the first capacitor C17 via the first resistor R17.
  • the first end of the first capacitor C17 is connected to the high-potential side power supply terminal 61H (see FIG. 3) of the first gate driver 61.
  • the second end of the first capacitor C17 is connected to the low-potential side power supply terminal 61L (see FIG. 3) of the first gate driver 61.
  • the first bootstrap circuit 71 supplies the first gate driver 61 with a voltage (a voltage greater than the threshold voltage of the first switching element Q1) required to turn on the first switching element Q1 in the first gate driver 61.
  • Each of the multiple first bootstrap circuits 71 further has a first Zener diode Z17 connected in parallel to the first capacitor C17.
  • the cathode of the first Zener diode Z17 is connected to the first end of the first capacitor C17, and the anode of the first Zener diode Z17 is connected to the second end of the first capacitor C17.
  • Each of the second bootstrap circuits 72 supplies a voltage to a corresponding one of the second gate drivers 62.
  • Each of the second bootstrap circuits 72 has a second resistor R27 in addition to a second capacitor C27 and a second diode D27.
  • the anode of the second diode D27 is connected to the positive terminal of the power supply unit 9 via a third diode D37.
  • the cathode of the second diode D27 is connected to a first end of the second capacitor C27 via a second resistor R27.
  • the first end of the second capacitor C27 is connected to the high potential side power supply terminal 62H (see FIG. 3) of the second gate driver 62.
  • the second end of the second capacitor C27 is connected to the low potential side power supply terminal 62L (see FIG. 3) of the second gate driver 62.
  • the second bootstrap circuit 72 supplies the second gate driver 62 with a voltage (a voltage greater than the threshold voltage of the second switching element Q2) required to turn on the second switching element Q2 in the second gate driver 62.
  • Each of the second bootstrap circuits 72 further includes a second Zener diode Z27 connected in parallel to the second capacitor C27. In each of the second bootstrap circuits 72, the cathode of the second Zener diode Z27 is connected to the first end of the second capacitor C27, and the anode of the second Zener diode Z27 is connected to the second end of the second capacitor C27.
  • Each of the multiple third bootstrap circuits 73 supplies a voltage to a corresponding third gate driver 63 among the multiple third gate drivers 63.
  • Each of the multiple third bootstrap circuits 73 has a third resistor R37 in addition to a third capacitor C37 and a third diode D37.
  • the anode of the third diode D37 is connected to the positive terminal of the power supply unit 9.
  • the cathode of the third diode D37 is connected to a first end of the third capacitor C37 via the third resistor R37.
  • the first end of the third capacitor C37 is connected to the high potential side power supply terminal 63H (see FIG. 3) of the third gate driver 63.
  • the second end of the third capacitor C37 is connected to the low potential side power supply terminal 63L (see FIG. 3) of the third gate driver 63.
  • the third bootstrap circuit 73 supplies the third gate driver 63 with a voltage (a voltage greater than the threshold voltage of the third switching element Q3) required to turn on the third switching element Q3 in the third gate driver 63.
  • Each of the third bootstrap circuits 73 further includes a third Zener diode Z37 connected in parallel to the third capacitor C37. In each of the third bootstrap circuits 73, the cathode of the third Zener diode Z37 is connected to the first end of the third capacitor C37, and the anode of the third Zener diode Z37 is connected to the second end of the third capacitor C37.
  • the power supply unit 9 is, for example, a DC power supply including an insulated DC-DC converter 91.
  • the positive terminal of the power supply unit 9 is connected to the high potential side power supply terminal 64H (see FIG. 3) of each of the multiple fourth gate drivers 64.
  • the positive terminal of the power supply unit 9 is also connected to the first end of the third capacitor C37 via the third diode D37 and the third resistor R37.
  • the positive terminal of the power supply unit 9 is also connected to the first end of the second capacitor C27 via the third diode D37, the second diode D27, and the second resistor R27.
  • the positive terminal of the power supply unit 9 is also connected to the first end of the first capacitor C17 via the third diode D37, the second diode D27, the first diode D17, and the first resistor R17.
  • the negative terminal of the power supply unit 9 is connected to the low potential side power supply terminal 64L (see FIG. 3) of each of the multiple fourth gate drivers 64.
  • the negative terminal of the power supply unit 9 is also connected to the negative pole N1 of the DC power supply unit 3.
  • the control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64.
  • the control unit 60 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4.
  • the execution subject of the control unit 60 includes a computer system.
  • the computer system has one or more computers.
  • the computer system is mainly composed of a processor and a memory as hardware.
  • the processor executes a program recorded in the memory of the computer system, thereby realizing the function of the control unit 60 as the execution subject in this disclosure.
  • the program may be pre-recorded in the memory of the computer system, or may be provided through an electric communication line, or may be recorded and provided on a non-transitory recording medium such as a memory card, an optical disk, or a hard disk drive (magnetic disk) that can be read by the computer system.
  • the processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI).
  • the multiple electronic circuits may be integrated into one chip, or may be distributed across multiple chips.
  • the multiple chips may be integrated into one device, or may be distributed across multiple devices.
  • the control unit 60 outputs a plurality (three) of first control signals S1 (see FIG. 2) for controlling a plurality (three) of first switching elements Q1.
  • the control unit 60 also outputs a plurality (three) of second control signals S2 (see FIG. 2) for controlling a plurality (three) of second switching elements Q2.
  • the control unit 60 also outputs a plurality (three) of third control signals S3 (see FIG. 2) for controlling a plurality of third switching elements Q3.
  • the control unit 60 also outputs a plurality (three) of fourth control signals S4 for controlling a plurality (three) of fourth switching elements Q4. Note that FIG. 2 shows only one inverter circuit 1 of the three inverter circuits 1 (see FIG.
  • the two first gate drivers 61, the two second gate drivers 62, the two third gate drivers 63, the two fourth gate drivers 64, the two first bootstrap circuits 71, the two second bootstrap circuits 72, and the two third bootstrap circuits 73 shown in FIG. 1 are omitted.
  • the three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the switching circuit 10U, a first control signal S1V that controls the first switching element Q1 of the switching circuit 10V, and a first control signal S1W that controls the first switching element Q1 of the switching circuit 10W.
  • the three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the switching circuit 10U, a second control signal S2V that controls the second switching element Q2 of the switching circuit 10V, and a second control signal S2W that controls the second switching element Q2 of the switching circuit 10W.
  • the three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the switching circuit 10U, a third control signal S3V that controls the third switching element Q3 of the switching circuit 10V, and a third control signal S3W that controls the third switching element Q3 of the switching circuit 10W.
  • the three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the switching circuit 10U, a fourth control signal S4V that controls the fourth switching element Q4 of the switching circuit 10V, and a fourth control signal S4W that controls the fourth switching element Q4 of the switching circuit 10W.
  • Each of the multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level.
  • the first potential level is, for example, 0V
  • the second potential level is a potential level greater than the gate threshold voltage of the IGBT. That is, for each of the multiple control signals (multiple first control signals S1, multiple second control signals S2, multiple third control signals S3, and multiple fourth control signals S4), the first potential level is a potential level for turning off the switching element corresponding to that control signal, and the second potential level is a potential level for turning on the switching element corresponding to that control signal.
  • Each of the multiple first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level, and turned off when it is at a low level.
  • Each of the multiple second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level, and turned off when it is at a low level.
  • Each of the multiple third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level, and turned off when it is at a low level.
  • Each of the multiple fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level, and turned off when it is at a low level.
  • the control unit 60 performs a charge control operation for charging the multiple first capacitors C17, the multiple second capacitors C27, and the multiple third capacitors C37 as a startup operation of the multilevel inverter 100, and an inverter control operation for causing an output current to flow to each of the multiple output terminals 41 as a steady-state operation of the multilevel inverter 100.
  • each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the multilevel inverter 100, the switching state of the switching circuit 10 in each of the three inverter circuits 1U, 1V, and 1W is controlled to any one of a first switching state, a second switching state, and a third switching state.
  • the first switching state, the second switching state, and the third switching state are different in combination of the on-off states of the first to fourth switching elements Q1 to Q4.
  • the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from each other. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes in three levels depending on the states of the first to fourth switching elements Q1 to Q4. Regarding the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other.
  • the first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the on state, and both the third switching element Q3 and the fourth switching element Q4 are in the off state.
  • each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3.
  • each of the multiple inverter circuits 1 has the potential of the third connection point 13 at the potential level of the positive electrode P1 of the DC power supply unit 3 (e.g., Vdc/2).
  • the second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the off state, and both the second switching element Q2 and the third switching element Q3 are in the on state.
  • each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3.
  • the potential of the third connection point 13 becomes the potential level of the intermediate potential point M1 (e.g., 0).
  • the third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the off state, and both the third switching element Q3 and the fourth switching element Q4 are in the on state.
  • each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3.
  • each of the multiple inverter circuits 1 has the potential of the third connection point 13 at the potential level of the negative electrode N1 of the DC power supply unit 3 (for example, -Vdc/2).
  • FIG 2 is an explanatory diagram of the current path when the switching circuit 10 is in the first switching state in the multilevel inverter 100 of the embodiment.
  • a current I1 flows through the path from the positive pole P1 of the DC power supply unit 3 - the first switching element Q1 - the second switching element Q2 - the third connection point 13 - the output terminal 41, and the voltage value of the output voltage to the AC load RA1 (see Figure 1) becomes approximately Vdc/2.
  • the first gate driver 61 supplies the first capacitor C17 of the first bootstrap circuit 71 with a voltage required for turning on the first switching element Q1. Therefore, the charge of the first capacitor C17 of the first bootstrap circuit 71 is discharged through the first discharge path Ru1 shown in FIG. 3.
  • the first discharge path Ru1 is the path from the first capacitor C17 to the high potential side power supply terminal 61H of the first gate driver 61 to the low potential side power supply terminal 61L of the first gate driver 61 to the first capacitor C17.
  • the voltage Vo1 across the first capacitor C17 in the first bootstrap circuit 71 decreases over time.
  • the second capacitor C27 of the second bootstrap circuit 72 supplies the second gate driver 62 with a voltage required for turning on the second switching element Q2 by the second gate driver 62. Therefore, the charge of the second capacitor C27 is discharged through the second discharge path Ru2 shown in FIG. 3.
  • the second discharge path Ru2 is a path from the second capacitor C27 to the high potential side power supply terminal 62H of the second gate driver 62 to the low potential side power supply terminal 62L of the second gate driver 62 to the second capacitor C27.
  • the voltage Vo2 across the second capacitor C27 in the second bootstrap circuit 72 decreases over time.
  • FIG. 3 is an explanatory diagram of the discharge path and the charge path when the switching circuit 10 is in the first switching state in the multilevel inverter 100 of the embodiment.
  • the switching circuit 10 of the inverter circuit 1 When the switching circuit 10 of the inverter circuit 1 is in the first switching state, the first capacitor C17 is charged by the second capacitor C27 if the first condition is satisfied.
  • the first condition As shown in FIG. 3, if the voltage across the first diode D17 is Vd1, the voltage across the first resistor R17 is VR1, and the voltage across the second switching element Q2 is Vf2, the first condition is Vo2>(Vo1+Vd1+VR1+Vf2).
  • the charge path Ru21 that charges the first capacitor C17 by the second capacitor C27 is the path of the second capacitor C27-second resistor R27-first diode D17-first resistor R17-first capacitor C17-first connection point 11-second switching element Q2-second capacitor C27.
  • FIG. 4 is an explanatory diagram of a current path when the switching circuit 10 is in the second switching state in the multilevel inverter 100 of the embodiment.
  • the switching circuit 10 of the inverter circuit 1 When the switching circuit 10 of the inverter circuit 1 is in the second switching state and the polarity of the output current is positive, as shown in FIG. 4, the current I1 flows through the path (indicated by the thick solid arrow) of the intermediate potential point M1 of the DC power supply unit 3-the first clamp diode D5-the second switching element Q2-the third connection point 13-the output terminal 41, and the voltage value of the output voltage to the AC load RA1 becomes 0.
  • the current I1 flows through the path of the intermediate potential point M1 of the DC power supply unit 3-the first clamp diode D5 of the inverter circuit 1U-the second switching element Q2 of the switching circuit 10U-the third connection point 13-the output terminal 41.
  • the switching circuits 10U, 10V, and 10W are in the second switching state, second switching state, and first switching state, respectively, in the inverter circuit 1U, the current I1 flows through the path of the output terminal 41-third connection point 13-third switching element Q3-second connection point 12-second clamp diode D6, and the voltage value of the output voltage to the AC load RA1 becomes 0.
  • FIG. 5 is an explanatory diagram of the discharge path and the charge path when the switching circuit 10 is in the second switching state in the multilevel inverter 100 of the embodiment.
  • the second gate driver 62 supplies the second capacitor C27 of the second bootstrap circuit 72 with a voltage required for turning on the second switching element Q2. Therefore, the charge of the second capacitor C27 is discharged through the second discharge path Ru2 shown in FIG. 5.
  • the second discharge path Ru2 is a path from the second capacitor C27-the high potential side power supply terminal 62H of the second gate driver 62-the low potential side power supply terminal 62L of the second gate driver 62-the second capacitor C27. As the charge of the second capacitor C27 is discharged, the voltage Vo2 across the second capacitor C27 in the second bootstrap circuit 72 decreases over time.
  • the third capacitor C37 of the third bootstrap circuit 73 supplies the third gate driver 63 with a voltage required for turning on the third switching element Q3. Therefore, the charge in the third capacitor C37 is discharged through the third discharge path Ru3 shown in FIG. 5.
  • the third discharge path Ru3 is a path from the third capacitor C37-the high potential side power supply terminal 63H of the third gate driver 63-the low potential side power supply terminal 63L of the third gate driver 63-the third capacitor C37. As the charge in the third capacitor C37 is discharged, the voltage Vo3 across the third capacitor C37 in the third bootstrap circuit 73 decreases over time.
  • the second capacitor C27 is charged by the third capacitor C37 if the second condition is met, and the first capacitor C17 is charged by the second capacitor C27 if the third condition is met.
  • the second condition is Vo3>(Vo2+Vd2+VR2+Vf3).
  • the third condition is Vo2>(Vo1+Vd1+VR1+Vf2).
  • the charging path Ru32 which charges the second capacitor C27 by the third capacitor C37, is the path of the third capacitor C37-third resistor R37-second diode D27-second resistor R27-second capacitor C27-third connection point 13-third switching element Q3-third capacitor C37.
  • the charging path Ru21 which charges the first capacitor C17 by the second capacitor C27, is the path of the second capacitor C27-second resistor R27-first diode D17-first resistor R17-first capacitor C17-first connection point 11-second switching element Q2-second capacitor C27.
  • FIG. 6 is an explanatory diagram of the current path when the switching circuit 10 is in the third switching state in the multilevel inverter 100 of the embodiment.
  • a current I1 flows through the path of the output terminal 41-the third connection point 13-the third switching element Q3-the fourth switching element Q4-the negative pole N1 of the DC power supply unit 3, and the voltage value of the output voltage to the AC load RA1 becomes -Vdc/2.
  • FIG. 7 is an explanatory diagram of the discharge path and the charge path when the switching circuit 10 is in the third switching state in the multilevel inverter 100 of the embodiment.
  • the switching circuit 10 of the inverter circuit 1 When the switching circuit 10 of the inverter circuit 1 is in the third switching state, the second capacitor C27 of the second bootstrap circuit 72 (see FIG. 1) is charged by the third capacitor C37, so that the voltage Vo2 across the second capacitor C27 rises over time, and the second capacitor C27 is fully charged.
  • the third capacitor C37 of the third bootstrap circuit 73 supplies the third gate driver 63 with a voltage required to turn on the third switching element Q3 by the third gate driver 63.
  • the discharge path Ru3 is a path from the third capacitor C37-the high potential side power supply terminal 63H of the third gate driver 63-the low potential side power supply terminal 63L of the third gate driver 63-the third capacitor C37.
  • the fourth condition is Voo>(Vo3+Vd3+VR3+Vf4).
  • the fifth condition is Vo3>(Vo2+Vd2+VR2+Vf3).
  • the charging path Ru93 for charging the third capacitor C37 by the power supply unit 9 is a path from the positive terminal of the power supply unit 9 to the third diode D37, the third resistor R37, the third capacitor C37, the second connection point 12, the fourth switching element Q4, and the negative terminal of the power supply unit 9.
  • the charging path Ru32 for charging the second capacitor C27 by the third capacitor C37 is a path from the third capacitor C37 to the third resistor R37, the second diode D27, the second resistor R27, the second capacitor C27, the third connection point 13, the third switching element Q3, and the third capacitor C37.
  • the control unit 60 generates first to fourth control signals S1 to S4 (S1U to S4U) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U based on a voltage command Vu (see FIG. 8) related to the output voltage of the inverter circuit 1U.
  • the control unit 60 also generates first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V based on a voltage command Vv (see FIG. 8) related to the output voltage of the inverter circuit 1V.
  • the control unit 60 also generates first to fourth control signals S1 to S4 (S1W to S4W) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W based on a voltage command Vw (see FIG. 8) related to the output voltage of the inverter circuit 1W.
  • the control unit 60 may perform PI (Proportional Integral) control of the voltage commands Vu, Vv, and Vw based on information output from the detection unit 8 that detects the state of the AC load RA1.
  • PI Proportional Integral
  • the information output from the detection unit 8 includes, for example, at least one of the following: information on the detection results of a plurality of current sensors that detect the output currents flowing through the U-phase, V-phase, and W-phase of the AC load RA1; and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.
  • one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U) will be described.
  • the operation of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W is similar to the operation of the U-phase inverter circuit 1U.
  • the output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with each other.
  • the control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control.
  • the voltage vector control by the control unit 60 is explained in more detail below.
  • the control unit 60 stores a group of voltage vectors in advance.
  • Each of the group of voltage vectors is determined by a combination of the potential levels of the connection point (third connection point 13) between the second switching element Q2 and the third switching element Q3 of the multiple inverter circuits 1.
  • the group of voltage vectors is determined by the switching state of the switching circuit 10U corresponding to the U phase, the switching state of the switching circuit 10V corresponding to the V phase, and the switching state of the switching circuit 10W corresponding to the W phase.
  • the group of voltage vectors includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of zero.
  • the group of voltage vectors also includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which has a magnitude of (2/3)1/2 ⁇ 2 Vdc and has different directions.
  • the group of voltage vectors also includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2/3)1/2 ⁇ Vdc.
  • the group of voltage vectors includes six voltage vectors V13, V14, V15, V16, V17, and V18, each of which has a magnitude of (2/3)1/2 ⁇ 31/2 ⁇ Vdc and a different direction.
  • the angle between two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees.
  • FIG. 9 is a vector diagram illustrating the group of voltage vectors on an orthogonal d-q coordinate system.
  • the group of voltage vectors can be expressed as shown in Figure 10 by expressing the first switching state, the second switching state, and the third switching state with the symbols "P", “0", and “N”, respectively, and listing the U phase, V phase, and W phase in that order.
  • V0p[PPP] expresses that, with respect to the zero vector V0p, the switching state of the U-phase switching circuit 10U is "P", the switching state of the V-phase switching circuit 10V is "P”, and the switching state of the W-phase switching circuit 10W is "P".
  • a voltage vector with "p" attached, such as V10p includes "P” and does not include "N”. This point is the same below.
  • a voltage vector with "n” attached such as V10n, includes the switching state “N” and does not include the switching state "P". This point is the same below.
  • voltage vectors with “o” attached such as V10o, include “0” and do not include “P” or “N”.
  • the switching state of the switching circuit 10 is "P"
  • the potential of the third connection point 13 in the switching circuit 10 is the potential of the positive pole P1 of the DC power supply unit 3.
  • the potential of the third connection point 13 in the switching circuit 10 is the potential of the negative pole N1 of the DC power supply unit 3.
  • the switching state of the switching circuit 10 is "0"
  • the potential of the third connection point 13 in the switching circuit 10 is the potential of the intermediate potential point M1 of the DC power supply unit 3.
  • V1, V2, V3, V4, V5, and V6 can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively.
  • Voltage vectors that do not have "p,” "n,” or "o” added after the number added to "V,” such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP] include "P" and "N” as the switching states of the three phases.
  • the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively.
  • V13, V14, V15, V16, V17, and V18 can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0], respectively.
  • FIG. 11 is a vector diagram for explaining the operation of the control unit 60 in the multilevel inverter 100 of the embodiment.
  • the control unit 60 converts the instantaneous value of the command voltage related to the output voltage of each of the multiple inverter circuits 1 into a command voltage vector V* (see FIG. 11). If the d-axis component of the command voltage vector V* on the orthogonal d-q coordinate system is Vd and the q-axis component of the command voltage vector V* on the orthogonal d-q coordinate system is Vq, the command voltage vector V* can be found using equation (1).
  • the control unit 60 selects multiple (e.g., five) voltage vectors from the group of voltage vectors that are adjacent to the command voltage vector V*.
  • the multiple voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN].
  • the angle between the voltage vector closest to the command voltage vector V* (hereinafter also referred to as voltage vector VV1) and the command voltage vector V* is less than 30 degrees.
  • the control unit 60 within a given control period Ts, matches the composite vector of the vectors of the vertices of an equilateral triangle surrounding the command voltage vector V* with the command voltage vector V*. That is, the control unit 60 matches the composite vector of the voltage vector VV1 (V8p[PP0] and V8n[00N] in the example of FIG. 11), the voltage vector V13[P0N], and the voltage vectors V7p[P00] and V7n[0NN] with the command voltage vector V*.
  • the control period Ts is one period of the carrier signal.
  • the switching state of only one of the U, V, and W phases in the two voltage vectors arranged in time series changes between "P" and "0” or between "0” and “N", and the same voltage vector is output twice.
  • FIG. 12 is a diagram showing a time chart of the switching state of each phase of the multilevel inverter 100 of the embodiment.
  • FIG. 13 is a diagram showing a time chart of the on-off state of the first to fourth switching elements (Q1 to Q4) of the multilevel inverter 100 of the embodiment.
  • the voltage vector V8n [00N] ⁇ voltage vector V13 [P0N] ⁇ voltage vector V7p [P00] ⁇ voltage vector V8p [PP0] ⁇ voltage vector V8p [PP0] ⁇ voltage vector V7p [P00] ⁇ voltage vector V13 [P0N] ⁇ voltage vector V8n [00N] is output in this order.
  • FIG. 12 is a diagram showing a time chart of the switching state of each phase of the multilevel inverter 100 of the embodiment.
  • FIG. 13 is a diagram showing a time chart of the on-off state of the first to fourth switching elements (Q1 to Q4) of the multilevel inverter 100 of the embodiment.
  • the voltage vector Va is the voltage vector V8p[PP0] and V8n[00N]
  • the voltage vector Vb is the voltage vector V13[P0N]
  • the voltage vector Vc is the voltage vector V7p[P00] and V7n[0NN].
  • the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are turned on and off within the control period Ts as shown in FIG. 13.
  • the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.
  • control unit 60 has a function of performing initial charge control to initially charge the first capacitors C17, the second capacitors C27, and the third capacitors C37 at the startup of the multilevel inverter 100.
  • the operation of the control unit 60 when performing the initial charge control will be described below with reference to FIGS.
  • the DC voltage source E1 is connected between the positive pole P1 and the negative pole N1 of the DC power supply unit 3, and the potential of the intermediate potential point M1 of the DC power supply unit 3 rises transiently to Vdc/2.
  • the DC voltage source E1 is connected between the positive pole P1 and the negative pole N1 of the DC power supply unit 3
  • the control unit 60 starts the operation of the DC-DC converter 91 included in the power supply unit 9.
  • control unit 60 performs a charging control operation after a time has elapsed during which the potential of the intermediate potential point M1 rises to Vdc/2 after the DC voltage source E1 is connected between the positive pole P1 and the negative pole N1 of the DC power supply unit 3.
  • the control unit 60 may be configured to monitor the potential of the intermediate potential point M1 of the DC power supply unit 3 and perform a charging control operation after the potential of the intermediate potential point M1 rises to Vdc/2.
  • the control unit 60 charges the multiple third capacitors C37 and the multiple second capacitors C27, and then charges the multiple first capacitors C17. Therefore, in the initial charging control, the control unit 60 performs a control (first control) to turn on only the fourth switching element Q4 in each of the multiple switching circuits 10, and then performs a control to turn on only the third switching element Q3 and the fourth switching element Q4, and then alternates between a control to turn on only the second switching element Q2 and the third switching element Q3 (third control) and a control to turn on only the third switching element Q3 and the fourth switching element Q4 (fourth control).
  • “Turning on only the fourth switching element Q4" means turning off the first switching element Q1, turning off the second switching element Q2, turning off the third switching element Q3, and turning on the fourth switching element Q4.
  • "Turning on only the third switching element Q3 and the fourth switching element Q4" means turning off the first switching element Q1, turning off the second switching element Q2, turning on the third switching element Q3, and turning on the fourth switching element Q4. Therefore, "turning on only the third switching element Q3 and the fourth switching element Q4" means controlling the inverter circuit 1 to the third switching state ("N").
  • FIG. 14 is an explanatory diagram of the charging path of the third capacitor C37 when the control unit 60 turns on only the fourth switching element Q4 in the initial charging control in the multilevel inverter 10 of the embodiment.
  • the control unit 60 charges the third capacitor C37 from the power supply unit 9 by turning on only the fourth switching element Q4 among the first to fourth switching elements Q1 to Q4 in each of the multiple switching circuits 10.
  • the charging path Ru93 that charges the third capacitor C37 from the power supply unit 9 is the path of the power supply unit 9-third diode D37-third resistor R37-third capacitor C37-second connection point 12-fourth switching element Q4-power supply unit 9, as shown in FIG. 14.
  • the control unit 60 sets the on-period time T1 (see FIG. 17) of the fourth switching element Q4 when only the fourth switching element Q4 in each of the multiple inverter circuits 1 is turned on to, for example, a time equal to or greater than the CR time constant determined by the capacitance of the third capacitor C37 and the resistance value of the third resistor R37 of the third bootstrap circuit 73 corresponding to the fourth switching element Q4.
  • the on-period time T1 of the fourth switching element Q4 is, for example, 1 ms.
  • control unit 60 turns on only the fourth switching element Q4 as described above, and then turns on only the third switching element Q3 and the fourth switching element Q4 among the first to fourth switching elements Q1 to Q4, thereby charging the third capacitor C37 and the second capacitor C27 from the power supply unit 9.
  • the charging path Ru93 that charges the third capacitor C37 from the power supply unit 9 is the path of the power supply unit 9-third diode D37-third resistor R37-third capacitor C37-second connection point 12-fourth switching element Q4-power supply unit 9, as shown in FIG. 15.
  • the charging path Ru92 that charges the second capacitor C27 from the power supply unit 9 is a path from the power supply unit 9 to the third diode D37, the second diode D27, the second resistor R27, the second capacitor C27, the third connection point 13, the third switching element Q3, the second connection point 12, the fourth switching element Q4, and the power supply unit 9, as shown in FIG. 15.
  • the control unit 60 sets the time T2 during which only the third switching element Q3 and the fourth switching element Q4 are on to, for example, a time equal to or greater than the CR time constant determined by the capacitance of the second capacitor C27 of the second bootstrap circuit 72 and the resistance value of the second resistor R27.
  • the time T2 during which only the third switching element Q3 and the fourth switching element Q4 are on is, for example, 1.1 ms.
  • FIG 16 is an explanatory diagram of the charging path of the first capacitor C17 and the charging path of the second capacitor C27 when the control unit 60 turns on only the second switching element Q2 and the third switching element Q3 in the initial charging control in the multilevel inverter 100 of the embodiment.
  • the control unit 60 charges the first capacitor C17 from the third capacitor C37 and the second capacitor C27 by turning on only the second switching element Q2 and the third switching element Q3.
  • the charging path R31 that charges the first capacitor C17 from the third capacitor C37 is the path of the third capacitor C37-third resistor R37-second diode D27-first diode D17-first resistor R17-first capacitor C17-first connection point 11-second switching element Q2-third connection point 13-third switching element Q3-third capacitor C37, as shown in FIG. 16.
  • the charging path R21 that charges the first capacitor C17 from the second capacitor C27 is the path of the second capacitor C27-second resistor R27-first diode D17-first resistor R17-first capacitor C17-first connection point 11-second switching element Q2-second capacitor C27.
  • the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4 in each of the multiple inverter circuits 1.
  • the third capacitor C37 and the second capacitor C27 are charged from the power supply unit 9.
  • the charging path Ru93 that charges the third capacitor C37 from the power supply unit 9 is a path from the power supply unit 9 to the third diode D37 - the third resistor R37 - the third capacitor C37 - the second connection point 12 - the fourth switching element Q4 - the power supply unit 9, as shown in FIG. 15.
  • the charging path Ru92 that charges the second capacitor C27 from the power supply unit 9 is a path from the power supply unit 9 to the third diode D37, the second diode D27, the second resistor R27, the second capacitor C27, the third connection point 13, the third switching element Q3, the second connection point 12, the fourth switching element Q4, and the power supply unit 9, as shown in FIG. 15.
  • the voltage charged to the first capacitor C17 in one third control and one fourth control is determined by the charge amount of the first capacitor C17, the discharge charge amount of the third capacitor C37, and the discharge charge amount of the second capacitor C27. By alternately repeating the third control and the fourth control, it is possible to increase the voltage Vo1 across the first capacitor C17.
  • the control unit 60 sets the time T3 (see FIG. 17) during which the third control and the fourth control are repeated to be, for example, a time equal to or greater than the CR time constant determined by the capacitance of the first capacitor C17 of the multiple first bootstrap circuits 71 and the resistance value of the first resistor R17.
  • the time T3 during which the third control and the fourth control are repeated is, for example, 2 ms.
  • FIG. 17 shows the states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 when the control unit 60 starts the charging control operation at time t1, and the waveforms of the voltage Vo1 across the first capacitor C17, the voltage Vo2 across the second capacitor C27, and the voltage Vo3 across the third capacitor C37.
  • the control unit 60 starts the first control at time t1, so that only the fourth switching element Q4 is turned on at time t1.
  • the fourth switching element Q4 is turned on, charging from the power supply unit 9 to the third capacitor C37 begins, and the voltage Vo3 across the third capacitor C37 increases to the fully charged voltage.
  • the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4.
  • the control unit 60 selects the zero vector V0n[NNN] (V0n in FIG. 17) as the voltage vector, and turns on only the third switching element Q3 and the fourth switching element Q4.
  • control unit 60 turns on only the second switching element Q2 and the third switching element Q3.
  • the control unit 60 selects the zero vector V0o[000] (V0o in FIG. 17) as the voltage vector, and turns on only the second switching element Q2 and the third switching element Q3.
  • the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4.
  • the control unit 60 selects the zero vector V0n[NNN] (V0n in FIG. 17) as the voltage vector, and turns on only the third switching element Q3 and the fourth switching element Q4.
  • the control unit 60 turns on only the second switching element Q2 and the third switching element Q3.
  • the control unit 60 selects the zero vector V0o[000] (V0o in FIG. 17) as the voltage vector, and turns on only the second switching element Q2 and the third switching element Q3.
  • the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4.
  • the control unit 60 selects the zero vector V0n [NNN] (V0n in FIG. 17) as the voltage vector, and turns on only the third switching element Q3 and the fourth switching element Q4.
  • the voltage Vo2 across the second capacitor C27 between time t5 and time t6 is greater than the voltage Vo2 across the second capacitor C27 between time t3 and time t4.
  • the voltage Vo3 across the third capacitor C37 between time t5 and time t6 is greater than the voltage Vo3 across the third capacitor C37 between time t3 and time t4.
  • the control unit 60 turns on only the second switching element Q2 and the third switching element Q3.
  • the control unit 60 selects the zero vector V0o[000] (V0o in FIG. 17) as the voltage vector, and turns on only the second switching element Q2 and the third switching element Q3.
  • the voltage Vo1 across the first capacitor C17 between time t5 and time t7 is greater than the voltage Vo1 across the first capacitor C17 between time t3 and time t5.
  • the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4.
  • the control unit 60 selects the zero vector V0n [NNN] (V0n in FIG. 17) as the voltage vector, and turns on only the third switching element Q3 and the fourth switching element Q4.
  • the voltage Vo2 across the second capacitor C27 between time t7 and time t8 is greater than the voltage Vo2 across the second capacitor C27 between time t5 and time t6.
  • the voltage Vo3 across the third capacitor C37 between time t7 and time t8 is greater than the voltage Vo3 across the third capacitor C37 between time t5 and time t6.
  • the control unit 60 turns on only the second switching element Q2 and the third switching element Q3.
  • the control unit 60 selects the zero vector V0o[000] (V0o in FIG. 17) as the voltage vector, and turns on only the second switching element Q2 and the third switching element Q3.
  • the voltage Vo1 across the first capacitor C17 between time t7 and time t9 is greater than the voltage Vo1 across the first capacitor C17 between time t5 and time t7.
  • the control unit 60 turns on only the third switching element Q3 and the fourth switching element Q4.
  • the control unit 60 selects the zero vector V0n [NNN] (V0n in FIG. 17) as the voltage vector, and turns on only the third switching element Q3 and the fourth switching element Q4.
  • the voltage Vo2 across the second capacitor C27 between time t9 and time t10 is greater than the voltage Vo2 across the second capacitor C27 between time t7 and time t8.
  • the voltage Vo3 across the third capacitor C37 between time t9 and time t10 is greater than the voltage Vo3 across the third capacitor C37 between time t7 and time t8.
  • the control unit 60 has a function of performing initial charging control for initially charging each of the first capacitors C17, each of the second capacitors C27, and each of the third capacitors C37 at the time of startup.
  • the control unit 60 performs a first control for turning on only the fourth switching element Q4 in each inverter circuit 1 and then turning on only the third switching element Q3 and the fourth switching element Q4, or a second control for turning on only the third switching element Q3 and the fourth switching element Q4, and then alternately repeats a third control for turning on only the second switching element Q2 and the third switching element Q3 and a fourth control for turning on only the third switching element Q3 and the fourth switching element Q4.
  • the multilevel inverter 100 according to the embodiment is capable of reducing switching losses because the control unit 60 performs the above-mentioned initial charging control at startup. More specifically, the multilevel inverter 100 according to the embodiment is capable of reducing switching losses in each of the first switching elements Q1, the second switching elements Q2, and the third switching elements Q3, compared to a case in which the control unit 60 does not perform the above-mentioned initial charging control at startup.
  • the control unit 60 performs the initial charging control and then performs the inverter control, so that the voltage Vo1 across each first capacitor C17 when the inverter control is started can be made larger (for example, the voltage Vo1 across each first capacitor C17 can be set to the fully charged voltage of each first capacitor C17).
  • the difference between the gate voltage (gate-emitter voltage) applied to the first switching element Q1 in each inverter circuit 1 and the threshold voltage (for example, 5.8 V) of the first switching element Q1 can be made larger, and the switching loss of the first switching element Q1 can be reduced.
  • the voltage Vo2 across each second capacitor C27 when the inverter control is started can be made larger (for example, the voltage Vo2 across each second capacitor C27 can be set to the fully charged voltage of each second capacitor C27). Therefore, in the multilevel inverter 100 according to the embodiment, the difference between the gate voltage (gate-emitter voltage) given to the second switching element Q2 in each inverter circuit 1 and the threshold voltage (e.g., 5.8 V) of the second switching element Q2 can be made larger, and the switching loss of the second switching element Q2 can be reduced.
  • the threshold voltage e.g., 5.8 V
  • the voltage Vo3 across each third capacitor C37 when the inverter control is started can be made larger (e.g., the voltage Vo3 across each third capacitor C37 can be set to the fully charged voltage of each third capacitor C37). Therefore, in the multilevel inverter 100 according to the embodiment, the difference between the gate voltage (gate-emitter voltage) given to the third switching element Q3 in each inverter circuit 1 and the threshold voltage (e.g., 5.8 V) of the third switching element Q3 can be made larger, and the switching loss of the third switching element Q3 can be reduced.
  • the threshold voltage e.g., 5.8 V
  • the control unit 60 may perform a control (second control) in which only the third switching element Q3 and the fourth switching element Q4 are turned on, and then the third control and the fourth control may be repeated alternately.
  • the control unit 60 performs the second control, the on-period time of the third switching element Q3 is the same as the on-period time of the fourth switching element Q4.
  • time T1 during which the control unit 60 turns on only the fourth switching element Q4 in the first control is not limited to a time equal to or greater than the CR time constant of the third bootstrap circuit 73, but may be, for example, a time equal to or greater than 90% and less than 100% of the CR time constant.
  • time T2 during which only the third switching element Q3 and the fourth switching element Q4 are on when the control unit 60 is in the first control or second control is not limited to a time equal to or greater than the CR time constant determined by the capacitance of the second capacitor C27 of the second bootstrap circuit 72 and the resistance value of the second resistor R27, but may be, for example, a time greater than or equal to 90% and less than 100% of the CR time constant.
  • the time T3 (see FIG. 17) during which the control unit 60 repeats the third control and the fourth control is not limited to a time equal to or greater than the CR time constant determined by the capacitance of the first capacitor C17 of the first bootstrap circuits 71 and the resistance value of the first resistor R17, but may be, for example, a time equal to or greater than 90% and less than 100% of the CR time constant.
  • each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 may be a MOSFET, not limited to an IGBT.
  • the control terminal, the first main terminal, and the second main terminal of each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 are a gate terminal, a drain terminal, and a source terminal, respectively.
  • the MOSFET constituting each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 is, for example, a normally-off type n-channel MOSFET.
  • the MOSFET is a Si-based MOSFET, but is not limited to a Si-based MOSFET and may be, for example, a SiC-based MOSFET.
  • each of the multiple first bootstrap circuits 71 may include a first Zener diode Z17, but may not include the first Zener diode Z17.Furthermore, each of the multiple second bootstrap circuits 72 may include a second Zener diode Z27, but may not include the second Zener diode Z27.Furthermore, each of the multiple third bootstrap circuits 73 may include a third Zener diode Z37, but may not include the third Zener diode Z37.
  • each of the multiple first bootstrap circuits 71 includes a first resistor R17, and is configured such that the CR time constant is determined by the capacitance of the first capacitor C17 and the resistance value of the first resistor R17, but may be configured such that the CR time constant is determined by the capacitance of the first capacitor C17 and the ESR (Equivalent Series Resistance) of the first capacitor C17 without including the first resistor R17.
  • each of the multiple second bootstrap circuits 72 includes a second resistor R27, and is configured such that the CR time constant is determined by the capacitance of the second capacitor C27 and the resistance value of the second resistor R27, but may be configured such that the CR time constant is determined by the capacitance of the second capacitor C27 and the ESR of the second capacitor C27 without including the second resistor R27.
  • each of the multiple third bootstrap circuits 73 includes a third resistor R37, and the CR time constant is determined by the capacitance of the third capacitor C37 and the resistance value of the third resistor R37. However, the configuration may be such that the CR time constant is determined by the capacitance of the third capacitor C37 and the ESR of the third capacitor C37 without including the third resistor R37.
  • the multilevel inverter 100 may also be configured such that the power supply unit 9 includes multiple (three) DC-DC converters 91.
  • the multiple DC-DC converters 91 correspond to multiple (three) fourth gate drivers 64 and are connected in parallel to the corresponding fourth gate drivers 64.
  • the multilevel inverter 100 is not limited to a configuration including multiple switching circuits 10, and may be configured to include one switching circuit 10.
  • the multilevel inverter 100 is configured to include one switching circuit 10 instead of multiple switching circuits 10, there is also one each of the first gate driver 61, the second gate driver 62, the third gate driver 63, and the fourth gate driver 64, and there is also one each of the first bootstrap circuit 71, the second bootstrap circuit 72, and the third bootstrap circuit 73.
  • control unit 60 is not limited to being configured to perform voltage vector control, but may also be configured to perform PWM control.
  • the multilevel inverter 100 may be a multilevel inverter with three or more levels, for example, a five-level inverter.
  • the multilevel inverter (100) includes a DC power supply unit (3), an inverter circuit (1), and a control device (6).
  • the DC power supply unit (3) has a positive pole (P1), a negative pole (N1), and an intermediate potential point (M1).
  • the inverter circuit (1) is connected between the positive pole (P1) and the negative pole (N1) of the DC power supply unit (3).
  • the control device (6) controls the inverter circuit (1).
  • the inverter circuit (1) includes a switching circuit (10), a first clamp diode (D5), and a second clamp diode (D6).
  • the switching circuit (10) includes a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4).
  • the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4) are connected in series from the positive electrode (P1) side to the negative electrode (N1) side in the order of the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4).
  • the first clamp diode (D5) is connected between a first connection point (11) between the first switching element (Q1) and the second switching element (Q2) and an intermediate potential point (M1).
  • the second clamp diode (D6) is connected between a second connection point (12) between the third switching element (Q3) and the fourth switching element (Q4) and an intermediate potential point (M1).
  • the control device (6) includes a first gate driver (61), a second gate driver (62), a third gate driver (63), a fourth gate driver (64), a first bootstrap circuit (71), a second bootstrap circuit (72), a third bootstrap circuit (73), a power supply unit (9), and a control unit (60).
  • the first gate driver (61) drives a first switching element (Q1).
  • the second gate driver (62) drives a second switching element (Q2).
  • the third gate driver (63) drives a third switching element (Q3).
  • the fourth gate driver (64) drives a fourth switching element (Q4).
  • the first bootstrap circuit (71) includes a first capacitor (C17) connected in parallel to the first gate driver (61) and a first diode (D17) connected in series to the first capacitor (C17).
  • the second bootstrap circuit (72) includes a second capacitor (C27) connected in parallel to the second gate driver (62) and a second diode (D27) connected in series to the second capacitor (C27).
  • the third bootstrap circuit (73) includes a third capacitor (C37) connected in parallel to the third gate driver (63) and a third diode (D37) connected in series to the third capacitor (C37).
  • the power supply unit (9) is connected in parallel to the fourth gate driver (64).
  • the control unit (60) controls the first gate driver (61), the second gate driver (62), the third gate driver (63) and the fourth gate driver (64).
  • the power supply unit (9) is connected to the third capacitor (C37) through the third diode (D37), to the second capacitor (C27) through the third diode (D37) and the second diode (D27), and to the first capacitor (C17) through the third diode (D37), the second diode (D27), and the first diode (D17).
  • the control unit (60) has a function of performing initial charge control for initially charging the first capacitor (C17), the second capacitor (C27), and the third capacitor (C37) at the time of start-up.
  • the control unit (60) performs a first control in which only the fourth switching element (Q4) is turned on, and then only the third switching element (Q3) and the fourth switching element (Q4) are turned on, or a second control in which only the third switching element (Q3) and the fourth switching element (Q4) are turned on, and then alternately repeats a third control in which only the second switching element (Q2) and the third switching element (Q3) are turned on, and a fourth control in which only the third switching element (Q3) and the fourth switching element (Q4) are turned on.
  • This embodiment makes it possible to reduce switching losses.
  • the first bootstrap circuit (71) further includes a first resistor (R17).
  • the first resistor (R17) is connected between the first diode (D17) and the first capacitor (C17).
  • the second bootstrap circuit (72) further includes a second resistor (R27).
  • the second resistor (R27) is connected between the second diode (D27) and the second capacitor (C27).
  • the third bootstrap circuit (73) further includes a third resistor (R37).
  • the third resistor (R37) is connected between the third diode (D37) and the third capacitor (C37).
  • the control unit (60) sets the time (T1) of the on-period of the fourth switching element (Q4) in the first control or the second control to a time equal to or greater than the CR time constant determined by the capacitance of the third capacitor (C37) and the resistance value of the third resistor (R37) of the third bootstrap circuit (73).
  • This embodiment makes it possible to reduce the switching loss of the third switching element (Q3) after the initial charging control.
  • control unit (60) performs a first control in which, in the initial charge control, only the fourth switching element (Q4) is turned on, and then only the third switching element (Q3) and the fourth switching element (Q4) are turned on.
  • the control unit (60) sets the time (T1) of the ON period of only the fourth switching element (Q4) to a time equal to or greater than the CR time constant determined by the capacitance of the third capacitor (C37) and the resistance value of the third resistor (R37) of the third bootstrap circuit (73), and sets the time (T2) of the ON period of only the third switching element (Q3) and the fourth switching element (Q4) to a time equal to or greater than the CR time constant determined by the capacitance of the second capacitor (C27) and the resistance value of the second resistor (R27) of the second bootstrap circuit (72).
  • the control unit (60) sets the time period during which the third control and the fourth control are repeated in the initial charging control to a time equal to or greater than the CR time constant determined by the capacitance of the first capacitor (C17) and the resistance value of the first resistor (R17) of the multiple first bootstrap circuits (71).
  • the multilevel inverter (100) is any one of the first to fifth aspects and includes three inverter circuits (1), three first gate drivers (61), three second gate drivers (62), three third gate drivers (63), three fourth gate drivers (64), three first bootstrap circuits (71), three second bootstrap circuits (72), and three third bootstrap circuits (73).
  • the three first bootstrap circuits (71) and the three second bootstrap circuits (72) are in one-to-one correspondence.
  • the three first bootstrap circuits (71) and the three third bootstrap circuits (73) are in one-to-one correspondence.
  • the three second bootstrap circuits (72) and the three third bootstrap circuits (73) are in one-to-one correspondence.
  • the power supply unit (9) is connected in parallel to the three fourth gate drivers (64).
  • the power supply unit (9) is connected to the third capacitor (C37) via a third diode (D37) in each of the three third bootstrap circuits (73).
  • the power supply unit (9) is connected to the second capacitor (C27) via the third diode (D37) and the second diode (D27) of the corresponding third bootstrap circuit (73) among the three third bootstrap circuits (73) in each of the three second bootstrap circuits (72).
  • the power supply unit (9) is connected to the first capacitor (C17) via the third diode (D37) of the corresponding third bootstrap circuit (73) among the three third bootstrap circuits (73) and the second diode (D27) and the first diode (D17) of the corresponding second bootstrap circuit (72) among the three second bootstrap circuits (72) in each of the three first bootstrap circuits (71).
  • This aspect makes it possible to achieve miniaturization.
  • the power supply unit (9) includes a DC-DC converter (91).
  • the multilevel inverter disclosed herein can reduce switching losses. In this way, the multilevel inverter disclosed herein is industrially useful.

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PCT/JP2024/020138 2023-06-27 2024-06-03 マルチレベルインバータ Ceased WO2025004696A1 (ja)

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Citations (5)

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Publication number Priority date Publication date Assignee Title
US20120230059A1 (en) * 2011-03-11 2012-09-13 Stmicroelectronics S.R.L. Device for avoiding hard switching in resonant converter and related method
JP2018133876A (ja) 2017-02-14 2018-08-23 株式会社東芝 ３レベル中性点クランプ形インバータのスイッチング素子駆動回路
JP2020182338A (ja) * 2019-04-25 2020-11-05 株式会社Ihi 半導体スイッチング素子駆動回路及びマルチレベル電力変換器
WO2024053452A1 (ja) * 2022-09-09 2024-03-14 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ
WO2024053453A1 (ja) * 2022-09-09 2024-03-14 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120230059A1 (en) * 2011-03-11 2012-09-13 Stmicroelectronics S.R.L. Device for avoiding hard switching in resonant converter and related method
JP2018133876A (ja) 2017-02-14 2018-08-23 株式会社東芝 ３レベル中性点クランプ形インバータのスイッチング素子駆動回路
JP2020182338A (ja) * 2019-04-25 2020-11-05 株式会社Ihi 半導体スイッチング素子駆動回路及びマルチレベル電力変換器
WO2024053452A1 (ja) * 2022-09-09 2024-03-14 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ
WO2024053453A1 (ja) * 2022-09-09 2024-03-14 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ

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