WO2025001644A1 - 多路复用电路、复用模组、显示装置和驱动方法 - Google Patents

多路复用电路、复用模组、显示装置和驱动方法 Download PDF

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Publication number
WO2025001644A1
WO2025001644A1 PCT/CN2024/094819 CN2024094819W WO2025001644A1 WO 2025001644 A1 WO2025001644 A1 WO 2025001644A1 CN 2024094819 W CN2024094819 W CN 2024094819W WO 2025001644 A1 WO2025001644 A1 WO 2025001644A1
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WIPO (PCT)
Prior art keywords
multiplexing
data
control line
line
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/094819
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English (en)
French (fr)
Inventor
谢勇贤
马小叶
王永灿
张然
王章涛
郭晖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
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Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/881,899 priority Critical patent/US20260011275A1/en
Publication of WO2025001644A1 publication Critical patent/WO2025001644A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a multiplexing circuit, a multiplexing module, a display device and a driving method.
  • an embodiment of the present disclosure provides a multiplexing circuit, which is electrically connected to M data voltage supply terminals and multiple column data lines, respectively, wherein the multiplexing circuit includes N multiplexing control lines and N multiplexing circuits, wherein the nth multiplexing circuit includes M multiplexing sub-circuits; and the nth multiplexing control line includes M control lines;
  • the mth multiplexing sub-circuit included in the nth multiplexing circuit is electrically connected to the mth control line, the mth data voltage supply terminal and the corresponding data line included in the nth multiplexing control line, respectively, and is used to write the data voltage provided by the mth data voltage supply terminal into the corresponding data line under the control of the control signal provided by the mth control line;
  • N and M are integers greater than 1
  • n is a positive integer less than or equal to N
  • m is a positive integer less than or equal to M.
  • the multiplexing circuit includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit, and a second multiplexing circuit;
  • the first multiplexed control line includes a first control line and a second control line;
  • the second multiplexed control line includes a third control line and a fourth control line;
  • the first multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the second multiplexing circuit includes a third multiplexing sub-circuit and a fourth multiplexing sub-circuit;
  • the first multiplexing subcircuit is electrically connected to the first control line, the first data voltage supply terminal and the first column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the first column data line under the control of the first control signal provided by the first control line;
  • the second multiplexing subcircuit is electrically connected to the second control line, the second data voltage supply terminal and the second column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the second column data line under the control of the second control signal provided by the second control line;
  • the third multiplexing sub-circuit is electrically connected to the third control line, the first data voltage supply terminal and the third column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the third column data line under the control of the third control signal provided by the third control line;
  • the fourth multiplexing sub-circuit is electrically connected to the fourth control line, the second data voltage supply terminal and the fourth column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the fourth column data line under the control of a fourth control signal provided by the fourth control line.
  • the first multiplexing sub-circuit includes a first transistor
  • the second multiplexing sub-circuit includes a second transistor
  • the gate of the first transistor is electrically connected to the first control line, the first electrode of the first transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the first transistor is electrically connected to the first column data line;
  • a gate of the second transistor is electrically connected to the second control line, a first electrode of the second transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the second transistor is electrically connected to the second column data line.
  • both the first transistor and the second transistor are n-type transistors; or, both the first transistor and the second transistor are p-type transistors.
  • the third multiplexing sub-circuit includes a third transistor
  • the fourth multiplexing sub-circuit includes a fourth transistor
  • the gate of the third transistor is electrically connected to the third control line, the first electrode of the third transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the third transistor is electrically connected to the third column data line;
  • a gate of the fourth transistor is electrically connected to the fourth control line, a first electrode of the fourth transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the fourth transistor is electrically connected to the fourth column data line.
  • the third transistor and the fourth transistor are both n-type transistors; or, the third transistor and the fourth transistor are both p-type transistors.
  • the disclosed embodiment also provides a multiplexing module, comprising a plurality of the above-mentioned multiplexing circuits.
  • the embodiment of the present disclosure also provides a display device, including a data driver, a plurality of columns of data lines and the above-mentioned multiplexing module;
  • the data driver is used to provide a data voltage to the multiplexing module through a data voltage supply terminal;
  • the data line is used to receive the data voltage provided by the multiplexing module.
  • the data driver provides a control signal for each control line through at least one corresponding output channel.
  • the display device includes a display panel, a data driver and a plurality of control lines;
  • the data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of the display panel;
  • the data driver is further configured to provide a control signal input to the control line.
  • control line includes a first end and a second end
  • the first output channel of the data driver is electrically connected to the first end, and the second output channel of the data driver is electrically connected to the second end.
  • the data driver is used to provide a control signal to the first end through the first output channel and to provide a control signal to the second end through the second output channel.
  • the display device includes a display panel, at least two data drivers and a plurality of control lines;
  • the data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of the display panel;
  • the data driver is further configured to provide a control signal input to the control line.
  • control line is electrically connected to the at least two data drivers through at least three access points, and is used to receive a control signal provided by the data driver.
  • the display device includes a first data driver and a second data driver
  • the first output channel of the first data driver is electrically connected to the first end of the control line, and the first output channel of the second data driver is electrically connected to the second end of the control line;
  • the second output channel of the first data driver and the second output channel of the second data driver are both electrically connected to the middle node of the control line;
  • the first data driver is used to provide a control signal to the control line through its first output channel and its second output channel;
  • the second data driver is used for providing a control signal to the control line through a first output channel and a second output channel thereof.
  • the display device further includes a plurality of rows of gate lines and a plurality of rows and columns of pixel circuits;
  • the pixel circuit is electrically connected to the corresponding row gate line and the corresponding column data line respectively, and is used for controlling and receiving the data voltage provided by the corresponding column data line under the control of the gate driving signal provided by the corresponding row gate line.
  • the embodiment of the present disclosure further provides a driving method, which is applied to the above-mentioned display device, and the driving method includes:
  • the data driver provides a data voltage to the multiplexing module through a data voltage supply terminal
  • the data line receives the data voltage provided by the multiplexing module.
  • the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;
  • the first multiplexing control line When the gate line of row 2a-1 is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on;
  • the second multiplexing control line When the gate line in row 2a is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on.
  • the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;
  • the second multiplexing control line When the gate line of row 2a-1 is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on;
  • the first multiplexing control line When the gate line in row 2a is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on.
  • FIG1 is a structural diagram of a multiplexing circuit according to at least one embodiment of the present disclosure.
  • FIG2 is a circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure.
  • FIG3A is a schematic diagram of some transistors included in a multiplexing module according to at least one embodiment of the present disclosure
  • FIG3B is a waveform diagram of a first control signal provided by M11 in at least one embodiment of the present disclosure
  • FIG3C is a waveform diagram of a multiplexing control signal provided by a multiplexing control line in the related art
  • FIG. 4 is a layout diagram of at least one embodiment shown in FIG. 3A ;
  • FIG5 is a layout diagram of the gate metal layer in FIG4 ;
  • FIG6 is a layout diagram of the semiconductor layer in FIG4;
  • FIG7 is a layout diagram of the source/drain metal layer in FIG4 ;
  • FIG8 is a layout diagram of the second conductive layer in FIG4;
  • FIG9 is a structural diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG10 is a structural diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG11 is a layout diagram of the middle portion of at least one embodiment shown in FIG10 ;
  • FIG12 is a layout diagram of the gate metal layer in FIG11;
  • FIG13 is a layout diagram of the source/drain metal layer in FIG11 ;
  • FIG14 is a layout diagram of the second conductive layer in FIG11;
  • 15 is a schematic diagram showing the connection relationship between a portion of pixel circuits and a portion of multiplexing transistors included in a display device according to at least one embodiment of the present disclosure
  • FIG16 is a timing diagram of the operation of at least one embodiment shown in FIG15 ;
  • FIG17 is a timing diagram of the operation of at least one embodiment shown in FIG15 ;
  • FIG. 18 is a timing diagram of operation of at least one embodiment shown in FIG. 15 .
  • the transistors used in all embodiments of the present disclosure can be thin film transistors or field effect transistors or In the disclosed embodiment, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the multiplexing circuit described in the embodiment of the present disclosure is electrically connected to M data voltage supply terminals and multiple column data lines respectively, the multiplexing circuit includes N multiplexing control lines and N multiplexing circuits, the nth multiplexing circuit includes M multiplexing sub-circuits; the nth multiplexing control line includes M control lines;
  • the mth multiplexing sub-circuit included in the nth multiplexing circuit is electrically connected to the mth control line, the mth data voltage supply terminal and the corresponding data line included in the nth multiplexing control line, respectively, and is used to write the data voltage provided by the mth data voltage supply terminal into the corresponding data line under the control of the control signal provided by the mth control line;
  • N and M are integers greater than 1
  • n is a positive integer less than or equal to N
  • m is a positive integer less than or equal to M.
  • the embodiment of the present disclosure proposes a data signal multiplexing circuit, which uses at least two multiplexing control lines and one data voltage supply terminal to drive at least two columns of data lines, so that the number of data voltage supply terminals used is small, and the number of data drivers used can be reduced while ensuring that the resolution of the display product remains unchanged.
  • the multiplexing control line is set to include at least two control lines, and the at least two control lines are driven by different channels of the data driver.
  • the number of transistors driven by each control line is reduced compared to the number of transistors driven by the relevant multiplexing control line, and the load of the control line is reduced, which can effectively reduce the rise time and fall time of the control signal on the control line, and greatly improve the charging capacity of the control line.
  • N and M are both equal to 2 as an example, but the present invention is not limited thereto. In actual operation, N and M may be integers greater than 1.
  • the multiplexing circuit described in at least one embodiment of the present disclosure includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit, and a second multiplexing circuit;
  • the first multiplexed control line includes a first control line and a second control line;
  • the second multiplexed control line includes a third control line and a fourth control line;
  • the first multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the second multiplexing circuit includes a third multiplexing sub-circuit and a fourth multiplexing sub-circuit;
  • the first multiplexing subcircuit is electrically connected to the first control line, the first data voltage supply terminal and the first column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the first column data line under the control of the first control signal provided by the first control line;
  • the second multiplexing subcircuit is electrically connected to the second control line, the second data voltage supply terminal and the second column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the second column data line under the control of the second control signal provided by the second control line;
  • the third multiplexing sub-circuit is electrically connected to the third control line, the first data voltage supply terminal and the third column data line respectively, and is used to write the data voltage provided by the first data voltage supply terminal into the third column data line under the control of the third control signal provided by the third control line;
  • the fourth multiplexing sub-circuit is electrically connected to the fourth control line, the second data voltage supply terminal and the fourth column data line respectively, and is used to write the data voltage provided by the second data voltage supply terminal into the fourth column data line under the control of a fourth control signal provided by the fourth control line.
  • the multiplexing circuit may include a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit and a second multiplexing circuit
  • the first multiplexing control line may include a first control line and a second control line
  • the second multiplexing control line may include a third control line and a fourth control line
  • the first multiplexing sub-circuit writes the data voltage provided by the first data voltage supply end into the first column data line under the control of a first control signal
  • the second multiplexing sub-circuit writes the data voltage provided by the second data voltage supply end into the second column data line under the control of a second control signal
  • the third multiplexing sub-circuit writes the data voltage provided by the first data voltage supply end into the third column data line under the control of a third control signal
  • the fourth multiplexing sub-circuit writes the data voltage provided by the second data voltage supply end into the fourth column data line under the control of a fourth control signal.
  • the multiplexing circuit is electrically connected to the first data voltage supply terminal S1, the second data voltage supply terminal S2, the first column data line D1, the second column data line D2, the third column data line D3, and the fourth column data line D4, respectively, and the multiplexing circuit includes a first multiplexing control line, a second multiplexing control line, a first multiplexing circuit, and a second multiplexing circuit;
  • the first multiplexed control line includes a first control line M11 and a second control line M12, and the second multiplexed control line includes a third control line M21 and a fourth control line M22;
  • the first multiplexing circuit includes a first multiplexing sub-circuit 11 and a second multiplexing sub-circuit 12, and the second multiplexing circuit includes a third multiplexing sub-circuit 13 and a fourth multiplexing sub-circuit 14;
  • the first multiplexing sub-circuit 11 is electrically connected to the first control line M11, the first data voltage supply terminal S1 and the first column data line D1 respectively, and is used to write the data voltage provided by the first data voltage supply terminal S1 into the first column data line D1 under the control of the first control signal provided by the first control line M11;
  • the second multiplexing sub-circuit 12 is electrically connected to the second control line M12, the second data voltage supply terminal S2 and the second column data line D2 respectively, and is used to write the data voltage provided by the second data voltage supply terminal S2 into the second column data line D2 under the control of the second control signal provided by the second control line M12;
  • the third multiplexing sub-circuit 13 is electrically connected to the third control line M13, the first data voltage supply terminal S1 and the third column data line D3 respectively, and is used to write the data voltage provided by the first data voltage supply terminal S1 into the third column data line D3 under the control of the third control signal provided by the third control line M13;
  • the fourth multiplexing sub-circuit 14 is electrically connected to the fourth control line M14, the second data voltage supply terminal S2 and the fourth column data line D4 respectively, and is used to write the data voltage provided by the second data voltage supply terminal S2 into the fourth column data line D4 under the control of the fourth control signal provided by the fourth control line M14.
  • the first control signal provided by the first control line M11 and the second control signal provided by the second control line M12 may be the same
  • the third control signal provided by the third control line M13 and the fourth control signal provided by the fourth control line M14 may be the same
  • the first control line M11, the second control line M12, the third control line M13, and the fourth control line M14 are electrically connected to the first output channel of the data driver, the second output channel of the data driver, the third output channel of the data driver, and the fourth output channel of the data driver, respectively
  • the corresponding output channels of the data driver provide control signals to each control line
  • the number of transistors driven by each control line is halved compared to the number of transistors driven by the related multiplexed control line
  • the load of the control line is reduced
  • the rise time of the control signal on the control line can be effectively reduced. and fall time, improving the charging capacity of each control line.
  • each control line may also be electrically connected to at least two output channels of the data driver to enhance the driving capability of the control line.
  • the first multiplexing sub-circuit includes a first transistor
  • the second multiplexing sub-circuit includes a second transistor
  • the gate of the first transistor is electrically connected to the first control line, the first electrode of the first transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the first transistor is electrically connected to the first column data line;
  • a gate of the second transistor is electrically connected to the second control line, a first electrode of the second transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the second transistor is electrically connected to the second column data line.
  • both the first transistor and the second transistor are n-type transistors; or, both the first transistor and the second transistor are p-type transistors.
  • the third multiplexing sub-circuit includes a third transistor
  • the fourth multiplexing sub-circuit includes a fourth transistor
  • the gate of the third transistor is electrically connected to the third control line, the first electrode of the third transistor is electrically connected to the first data voltage supply terminal, and the second electrode of the third transistor is electrically connected to the third column data line;
  • a gate of the fourth transistor is electrically connected to the fourth control line, a first electrode of the fourth transistor is electrically connected to the second data voltage supply terminal, and a second electrode of the fourth transistor is electrically connected to the fourth column data line.
  • the third transistor and the fourth transistor are both n-type transistors; or, the third transistor and the fourth transistor are both p-type transistors.
  • the first multiplexing sub-circuit includes a first transistor T1
  • the second multiplexing sub-circuit includes a second transistor T2 ;
  • the gate of the first transistor T1 is electrically connected to the first control line M11, the source of the first transistor T1 is electrically connected to the first data voltage supply terminal S1, and the drain of the first transistor T1 is electrically connected to the first column data line D1;
  • the gate of the second transistor T2 is electrically connected to the second control line M12, the source of the second transistor T2 is electrically connected to the second data voltage supply terminal S2, and the drain of the second transistor T2 is electrically connected to the second column data line D2;
  • the third multiplexing sub-circuit includes a third transistor T3, and the fourth multiplexing sub-circuit includes a fourth transistor T4;
  • the gate of the third transistor T3 is electrically connected to the third control line M13, the source of the third transistor T3 is electrically connected to the first data voltage supply terminal S1, and the drain of the third transistor T3 is electrically connected to the third column data line D3;
  • a gate of the fourth transistor T4 is electrically connected to the fourth control line M14 , a source of the fourth transistor T4 is electrically connected to the second data voltage supply terminal S2 , and a drain of the fourth transistor T4 is electrically connected to the fourth column data line D4 .
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • a data providing cycle may include a first multiplexing phase and a second multiplexing phase
  • M11 and M12 both provide high voltage signals, T1 and T2 are both turned on, S1 is connected to D1, S2 is connected to D2, a data voltage is provided to D1 through S1, and a data voltage is provided to D2 through S2;
  • M13 and M14 both provide high voltage signals, T3 and T4 are both turned on, S1 is connected to D3, S2 is connected to D4, a data voltage is provided to D3 through S1, and a data voltage is provided to D4 through S2.
  • the multiplexing module described in the embodiment of the present disclosure includes a plurality of the above-mentioned multiplexing circuits.
  • FIG. 3A is a schematic diagram showing some transistors included in a multiplexing module according to at least one embodiment of the present disclosure.
  • the multiplexing module described in at least one embodiment of the present disclosure includes a first multiplexing circuit and a second multiplexing circuit;
  • the first multiplexing circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4;
  • the second multiplexing circuit includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;
  • the gate of the first transistor T1 is electrically connected to the first control line M11, the source of the first transistor T1 is electrically connected to the first data voltage supply terminal S1, and the drain of the first transistor T1 is electrically connected to the first column data line D1;
  • the gate of the second transistor T2 is electrically connected to the second control line M12, the source of the second transistor T2 is electrically connected to the second data voltage supply terminal S2, and the drain of the second transistor T2 is electrically connected to the second column data line D2;
  • the gate of the third transistor T3 is electrically connected to the third control line M13, the source of the third transistor T3 is electrically connected to the first data voltage supply terminal S1, and the drain of the third transistor T3 is electrically connected to the third column data line D3;
  • the gate of the fourth transistor T4 is electrically connected to the fourth control line M14, the source of the fourth transistor T4 is electrically connected to the second data voltage supply terminal S2, and the drain of the fourth transistor T4 is electrically connected to the fourth column data line D4;
  • the gate of the fifth transistor T5 is electrically connected to the first control line M11, the source of the fifth transistor T5 is electrically connected to the third data voltage supply terminal S3, and the drain of the fifth transistor T5 is electrically connected to the fifth column data line D5;
  • the gate of the sixth transistor T6 is electrically connected to the second control line M12, the source of the sixth transistor T6 is electrically connected to the fourth data voltage supply terminal S4, and the drain of the sixth transistor T6 is electrically connected to the sixth column data line D6;
  • the gate of the seventh transistor T7 is electrically connected to the third control line M13, the source of the seventh transistor T7 is electrically connected to the third data voltage supply terminal S3, and the drain of the seventh transistor T7 is electrically connected to the seventh data line D7;
  • the gate of the eighth transistor T8 is electrically connected to the fourth control line M14, the source of the eighth transistor T8 is electrically connected to the fourth data voltage supply terminal S4, and the drain of the eighth transistor T8 is electrically connected to the eighth data line D8.
  • T1 , T2 , T3 , T4 , T5 , T6 , T7 , and T8 are all n-type transistors, but the present invention is not limited thereto.
  • the data provision cycle may include a first multiplexing phase and a second multiplexing phase
  • M11 and M12 both provide high voltage signals, T1, T2, T5 and T6 are all turned on, S1 is connected to D1, S2 is connected to D2, a data voltage is provided to D1 through S1, and a data voltage is provided to D2 through S2; S3 is connected to D5, S4 is connected to D6, a data voltage is provided to D5 through S3, and a data voltage is provided to D6 through S4;
  • M13 and M14 both provide high voltage signals, T3, T4, T7 and T8 are all turned on, S1 is connected to D3, S2 is connected to D4, data voltage is provided to D3 through S1, and data voltage is provided to D4 through S2; S3 is connected to D7, S4 is connected to D8, data voltage is provided to D7 through S3, and data voltage is provided to D8 through S4.
  • the number of transistors used is halved, and S1 drives D1 and D3, and S2 drives D2 and D4.
  • S1 provides a positive polarity data voltage
  • D1 and D3 provide a positive polarity data voltage
  • S2 provides a negative polarity data voltage
  • D2 and D4 provide a negative polarity data voltage, thereby achieving the purpose of opposite polarity of the data voltages on the data lines adjacent to the pixel area.
  • FIG3B is a waveform diagram of a first control signal provided by M11 in at least one embodiment of the present disclosure
  • FIG. 3C is a waveform diagram of a multiplexing control signal provided by a multiplexing control line in the related art.
  • the rise time and the fall time of the first control signal provided by M11 are shorter, while in the related art, the rise time and the fall time of the multiplexing control signal M1 provided by the multiplexing control line are longer.
  • the rise time of the first control signal provided by M11 can be 0.26 ⁇ s, and the fall time of the first control signal provided by M11 can be 0.25 ⁇ s.
  • the rise time of the multiplexed control signal M1 is 0.46 ⁇ s, and the fall time of the multiplexed control signal M1 is 0.45 ⁇ s. It can be seen from the above that in at least one embodiment of the present disclosure, the control signal is more beneficial to charging.
  • FIG. 4 is a layout diagram of at least one embodiment of the invention shown in FIG. 3A .
  • FIG. 5 is a layout diagram of the gate metal layer in FIG. 4 .
  • the gate labeled G1 is T1
  • the gate labeled G2 is T2
  • the gate labeled G3 is T3
  • the gate labeled G4 is T4
  • the gate labeled G5 is T5
  • the gate labeled G6 is T6
  • the gate labeled G7 is T7
  • the gate labeled G8 is T8.
  • FIG. 6 is a layout diagram of the semiconductor layer in FIG. 4 .
  • A1 is the active pattern of T1
  • A2 is the active pattern of T2
  • A3 is the active pattern of T3
  • A4 is the active pattern of T4
  • A5 is the active pattern of T5
  • A6 is the active pattern of T6
  • A7 is the active pattern of T7
  • A8 is the active pattern of T8.
  • FIG. 7 is a layout diagram of the source/drain metal layer in FIG. 4 .
  • the source-drain pattern labeled SD1 is T1
  • the source-drain pattern labeled SD2 is T2
  • the source-drain pattern labeled SD3 is T3
  • the source-drain pattern labeled SD4 is T4
  • the source-drain pattern labeled SD5 is T5
  • the source-drain pattern labeled SD6 is T6
  • the source-drain pattern labeled SD7 is T7
  • the source-drain pattern labeled SD8 is T8.
  • FIG. 8 is a layout diagram of the second conductive layer in FIG. 4 .
  • the gate metal layer, the semiconductor layer, the source-drain metal layer and the second conductive layer can be arranged in sequence along the direction away from the substrate, and a first conductive layer can be provided between the source-drain metal layer and the second conductive layer, and the first conductive layer can be a common electrode layer of the entire layer;
  • the second conductive layer can be a pixel electrode layer, and in the display area, the second conductive layer can include a pixel electrode;
  • the first conductive layer and the second conductive layer can both be made of ITO (indium tin oxide), but are not limited to this.
  • a touch electrode layer may be further disposed between the source/drain metal layer and the first conductive layer, but the present invention is not limited thereto.
  • the display device described in the embodiment of the present disclosure includes a data driver, a plurality of columns of data lines and the above-mentioned multiplexing module;
  • the data driver is used to provide a data voltage to the multiplexing module through a data voltage supply terminal;
  • the data line is used to receive the data voltage provided by the multiplexing module.
  • the display device may include a data driver and the multiplexing module described above, and the data driver provides a data voltage to a corresponding data line for the multiplexing resistor via a data voltage supply terminal.
  • the data driver provides a control signal to each of the control lines through at least one corresponding output channel to enhance the driving capability of each control line.
  • the display device includes a display panel, a data driver, and a plurality of control lines;
  • the data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of the display panel;
  • the data driver is further configured to provide a control signal input to the control line.
  • the display device may include only one data driver, and the control line may be arranged between the data driver and the effective display area of the display panel, and the data driver provides a control signal to the control line.
  • control line includes a first end and a second end
  • the first output channel of the data driver is electrically connected to the first end, and the second output channel of the data driver is electrically connected to the second end.
  • the data driver is used to provide a control signal to the first end through the first output channel and to provide a control signal to the second end through the second output channel.
  • the data driver when the display device includes a data driver, can be electrically connected to the first end of the control line through an output channel, and electrically connected to the second end of the control line through another output channel, and provide a control signal to the control line through the first end and the second end respectively, so as to enhance the driving capability of the control line.
  • the display panel when the display panel is a display product with a resolution of 1200 ⁇ 2000, the display panel includes 2000 rows of pixel circuits, and the number of data lines included in the display panel is 3600 columns. If one data voltage supply end of the data driver drives two columns of data lines, a data driver is required; at this time, the data driver can be electrically connected to the first end of the control line through an output channel, and electrically connected to the second end of the control line through another output channel to improve the driving capability of the control line.
  • the area labeled A0 is the effective display area
  • the area labeled SI is the data driver
  • the line labeled M11 is the first control line
  • the data driver SI is disposed below A0, and the first control line M11 is disposed between the data driver SI and the effective display area A0;
  • the data driver SI is electrically connected to the first end of the first control line M11 through the first output channel CH1 located on the left side thereof;
  • the data driver SI is electrically connected to the second end of the first control line M11 through the second output channel CH2 located on the right side thereof;
  • Both ends of the first control line M11 are driven simultaneously.
  • the second control line M12 , the third control line M13 , and the fourth control line M14 may be driven in the same manner as the first control line M11 , and are all driven simultaneously from both ends of the line.
  • the display device includes a display panel, at least two data drivers, and a plurality of control lines;
  • the data driver is disposed on a first side of the display panel, and the plurality of control lines are disposed between the data driver and an effective display area of the display panel;
  • the data driver is further configured to provide a control signal input to the control line.
  • control line may be arranged between the data driver and the effective display area of the display panel, and the data driver provides a control signal input to the control line.
  • control line is electrically connected to the at least two data drivers through at least three access points, and is used to receive a control signal provided by the data driver.
  • control line can be electrically connected to the at least two data drivers through at least three access points to receive a control signal, which can further enhance the driving capability of the control line.
  • the display device includes a first data driver and a second data driver
  • the first output channel of the first data driver is electrically connected to the first end of the control line, and the first output channel of the second data driver is electrically connected to the second end of the control line;
  • the second output channel of the first data driver and the second output channel of the second data driver are both electrically connected to the middle node of the control line;
  • the first data driver is used to provide a control signal to the control line through its first output channel and its second output channel;
  • the second data driver is used for providing a control signal to the control line through a first output channel and a second output channel thereof.
  • the number of rows of pixel circuits included in the display panel is 1840
  • the number of data lines included in the display panel is 8832
  • a driving architecture using one data voltage supply terminal to drive two columns of data lines requires 4416 data voltage supply terminals; the number of channels of each data driver is 2400, so two data drivers are required. Drive.
  • the effective display area is labeled A0
  • the first data driver is labeled SI1
  • the second data driver is labeled SI2
  • the first control line is labeled M11;
  • the first control line M11 is disposed between the data driver and the effective display area A0;
  • the first output channel CH11 of the first data driver SI1 is electrically connected to the first end of the first control line M11, and the first output channel CH21 of the second data driver SI2 is electrically connected to the second end of the first control line M11;
  • the second output channel CH12 of the first data driver SI1 and the second output channel CH22 of the second data driver SI2 are both electrically connected to the middle node N0 of the control line;
  • the first data driver SI1 provides a control signal to the first control line M11 through CH11 and CH12;
  • the second data driver SI2 provides a control signal to the first control line M11 through CH21 and CH22.
  • the driving method of the second control line M12, the driving method of the third control line M13 and the driving method of the fourth control line M14 are the same as the driving method of the first control line M11, and each line is connected to the driving signal at three positions to further enhance the driving capability of each control signal.
  • FIG. 11 is a layout diagram of the middle portion of at least one embodiment shown in FIG. 10 , illustrating the connection relationship between the connection line between two data drivers and the middle nodes of each control line.
  • M01 is a first connection line between the first source driver and the second source driver
  • M02 is a second connection line between the first source driver and the second source driver
  • M03 is a third connection line between the first source driver and the second source driver
  • M04 is a connection line between the first source driver and the second source driver
  • M01 is electrically connected to M11 through the first connection portion L1
  • M02 is electrically connected to M12 through the second connection portion L2
  • M03 is electrically connected to M13 through the third connection portion L3
  • M04 is electrically connected to M14 through the fourth connection portion L4.
  • FIG. 12 is a layout diagram of the gate metal layer in FIG. 11 , and M01 , M02 , M03 , M04 , M11 , M12 , M13 , and M14 may all be formed in the gate metal layer.
  • FIG. 13 is a layout diagram of the source/drain metal layer in FIG. 11 .
  • FIG. 14 is a layout diagram of the second conductive layer in FIG. 11 , and L1 , L2 , L3 , and L4 may be formed in the second conductive layer.
  • the display device described in at least one embodiment of the present disclosure further includes a plurality of rows of gate lines and a plurality of rows and columns of pixel circuits;
  • the pixel circuit is electrically connected to the corresponding row gate line and the corresponding column data line respectively, and is used for controlling and receiving the data voltage provided by the corresponding column data line under the control of the gate driving signal provided by the corresponding row gate line.
  • the display device may include a plurality of rows of gate lines and a plurality of rows and columns of pixel circuits.
  • the pixel circuits receive data voltages provided by data lines under the control of gate drive signals.
  • the display device described in the embodiment of the present disclosure may be a TDDI product, but is not limited thereto. In actual operation, the display device may also be other types of display products.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned display device, and the driving method includes:
  • the data driver provides a data voltage to the multiplexing module through a data voltage supply terminal
  • the data line receives the data voltage provided by the multiplexing module.
  • the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;
  • the first multiplexing control line When the gate line of row 2a-1 is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on;
  • the second multiplexing control line When the gate line in row 2a is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on.
  • the first multiplexing control line may include a first control line and a second control line
  • the second multiplexing control line may include a third control line and a fourth control line
  • the first control line and the second control line respectively control corresponding multiplexing transistors
  • the third control line and the fourth control line respectively control corresponding multiplexing transistors.
  • the corresponding multiplexing transistors when the odd-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to be turned on through the first multiplexing control line, and then the corresponding multiplexing transistors can be controlled to be turned on through the second multiplexing control line; after the even-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to be turned on through the second multiplexing control line, and then the corresponding multiplexing transistors can be controlled to be turned on through the first multiplexing control line. In this way, the frequency of the control signals on each multiplexing control line is low and the power consumption is small.
  • the display device further includes a plurality of rows of gate lines and two multiplexing control lines; a is a positive integer;
  • the second multiplexing control line When the gate line of row 2a-1 is turned on, the second multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the first multiplexing control line controls the corresponding multiplexing transistor to turn on;
  • the first multiplexing control line When the gate line in row 2a is turned on, the first multiplexing control line first controls the corresponding multiplexing transistor to turn on, and then the second multiplexing control line controls the corresponding multiplexing transistor to turn on.
  • the first multiplexing control line may include a first control line and a second control line
  • the second multiplexing control line may include a third control line and a fourth control line
  • the first control line and the second control line respectively control corresponding multiplexing transistors
  • the third control line and the fourth control line respectively control corresponding multiplexing transistors.
  • the corresponding multiplexing transistors when the odd-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to be turned on through the second multiplexing control line, and then the corresponding multiplexing transistors can be controlled to be turned on through the first multiplexing control line; after the even-numbered row gate lines are turned on, the corresponding multiplexing transistors can be controlled to be turned on through the first multiplexing control line, and then the corresponding multiplexing transistors can be controlled to be turned on through the second multiplexing control line. In this way, the frequency of the control signals on each multiplexing control line is low and the power consumption is small.
  • the first multiplexing control line includes a first control line M11 that controls the first transistor T1
  • the second multiplexing control line includes a third control line M13 that controls the third transistor T3 ;
  • the terminal labeled S1 is a first data voltage supply terminal
  • the pixel circuit labeled P11 is the first row and first column, and the pixel circuit labeled P13 is the first row and third column;
  • P11 and P13 are both electrically connected to the first row gate line GT1, P11 is electrically connected to the first column data line D1, and P13 is electrically connected to the third column data line D3;
  • the pixel circuit labeled P21 is the second row and first column, and the pixel circuit labeled P23 is the second row and third column;
  • P21 and P23 are both electrically connected to the second row gate line GT2, P21 is electrically connected to the first column data line D1, and P23 is electrically connected to the third column data line D3;
  • the pixel circuit labeled P31 is the pixel circuit in the third row and first column
  • the pixel circuit labeled P33 is the pixel circuit in the third row and third column
  • Both P31 and P33 are electrically connected to the third row gate line GT3
  • P31 is electrically connected to the first column data line D1
  • P33 is electrically connected to the third column data line D3.
  • the potential of the first gate driving signal output by GT1 first rises from a low voltage to a high voltage, and then the control signal output by M11 rises from a low voltage to a high voltage, and T1 is turned on to write the data voltage provided by S1 into the first column data line D1.
  • P11 receives the data voltage provided by D1;
  • the potential of the first gate driving signal output by GT1 first rises from a low voltage to a high voltage, and then the control signal output by M13 rises from a low voltage to a high voltage, and T3 is turned on to write the data voltage provided by S1 into the third column data line D3.
  • P13 receives the data voltage provided by D3;
  • T1 and T3 are n-type transistors.
  • At least one embodiment shown in FIG. 15 can be driven in a bow shape during operation, that is, as shown in FIG. 18 ,
  • GT1 is turned on first, then in the first time period P1, M11 outputs a high voltage signal, M11 first controls T1 to turn on, and writes the data voltage into P11, then in the second time period P2, M13 outputs a high voltage signal, M13 controls T3 to turn on, and writes the data voltage into P13;
  • GT2 is turned on, and then in the third time period P3, M13 outputs a high voltage signal, M13 first controls T3 to turn on, and writes the data voltage into P23, and then in the fourth time period P4, M11 outputs a high voltage signal, and M11 controls T1 to turn on, and writes the data voltage into P21;
  • GT3 is turned on, and then in the fifth time period P5, M11 outputs a high voltage signal, M11 first controls T1 to turn on, and writes the data voltage to P31, and then in the sixth time period P6, M13 outputs a high voltage signal, and M13 controls T3 to turn on, and writes the data voltage to P33.
  • FIG. 18 is a timing diagram of operation of at least one embodiment shown in FIG. 15 .
  • the frequencies of the control signal provided by M11 and the control signal provided by M13 are relatively low, which is beneficial to reducing power consumption.
  • the width-to-length ratio of each multiplexing transistor may be greater than or equal to 50 and less than or equal to 100, but is not limited thereto.

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Abstract

本公开提供一种多路复用电路、复用模组、显示装置和驱动方法。多路复用电路分别与M个数据电压提供端和多列数据线电连接，多路复用电路包括N个复用控制线和N个复用电路，第n复用电路包括M个复用子电路；第n复用控制线包括M条控制线；第n复用电路包括的第m复用子电路分别与第n复用控制线包括的第m条控制线、第m数据电压提供端和相应的数据线电连接，用于在第m条控制线提供的控制信号的控制下，将第m数据电压提供端提供的数据电压写入所述相应的数据线；N和M都为大于1的整数，n为小于或等于N的正整数，m为小于或等于M的正整数。本公开能够在保证显示产品分辨率不变的情况下，使得数据驱动器的使用数量减少。

Description

多路复用电路、复用模组、显示装置和驱动方法
相关申请的交叉引用
本申请主张在2023年6月30日在中国提交的中国专利申请号No.202310812831.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种多路复用电路、复用模组、显示装置和驱动方法。
背景技术
在相关技术中，在显示产品中，数据驱动器的数量较多，而数据驱动器的价格较高，导致目前的显示产品的成本较高。
发明内容
在一个方面中，本公开实施例提供一种多路复用电路，分别与M个数据电压提供端和多列数据线电连接，所述多路复用电路包括N个复用控制线和N个复用电路，第n复用电路包括M个复用子电路；第n复用控制线包括M条控制线；
第n复用电路包括的第m复用子电路分别与第n复用控制线包括的第m条控制线、第m数据电压提供端和相应的数据线电连接，用于在所述第m条控制线提供的控制信号的控制下，将所述第m数据电压提供端提供的数据电压写入所述相应的数据线；
N和M都为大于1的整数，n为小于或等于N的正整数，m为小于或等于M的正整数。
可选的，所述多路复用电路包括第一复用控制线、第二复用控制线、第一复用电路和第二复用电路；
所述第一复用控制线包括第一控制线和第二控制线；所述第二复用控制线包括第三控制线和第四控制线；
所述第一复用电路包括第一复用子电路和第二复用子电路；所述第二复用电路包括第三复用子电路和第四复用子电路；
所述第一复用子电路分别与所述第一控制线、第一数据电压提供端和第一列数据线电连接，用于在所述第一控制线提供的第一控制信号的控制下，将所述第一数据电压提供端提供的数据电压写入所述第一列数据线；
所述第二复用子电路分别与所述第二控制线、第二数据电压提供端和第二列数据线电连接，用于在所述第二控制线提供的第二控制信号的控制下，将所述第二数据电压提供端提供的数据电压写入所述第二列数据线；
所述第三复用子电路分别与所述第三控制线、所述第一数据电压提供端和第三列数据线电连接，用于在所述第三控制线提供的第三控制信号的控制下，将所述第一数据电压提供端提供的数据电压写入所述第三列数据线；
所述第四复用子电路分别与所述第四控制线、所述第二数据电压提供端和第四列数据线电连接，用于在所述第四控制线提供的第四控制信号的控制下，将所述第二数据电压提供端提供的数据电压写入所述第四列数据线。
可选的，所述第一复用子电路包括第一晶体管，所述第二复用子电路包括第二晶体管；
所述第一晶体管的栅极与所述第一控制线电连接，所述第一晶体管的第一极与所述第一数据电压提供端电连接，所述第一晶体管的第二极与所述第一列数据线电连接；
所述第二晶体管的栅极与所述第二控制线电连接，所述第二晶体管的第一极与所述第二数据电压提供端电连接，所述第二晶体管的第二极与所述第二列数据线电连接。
可选的，所述第一晶体管和所述第二晶体管都为n型晶体管；或者，所述第一晶体管和所述第二晶体管都为p型晶体管。
可选的，所述第三复用子电路包括第三晶体管，所述第四复用子电路包括第四晶体管；
所述第三晶体管的栅极与所述第三控制线电连接，所述第三晶体管的第一极与所述第一数据电压提供端电连接，所述第三晶体管的第二极与所述第三列数据线电连接；
所述第四晶体管的栅极与所述第四控制线电连接，所述第四晶体管的第一极与所述第二数据电压提供端电连接，所述第四晶体管的第二极与所述第四列数据线电连接。
可选的，所述第三晶体管和所述第四晶体管都为n型晶体管；或者，所述第三晶体管和所述第四晶体管都为p型晶体管。
本公开实施例还提供了一种复用模组，包括多个上述的多路复用电路。
本公开实施例还提供了一种显示装置，包括数据驱动器、多列数据线和上述的复用模组；
所述数据驱动器用于通过数据电压提供端为所述复用模组提供数据电压；
所述数据线用于接收复用模组提供的数据电压。
可选的，所述数据驱动器通过相应的至少一个输出通道为每一控制线提供控制信号。
可选的，所述显示装置包括显示面板、一个数据驱动器和多条控制线；
所述数据驱动器通过设置于所述显示面板的第一侧边，所述多条控制线设置于所述数据驱动器与所述显示面板的有效显示区域之间；
所述数据驱动器还用于提供输入至所述控制线的控制信号。
可选的，所述控制线包括第一端部和第二端部；
所述数据驱动器的第一输出通道与所述第一端部电连接，所述数据驱动器的第二输出通道与所述第二端部电连接，所述数据驱动器用于通过所述第一输出通道向所述第一端部提供控制信号，通过所述第二输出通道向所述第二端部提供控制信号。
可选的，所述显示装置包括显示面板、至少两个数据驱动器和多条控制线；
所述数据驱动器通过设置于所述显示面板的第一侧边，所述多条控制线设置于所述数据驱动器与所述显示面板的有效显示区域之间；
所述数据驱动器还用于提供输入至所述控制线的控制信号。
可选的，所述控制线通过至少三个接入点与所述至少两个数据驱动器电连接，用于接收所述数据驱动器提供的控制信号。
可选的，所述显示装置包括第一数据驱动器和第二数据驱动器；
所述第一数据驱动器的第一输出通道与所述控制线的第一端部电连接，所述第二数据驱动器的第一输出通道与所述控制线的第二端部电连接；
所述第一数据驱动器的第二输出通道和所述第二数据驱动器的第二输出通道都与所述控制线的中间节点电连接；
所述第一数据驱动器用于通过其第一输出通道和其第二输出通道为所述控制线提供控制信号；
所述第二数据驱动器用于通过其第一输出通道和其第二输出通道为所述控制线提供控制信号。
可选的，本公开至少一实施例所述的显示装置，还包括多行栅线和多行多列像素电路；
所述像素电路分别与相应行栅线和相应列数据线电连接，用于在所述相应行栅线提供的栅极驱动信号的控制下，控制接收所述相应列数据线提供的数据电压。
本公开实施例还提供了一种驱动方法，应用于上述的显示装置，所述驱动方法包括：
数据驱动器通过数据电压提供端为复用模组提供数据电压；
数据线接收复用模组提供的数据电压。
可选的，所述显示装置还包括多行栅线和两个复用控制线；a为正整数；
当第2a-1行栅线打开时，第一复用控制线先控制相应的复用晶体管打开，之后，第二复用控制线控制相应的复用晶体管打开；
当第2a行栅线打开时，第二复用控制线先控制相应的复用晶体管打开，之后，第一复用控制线控制相应的复用晶体管打开。
可选的，所述显示装置还包括多行栅线和两个复用控制线；a为正整数；
当第2a-1行栅线打开时，第二复用控制线先控制相应的复用晶体管打开，之后，第一复用控制线控制相应的复用晶体管打开；
当第2a行栅线打开时，第一复用控制线先控制相应的复用晶体管打开，之后，第二复用控制线控制相应的复用晶体管打开。
附图说明
图1是本公开至少一实施例所述的多路复用电路的结构图；
图2是本公开至少一实施例所述的多路复用电路的电路图；
图3A是本公开至少一实施例所述的复用模组包括的部分晶体管的示意图；
图3B是在本公开至少一实施例中，M11提供的第一控制信号的波形图；
图3C是在相关技术中，复用控制线提供的复用控制信号的波形图；
图4是图3A所示的至少一实施例的布局图；
图5是图4中的栅金属层的布局图；
图6是图4中的半导体层的布局图；
图7是图4中的源漏金属层的布局图；
图8是图4中的第二导电层的布局图；
图9是本公开至少一实施例所述的显示装置的结构图；
图10是本公开至少一实施例所述的显示装置的结构图；
图11是图10所示的至少一实施例中的中间部分的布局图；
图12是图11中的栅金属层的布局图；
图13是图11中的源漏金属层的布局图；
图14是图11中的第二导电层的布局图；
图15是本公开至少一实施例所述的显示装置包括的部分像素电路与部分复用晶体管的连接关系示意图；
图16是图15所示的至少一实施例的工作时序图；
图17是图15所示的至少一实施例的工作时序图；
图18是图15所示的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其 他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的多路复用电路，分别与M个数据电压提供端和多列数据线电连接，所述多路复用电路包括N个复用控制线和N个复用电路，第n复用电路包括M个复用子电路；第n复用控制线包括M条控制线；
第n复用电路包括的第m复用子电路分别与第n复用控制线包括的第m条控制线、第m数据电压提供端和相应的数据线电连接，用于在所述第m条控制线提供的控制信号的控制下，将所述第m数据电压提供端提供的数据电压写入所述相应的数据线；
N和M都为大于1的整数，n为小于或等于N的正整数，m为小于或等于M的正整数。
在相关技术中，在TDDI(Touch and Display Driver Integration，触控与显示驱动器集成)产品中，数据驱动器的数量较多，而数据驱动器的价格较高，导致目前的TDDI产品的成本较高。基于此，本公开实施例提出了一种数据信号多路复用电路，使用至少两个复用控制线和一个数据电压提供端驱动至少两列数据线，使得采用的数据电压提供端的数目少，能够在保证显示产品分辨率不变的情况下，使得数据驱动器的使用数量减少。同时，为了减少复用控制线的负载，将复用控制线设置为包括至少两条控制线，所述至少两条控制线由数据驱动器的不同通道驱动，每条控制线驱动的晶体管的数目比起相关的复用控制线驱动的晶体管的数目减小，所述控制线的负载减小，能够有效减小所述控制线上的控制信号的上升时间和下降时间，极大程度提升了控制线的充电能力。
在本公开至少一实施例中，以N和M都等于2为例说明，但不以此为限，在实际操作时，N和M可以为大于1的整数。
本公开至少一实施例所述的多路复用电路包括第一复用控制线、第二复用控制线、第一复用电路和第二复用电路；
所述第一复用控制线包括第一控制线和第二控制线；所述第二复用控制线包括第三控制线和第四控制线；
所述第一复用电路包括第一复用子电路和第二复用子电路；所述第二复用电路包括第三复用子电路和第四复用子电路；
所述第一复用子电路分别与所述第一控制线、第一数据电压提供端和第一列数据线电连接，用于在所述第一控制线提供的第一控制信号的控制下，将所述第一数据电压提供端提供的数据电压写入所述第一列数据线；
所述第二复用子电路分别与所述第二控制线、第二数据电压提供端和第二列数据线电连接，用于在所述第二控制线提供的第二控制信号的控制下，将所述第二数据电压提供端提供的数据电压写入所述第二列数据线；
所述第三复用子电路分别与所述第三控制线、所述第一数据电压提供端和第三列数据线电连接，用于在所述第三控制线提供的第三控制信号的控制下，将所述第一数据电压提供端提供的数据电压写入所述第三列数据线；
所述第四复用子电路分别与所述第四控制线、所述第二数据电压提供端和第四列数据线电连接，用于在所述第四控制线提供的第四控制信号的控制下，将所述第二数据电压提供端提供的数据电压写入所述第四列数据线。
在具体实施时，所述多路复用电路可以包括第一复用控制线、第二复用控制线、第一复用电路和第二复用电路，第一复用控制线可以包括第一控制线和第二控制线，所述第二复用控制线可以包括第三控制线和第四控制线，第一复用子电路在第一控制信号的控制下，将第一数据电压提供端提供的数据电压写入所述第一列数据线，第二复用子电路在第二控制信号的控制下，将所述第二数据电压提供端提供的数据电压写入所述第二列数据线，第三复用子电路在第三控制信号的控制下，将所述第一数据电压提供端提供的数据电压写入所述第三列数据线；第四复用子电路在第四控制信号的控制下，将所述第二数据电压提供端提供的数据电压写入所述第四列数据线。
如图1所示，本公开至少一实施例所述的多路复用电路分别与第一数据电压提供端S1、第二数据电压提供端S2、第一列数据线D1、第二列数据线D2、第三列数据线D3和第四列数据线D4电连接，所述多路复用电路包括第一复用控制线、第二复用控制线、第一复用电路和第二复用电路；
所述第一复用控制线包括第一控制线M11和第二控制线M12，所述第二复用控制线包括第三控制线M21和第四控制线M22；
第一复用电路包括第一复用子电路11和第二复用子电路12，第二复用电路包括第三复用子电路13和第四复用子电路14；
所述第一复用子电路11分别与第一控制线M11、第一数据电压提供端S1和第一列数据线D1电连接，用于在所述第一控制线M11提供的第一控制信号的控制下，将所述第一数据电压提供端S1提供的数据电压写入第一列数据线D1；
所述第二复用子电路12分别与第二控制线M12、第二数据电压提供端S2和第二列数据线D2电连接，用于在所述第二控制线M12提供的第二控制信号的控制下，将所述第二数据电压提供端S2提供的数据电压写入第二列数据线D2；
所述第三复用子电路13分别与第三控制线M13、第一数据电压提供端S1和第三列数据线D3电连接，用于在所述第三控制线M13提供的第三控制信号的控制下，将所述第一数据电压提供端S1提供的数据电压写入所述第三列数据线D3；
所述第四复用子电路14分别与第四控制线M14、第二数据电压提供端S2和第四列数据线D4电连接，用于在所述第四控制线M14提供的第四控制信号的控制下，将所述第二数据电压提供端S2提供的数据电压写入所述第四列数据线D4。
本公开图1所示的多路复用电路的至少一实施例在工作时，第一控制线M11提供的第一控制信号和第二控制线M12提供的第二控制信号可以相同，第三控制线M13提供的第三控制信号和第四控制线M14提供的第四控制信号可以相同，第一控制线M11、第二控制线M12、第三控制线M13、第四控制线M14分别与数据驱动器的第一输出通道、所述数据驱动器的第二输出通道、所述数据驱动器的第三输出通道、所述数据驱动器的第四输出通道电连接，由数据驱动器的相应的输出通道分别为各控制线提供控制信号，每条控制线驱动的晶体管的数目比起相关的复用控制线驱动的晶体管的数目减半，所述控制线的负载减小，能够有效减小所述控制线上的控制信号的上升时间 和下降时间，提升了各控制线的充电能力。
在本公开图1所示的多路复用电路的至少一实施例中，各控制线也可以与所述数据驱动器的至少两个输出通道电连接，以提升控制线的驱动能力。
可选的，所述第一复用子电路包括第一晶体管，所述第二复用子电路包括第二晶体管；
所述第一晶体管的栅极与所述第一控制线电连接，所述第一晶体管的第一极与所述第一数据电压提供端电连接，所述第一晶体管的第二极与所述第一列数据线电连接；
所述第二晶体管的栅极与所述第二控制线电连接，所述第二晶体管的第一极与所述第二数据电压提供端电连接，所述第二晶体管的第二极与所述第二列数据线电连接。
可选的，所述第一晶体管和所述第二晶体管都为n型晶体管；或者，所述第一晶体管和所述第二晶体管都为p型晶体管。
可选的，所述第三复用子电路包括第三晶体管，所述第四复用子电路包括第四晶体管；
所述第三晶体管的栅极与所述第三控制线电连接，所述第三晶体管的第一极与所述第一数据电压提供端电连接，所述第三晶体管的第二极与所述第三列数据线电连接；
所述第四晶体管的栅极与所述第四控制线电连接，所述第四晶体管的第一极与所述第二数据电压提供端电连接，所述第四晶体管的第二极与所述第四列数据线电连接。
可选的，所述第三晶体管和所述第四晶体管都为n型晶体管；或者，所述第三晶体管和所述第四晶体管都为p型晶体管。
如图2所示，在图1所示的多路复用电路的至少一实施例的基础上，所述第一复用子电路包括第一晶体管T1，所述第二复用子电路包括第二晶体管T2；
所述第一晶体管T1的栅极与所述第一控制线M11电连接，所述第一晶体管T1的源极与所述第一数据电压提供端S1电连接，所述第一晶体管T1的漏极与所述第一列数据线D1电连接；
所述第二晶体管T2的栅极与所述第二控制线M12电连接，所述第二晶体管T2的源极与所述第二数据电压提供端S2电连接，所述第二晶体管T2的漏极与所述第二列数据线D2电连接；
所述第三复用子电路包括第三晶体管T3，所述第四复用子电路包括第四晶体管T4；
所述第三晶体管T3的栅极与所述第三控制线M13电连接，所述第三晶体管T3的源极与所述第一数据电压提供端S1电连接，所述第三晶体管T3的漏极与所述第三列数据线D3电连接；
所述第四晶体管T4的栅极与所述第四控制线M14电连接，所述第四晶体管T4的源极与所述第二数据电压提供端S2电连接，所述第四晶体管T4的漏极与所述第四列数据线D4电连接。
在图2所示的多路复用电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
图2所示的多路复用电路的至少一实施例在工作时，数据提供周期可以包括第一复用阶段和第二复用阶段；
在第一复用阶段，M11和M12都提供高电压信号，T1和T2都打开，S1与D1之间连通，S2与D2之间连通，通过S1为D1提供数据电压，通过S2为D2提供数据电压；
在第二复用阶段，M13和M14都提供高电压信号，T3和T4都打开，S1与D3之间连通，S2与D4之间连通，通过S1为D3提供数据电压，通过S2为D4提供数据电压。
本公开实施例所述的复用模组包括多个上述的多路复用电路。
图3A示出了本公开至少一实施例所述的复用模组包括的部分晶体管的示意图。
如图3A所示，本公开至少一实施例所述的复用模组包括第一多路复用电路和第二多路复用电路；
所述第一多路复用电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4；
所述第二多路复用电路包括第五晶体管T5、第六晶体管T6、第七晶体管 T7和第八晶体管T8；
所述第一晶体管T1的栅极与所述第一控制线M11电连接，所述第一晶体管T1的源极与所述第一数据电压提供端S1电连接，所述第一晶体管T1的漏极与所述第一列数据线D1电连接；
所述第二晶体管T2的栅极与所述第二控制线M12电连接，所述第二晶体管T2的源极与所述第二数据电压提供端S2电连接，所述第二晶体管T2的漏极与所述第二列数据线D2电连接；
所述第三晶体管T3的栅极与所述第三控制线M13电连接，所述第三晶体管T3的源极与所述第一数据电压提供端S1电连接，所述第三晶体管T3的漏极与所述第三列数据线D3电连接；
所述第四晶体管T4的栅极与所述第四控制线M14电连接，所述第四晶体管T4的源极与所述第二数据电压提供端S2电连接，所述第四晶体管T4的漏极与所述第四列数据线D4电连接；
所述第五晶体管T5的栅极与所述第一控制线M11电连接，所述第五晶体管T5的源极与第三数据电压提供端S3电连接，所述第五晶体管T5的漏极与所述第五列数据线D5电连接；
所述第六晶体管T6的栅极与所述第二控制线M12电连接，所述第六晶体管T6的源极与所述第四数据电压提供端S4电连接，所述第六晶体管T6的漏极与所述第六列数据线D6电连接；
所述第七晶体管T7的栅极与所述第三控制线M13电连接，所述第七晶体管T7的源极与所述第三数据电压提供端S3电连接，所述第七晶体管T7的漏极与所述第七数据线D7电连接；
所述第八晶体管T8的栅极与所述第四控制线M14电连接，所述第八晶体管T8的源极与所述第四数据电压提供端S4电连接，所述第八晶体管T8的漏极与所述第八数据线D8电连接
在图3A所示的至少一实施例中，T1、T2、T3、T4、T5、T6、T7和T8都为n型晶体管，但不以此为限。
本公开图3A所示的至少一实施例在工作时，数据提供周期可以包括第一复用阶段和第二复用阶段；
在第一复用阶段，M11和M12都提供高电压信号，T1、T2、T5和T6都打开，S1与D1之间连通，S2与D2之间连通，通过S1为D1提供数据电压，通过S2为D2提供数据电压；S3与D5之间连通，S4与D6之间连通，通过S3为D5提供数据电压，通过S4为D6提供数据电压；
在第二复用阶段，M13和M14都提供高电压信号，T3、T4、T7和T8都打开，S1与D3之间连通，S2与D4之间连通，通过S1为D3提供数据电压，通过S2为D4提供数据电压；S3与D7之间连通，S4与D8之间连通，通过S3为D7提供数据电压，通过S4为D8提供数据电压。
本公开图3A所示的至少一实施例采用的晶体管的数目减半，并且，S1驱动D1和D3，S2驱动D2和D4，当S1提供正极性数据电压时，D1和D3提供正极性数据电压，当S2提供负极性数据电压时，D2和D4提供负极性数据电压，从而实现像素区相邻的数据线上的数据电压极性相反的目的。
图3B是在本公开至少一实施例中，M11提供的第一控制信号的波形图；
图3C是在相关技术中，复用控制线提供的复用控制信号的波形图。
对比图3B和图3C，M11提供的第一控制信号的上升时间和下降时间较短，而在相关技术中，复用控制线提供的复用控制信号M1的上升时间和下降时间较长。
在本公开至少一实施例中，M11提供的第一控制信号的上升时间可以为0.26μs，M11提供的第一控制信号的下降时间可以为0.25μs，在相关技术中，所述复用控制信号M1的上升时间为0.46μs，所述复用控制信号M1的下降时间为0.45μs；由上可知，在本公开至少一实施例中，控制信号对充电更有利。
图4是图3A所示的至少一实施例的布局图。
图5是图4中的栅金属层的布局图。
在图5中，标号为G1的为T1的栅极，标号为G2的为T2的栅极，标号为G3的为T3的栅极，标号为G4的为T4的栅极，标号为G5的为T5的栅极，标号为G6的为T6的栅极，标号为G7的为T7的栅极，标号为G8的为T8的栅极。
图6是图4中的半导体层的布局图。
在图6中，标号为A1的为T1的有源图形，标号为A2的为T2的有源图形，标号为A3的为T3的有源图形，标号为A4的为T4的有源图形，标号为A5的为T5的有源图形，标号为A6的为T6的有源图形，标号为A7的为T7的有源图形，标号为A8的为T8的有源图形。
图7是图4中的源漏金属层的布局图。
在图7中，标号为SD1的为T1的源漏极图形，标号为SD2的为T2的源漏极图形，标号为SD3的为T3的源漏极图形，标号为SD4的为T4的源漏极图形，标号为SD5的为T5的源漏极图形，标号为SD6的为T6的源漏极图形，标号为SD7的为T7的源漏极图形，标号为SD8的为T8的源漏极图形。
图8是图4中的第二导电层的布局图。
在图4中，栅金属层、半导体层、源漏金属层和第二导电层可以沿着远离基底的方向依次排列，在源漏金属层与第二导电层之间可以设置有第一导电层，所述第一导电层可以为整层的公共电极层；所述第二导电层可以为像素电极层，在显示区域，所述第二导电层可以包括像素电极；所述第一导电层和所述第二导电层可以都由ITO(氧化铟锡)制成，但不以此为限。
在本公开至少一实施例中，在源漏金属层和第一导电层之间还可以设置有触控电极层，但不以此为限。
本公开实施例所述的显示装置包括数据驱动器、多列数据线和上述的复用模组；
所述数据驱动器用于通过数据电压提供端为所述复用模组提供数据电压；
所述数据线用于接收复用模组提供的数据电压。
在本公开实施例中，所述显示装置可以包括数据驱动器和上述的复用模组，数据驱动器通过数据电压提供端为复用电阻提供数据电压至相应的数据线。
可选的，所述数据驱动器通过相应的至少一输出通道为每一所述控制线提供控制信号，以提升各控制线的驱动能力。
在本公开至少一实施例中，所述显示装置包括显示面板、一个数据驱动器和多条控制线；
所述数据驱动器通过设置于所述显示面板的第一侧边，所述多条控制线设置于所述数据驱动器与所述显示面板的有效显示区域之间；
所述数据驱动器还用于提供输入至所述控制线的控制信号。
在具体实施时，所述显示装置可以仅包括一个数据驱动器，控制线可以设置于数据驱动器和显示面板的有效显示区域之间，所述数据驱动器向所述控制线提供控制信号。
可选的，所述控制线包括第一端部和第二端部；
所述数据驱动器的第一输出通道与所述第一端部电连接，所述数据驱动器的第二输出通道与所述第二端部电连接，所述数据驱动器用于通过所述第一输出通道向所述第一端部提供控制信号，通过所述第二输出通道向所述第二端部提供控制信号。
在具体实施时，当所述显示装置包括一个数据驱动器时，所述数据驱动器可以通过一输出通道与所述控制线的第一端部电连接，通过另一输出通道与所述控制线的第二端部电连接，分别通过第一端部和第二端部向所述控制线提供控制信号，以提升所述控制线的驱动能力。
在本公开一实施例中，当显示面板为分辨率为1200×2000的显示产品，显示面板包括2000行像素电路，所述显示面板包括的数据线的数量为3600列，若数据驱动器的一个数据电压提供端驱动两列数据线，则需要采用一颗数据驱动器；此时，所述数据驱动器可以通过一输出通道与控制线的第一端部电连接，通过另一输出通道与所述控制线的第二端部电连接，以提升控制线的驱动能力。
如图9所示，标号为A0的为有效显示区域，标号为SI的为数据驱动器；
标号为M11的为第一控制线；
数据驱动器SI设置于A0下方，第一控制线M11设置于数据驱动器SI和有效显示区域A0之间；
所述数据驱动器SI通过位于其左侧的第一输出通道CH1与第一控制线M11的第一端部电连接；
所述数据驱动器SI通过位于其右侧的第二输出通道CH2与第一控制线M11的第二端部电连接；
从所述第一控制线M11的两端同时驱动。
在本公开至少一实施例中，第二控制线M12、第三控制线M13和第四控制线M14的驱动方式可以与第一控制线M11的驱动方式相同，均从走线的两端同时驱动。
在本公开至少一实施例中，所述显示装置包括显示面板、至少两个数据驱动器和多条控制线；
所述数据驱动器通过设置于所述显示面板的第一侧边，所述多条控制线设置于所述数据驱动器与所述显示面板的有效显示区域之间；
所述数据驱动器还用于提供输入至所述控制线的控制信号。
在具体实施时，当所述显示装置包括至少两个数据驱动器时，所述控制线可以设置于数据驱动器与显示面板的有效显示区域之间，由数据驱动器提供输入至控制线的控制信号。
在本公开至少一实施例中，所述控制线通过至少三个接入点与所述至少两个数据驱动器电连接，用于接收所述数据驱动器提供的控制信号。
在具体实施时，所述控制线可以通过至少三个接入点与所述至少两个数据驱动器电连接，以接收控制信号，能进一步提升控制线的驱动能力。
可选的，所述显示装置包括第一数据驱动器和第二数据驱动器；
所述第一数据驱动器的第一输出通道与所述控制线的第一端部电连接，所述第二数据驱动器的第一输出通道与所述控制线的第二端部电连接；
所述第一数据驱动器的第二输出通道和所述第二数据驱动器的第二输出通道都与所述控制线的中间节点电连接；
所述第一数据驱动器用于通过其第一输出通道和其第二输出通道为所述控制线提供控制信号；
所述第二数据驱动器用于通过其第一输出通道和其第二输出通道为所述控制线提供控制信号。
在具体实施时，对于分辨率为1840×2944的显示面板，显示面板包括的像素电路的行数为1840行，显示面板包括的数据线的数量为8832列，使用一个数据电压提供端驱动两列数据线的驱动架构，需要的数据电压提供端的数目为4416；每一颗数据驱动器的通道数为2400个，则需要采用两颗数据 驱动器。
如图10所示，标号为A0的为有效显示区域，标号为SI1的为第一数据驱动器，标号为SI2的为第二数据驱动器；标号为M11的为第一控制线；
第一控制线M11设置于数据驱动器与有效显示区域A0之间；
第一数据驱动器SI1的第一输出通道CH11与所述第一控制线M11的第一端部电连接，所述第二数据驱动器SI2的第一输出通道CH21与所述第一控制线M11的第二端部电连接；
第一数据驱动器SI1的第二输出通道CH12和第二数据驱动器SI2的第二输出通道CH22都与所述控制线的中间节点N0电连接；
所述第一数据驱动器SI1通过CH11和CH12为所述第一控制线M11提供控制信号；
所述第二数据驱动器SI2通过CH21和CH22为所述第一控制线M11提供控制信号。
在具体实施时，第二控制线M12的驱动方式、第三控制线M13的驱动方式和第四控制线M14的驱动方式与第一控制线M11的驱动方法相同，每根走线均为三个位置接入驱动信号，以能够进一步增强各控制信号的驱动能力。
图11是图10所示的至少一实施例中的中间部分的布局图，示出了两个数据驱动器之间的连接线与各控制线的中间节点之间的连接关系。
在图11中，标号为M01的为第一源极驱动器和第二源极驱动器之间的第一连接线，标号为M02的为第一源极驱动器和第二源极驱动器之间的第二连接线，标号为M03的为第一源极驱动器和第二源极驱动器之间的第三连接线，标号为M04的为第一源极驱动器和第二源极驱动器之间的连接线；
M01通过第一连接部L1与M11电连接，M02通过第二连接部L2与M12电连接，M03通过第三连接部L3与M13电连接，M04通过第四连接部L4与M14电连接。
图12是图11中的栅金属层的布局图，M01、M02、M03、M04、M11、M12、M13和M14可以都形成于栅金属层。
图13是图11中的源漏金属层的布局图。
图14是图11中的第二导电层的布局图，L1、L2、L3和L4可以形成于第二导电层。
本公开至少一实施例所述的显示装置还包括多行栅线和多行多列像素电路；
所述像素电路分别与相应行栅线和相应列数据线电连接，用于在所述相应行栅线提供的栅极驱动信号的控制下，控制接收所述相应列数据线提供的数据电压。
在具体实施时，所述显示装置可以包括多行栅线和多行多列像素电路，像素电路在栅极驱动信号的控制下，接收数据线提供的数据电压。
本公开实施例所述的显示装置可以为TDDI产品，但不以此为限。在实际操作时，所述显示装置也可以为其他类型的显示产品。
本公开实施例所述的驱动方法，应用于上述的显示装置，所述驱动方法包括：
数据驱动器通过数据电压提供端为复用模组提供数据电压；
数据线接收复用模组提供的数据电压。
在本公开至少一实施例中，所述显示装置还包括多行栅线和两个复用控制线；a为正整数；
当第2a-1行栅线打开时，第一复用控制线先控制相应的复用晶体管打开，之后，第二复用控制线控制相应的复用晶体管打开；
当第2a行栅线打开时，第二复用控制线先控制相应的复用晶体管打开，之后，第一复用控制线控制相应的复用晶体管打开。
其中，第一复用控制线可以包括第一控制线和第二控制线，第二复用控制线可以包括第三控制线和第四控制线，第一控制线和第二控制线分别控制相应的复用晶体管，第三控制线和第四控制线分别控制相应的复用晶体管。
在具体实施时，可以在奇数行栅线打开时，通过第一复用控制线控制相应的复用晶体管打开，再通过第二复用控制线控制相应的复用晶体管打开；在偶数行栅线打开后，通过第二复用控制线控制相应的复用晶体管打开，再由第一复用控制线控制相应的复用晶体管打开，这样，各复用控制线上的控制信号的频率较低，功耗小。
在本公开至少一实施例中，所述显示装置还包括多行栅线和两个复用控制线；a为正整数；
当第2a-1行栅线打开时，第二复用控制线先控制相应的复用晶体管打开，之后，第一复用控制线控制相应的复用晶体管打开；
当第2a行栅线打开时，第一复用控制线先控制相应的复用晶体管打开，之后，第二复用控制线控制相应的复用晶体管打开。
其中，第一复用控制线可以包括第一控制线和第二控制线，第二复用控制线可以包括第三控制线和第四控制线，第一控制线和第二控制线分别控制相应的复用晶体管，第三控制线和第四控制线分别控制相应的复用晶体管。
在具体实施时，可以在奇数行栅线打开时，通过第二复用控制线控制相应的复用晶体管打开，再通过第一复用控制线控制相应的复用晶体管打开；在偶数行栅线打开后，通过第一复用控制线控制相应的复用晶体管打开，再由第二复用控制线控制相应的复用晶体管打开，这样，各复用控制线上的控制信号的频率较低，功耗小。
如图15所示，第一复用控制线包括的第一控制线M11控制第一晶体管T1，第二复用控制线包括的第三控制线M13控制第三晶体管T3；
标号为S1的为第一数据电压提供端；
标号为P11的为第一行第一列像素电路，标号为P13的为第一行第三列像素电路；
P11和P13都与第一行栅线GT1电连接，P11与第一列数据线D1电连接，P13与第三列数据线D3电连接；
标号为P21的为第二行第一列像素电路，标号为P23的为第二行第三列像素电路；
P21和P23都与第二行栅线GT2电连接，P21与第一列数据线D1电连接，P23与第三列数据线D3电连接；
标号为P31的为第三行第一列像素电路，标号为P33的为第三行第三列像素电路；
P31和P33都与第三行栅线GT3电连接，P31与第一列数据线D1电连接，P33与第三列数据线D3电连接。
图15所示的至少一实施例在工作时，在驱动第一行像素电路时，
如图16所示，GT1输出的第一栅极驱动信号的电位先从低电压上升为高电压，之后，M11输出的控制信号由低电压上升为高电压，T1打开，以将S1提供的数据电压写入第一列数据线D1，当第一栅极驱动信号的电位为高电压时，P11接收D1提供的数据电压；
如图17所示，GT1输出的第一栅极驱动信号的电位先从低电压上升为高电压，之后，M13输出的控制信号由低电压上升为高电压，T3打开，以将S1提供的数据电压写入第三列数据线D3，当第一栅极驱动信号的电位为高电压时，P13接收D3提供的数据电压；
T1和T3为n型晶体管。
在具体实施时，如图15所示的至少一实施例在工作时，可以进行弓字形驱动，也即，如图18所示，
GT1先打开，之后，在第一时间段P1，M11输出高电压信号，M11先控制T1打开，将数据电压写入P11，之后，在第二时间段P2，M13输出高电压信号，M13再控制T3打开，将数据电压写入P13；
之后，GT2打开，然后在第三时间段P3，M13输出高电压信号，M13先控制T3打开，将数据电压写入P23，之后在第四时间段P4，M11输出高电压信号，M11再控制T1打开，将数据电压写入P21；
之后，GT3打开，然后在第五时间段P5，M11输出高电压信号，M11先控制T1打开，将数据电压写入P31，之后在第六时间段P6，M13输出高电压信号，M13再控制T3打开，将数据电压写入P33。
图18是图15所示的至少一实施例的工作时序图。
如图18所示，M11提供的控制信号和M13提供的控制信号的频率较低，有利于降低功耗。
在本公开至少一实施例中，各复用晶体管的宽长比可以大于或等于50而小于或等于100，但不以为为限。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (18)

  1. 一种多路复用电路，分别与M个数据电压提供端和多列数据线电连接，所述多路复用电路包括N个复用控制线和N个复用电路，第n复用电路包括M个复用子电路；第n复用控制线包括M条控制线；
    第n复用电路包括的第m复用子电路分别与第n复用控制线包括的第m条控制线、第m数据电压提供端和相应的数据线电连接，用于在所述第m条控制线提供的控制信号的控制下，将所述第m数据电压提供端提供的数据电压写入所述相应的数据线；
    N和M都为大于1的整数，n为小于或等于N的正整数，m为小于或等于M的正整数。
  2. 如权利要求1所述的多路复用电路，其中，所述多路复用电路包括第一复用控制线、第二复用控制线、第一复用电路和第二复用电路；
    所述第一复用控制线包括第一控制线和第二控制线；所述第二复用控制线包括第三控制线和第四控制线；
    所述第一复用电路包括第一复用子电路和第二复用子电路；所述第二复用电路包括第三复用子电路和第四复用子电路；
    所述第一复用子电路分别与所述第一控制线、第一数据电压提供端和第一列数据线电连接，用于在所述第一控制线提供的第一控制信号的控制下，将所述第一数据电压提供端提供的数据电压写入所述第一列数据线；
    所述第二复用子电路分别与所述第二控制线、第二数据电压提供端和第二列数据线电连接，用于在所述第二控制线提供的第二控制信号的控制下，将所述第二数据电压提供端提供的数据电压写入所述第二列数据线；
    所述第三复用子电路分别与所述第三控制线、所述第一数据电压提供端和第三列数据线电连接，用于在所述第三控制线提供的第三控制信号的控制下，将所述第一数据电压提供端提供的数据电压写入所述第三列数据线；
    所述第四复用子电路分别与所述第四控制线、所述第二数据电压提供端和第四列数据线电连接，用于在所述第四控制线提供的第四控制信号的控制下，将所述第二数据电压提供端提供的数据电压写入所述第四列数据线。
  3. 如权利要求2所述的多路复用电路，其中，所述第一复用子电路包括第一晶体管，所述第二复用子电路包括第二晶体管；
    所述第一晶体管的栅极与所述第一控制线电连接，所述第一晶体管的第一极与所述第一数据电压提供端电连接，所述第一晶体管的第二极与所述第一列数据线电连接；
    所述第二晶体管的栅极与所述第二控制线电连接，所述第二晶体管的第一极与所述第二数据电压提供端电连接，所述第二晶体管的第二极与所述第二列数据线电连接。
  4. 如权利要求3所述的多路复用电路，其中，所述第一晶体管和所述第二晶体管都为n型晶体管；或者，所述第一晶体管和所述第二晶体管都为p型晶体管。
  5. 如权利要求2所述的多路复用电路，其中，所述第三复用子电路包括第三晶体管，所述第四复用子电路包括第四晶体管；
    所述第三晶体管的栅极与所述第三控制线电连接，所述第三晶体管的第一极与所述第一数据电压提供端电连接，所述第三晶体管的第二极与所述第三列数据线电连接；
    所述第四晶体管的栅极与所述第四控制线电连接，所述第四晶体管的第一极与所述第二数据电压提供端电连接，所述第四晶体管的第二极与所述第四列数据线电连接。
  6. 如权利要求5所述的多路复用电路，其中，所述第三晶体管和所述第四晶体管都为n型晶体管；或者，所述第三晶体管和所述第四晶体管都为p型晶体管。
  7. 一种复用模组，包括多个如权利要求1至6中任一权利要求所述的多路复用电路。
  8. 一种显示装置，包括数据驱动器、多列数据线和如权利要求7所述的复用模组；
    所述数据驱动器用于通过数据电压提供端为所述复用模组提供数据电压；
    所述数据线用于接收复用模组提供的数据电压。
  9. 如权利要求8所述的显示装置，其中，所述数据驱动器通过相应的至 少一个输出通道为每一控制线提供控制信号。
  10. 如权利要求8所述的显示装置，其中，所述显示装置包括显示面板、一个数据驱动器和多条控制线；
    所述数据驱动器通过设置于所述显示面板的第一侧边，所述多条控制线设置于所述数据驱动器与所述显示面板的有效显示区域之间；
    所述数据驱动器还用于提供输入至所述控制线的控制信号。
  11. 如权利要求10所述的显示装置，其中，所述控制线包括第一端部和第二端部；
    所述数据驱动器的第一输出通道与所述第一端部电连接，所述数据驱动器的第二输出通道与所述第二端部电连接，所述数据驱动器用于通过所述第一输出通道向所述第一端部提供控制信号，通过所述第二输出通道向所述第二端部提供控制信号。
  12. 如权利要求9所述的显示装置，其中，所述显示装置包括显示面板、至少两个数据驱动器和多条控制线；
    所述数据驱动器通过设置于所述显示面板的第一侧边，所述多条控制线设置于所述数据驱动器与所述显示面板的有效显示区域之间；
    所述数据驱动器还用于提供输入至所述控制线的控制信号。
  13. 如权利要求12所述的显示装置，其中，所述控制线通过至少三个接入点与所述至少两个数据驱动器电连接，用于接收所述数据驱动器提供的控制信号。
  14. 如权利要求13所述的显示装置，其中，所述显示装置包括第一数据驱动器和第二数据驱动器；
    所述第一数据驱动器的第一输出通道与所述控制线的第一端部电连接，所述第二数据驱动器的第一输出通道与所述控制线的第二端部电连接；
    所述第一数据驱动器的第二输出通道和所述第二数据驱动器的第二输出通道都与所述控制线的中间节点电连接；
    所述第一数据驱动器用于通过其第一输出通道和其第二输出通道为所述控制线提供控制信号；
    所述第二数据驱动器用于通过其第一输出通道和其第二输出通道为所述 控制线提供控制信号。
  15. 如权利要求8至14中任一权利要求所述的显示装置，其中，还包括多行栅线和多行多列像素电路；
    所述像素电路分别与相应行栅线和相应列数据线电连接，用于在所述相应行栅线提供的栅极驱动信号的控制下，控制接收所述相应列数据线提供的数据电压。
  16. 一种驱动方法，应用于如权利要求8至15中任一权利要求所述的显示装置，所述驱动方法包括：
    数据驱动器通过数据电压提供端为复用模组提供数据电压；
    数据线接收复用模组提供的数据电压。
  17. 权利要求16所述的驱动方法，其中，所述显示装置还包括多行栅线和两个复用控制线；a为正整数；
    当第2a-1行栅线打开时，第一复用控制线先控制相应的复用晶体管打开，之后，第二复用控制线控制相应的复用晶体管打开；
    当第2a行栅线打开时，第二复用控制线先控制相应的复用晶体管打开，之后，第一复用控制线控制相应的复用晶体管打开。
  18. 如权利要求16所述的驱动方法，其中，所述显示装置还包括多行栅线和两个复用控制线；a为正整数；
    当第2a-1行栅线打开时，第二复用控制线先控制相应的复用晶体管打开，之后，第一复用控制线控制相应的复用晶体管打开；
    当第2a行栅线打开时，第一复用控制线先控制相应的复用晶体管打开，之后，第二复用控制线控制相应的复用晶体管打开。
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