WO2024255543A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024255543A1
WO2024255543A1 PCT/CN2024/094323 CN2024094323W WO2024255543A1 WO 2024255543 A1 WO2024255543 A1 WO 2024255543A1 CN 2024094323 W CN2024094323 W CN 2024094323W WO 2024255543 A1 WO2024255543 A1 WO 2024255543A1
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WIPO (PCT)
Prior art keywords
transistor
signal line
display panel
layer
anode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/094323
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English (en)
French (fr)
Inventor
李硕
侯鹏
石领
荣坤
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/880,738 priority Critical patent/US20260007010A1/en
Publication of WO2024255543A1 publication Critical patent/WO2024255543A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel and a display device.
  • OLED display panels have been widely used due to their advantages of self-luminescence, low driving voltage, and fast response speed.
  • OLED display panels generally include: multiple pixel units, each pixel unit includes a light-emitting unit and a pixel circuit connected to the light-emitting unit, and the light-emitting unit includes an anode, a light-emitting layer located on the anode, and a cathode located on the light-emitting layer. Therefore, the flatness of the anode of the light-emitting unit affects the color separation of a light-emitting unit.
  • the pixel circuit under the anode has relatively complex electronic components (such as transistors, storage capacitors, etc.) and wiring structures, the flatness of the anode is not very ideal. Therefore, the current display panel and display device still need to be improved.
  • the present application provides a display panel and a method for manufacturing the same.
  • the display panel has first pixel circuits and second pixel circuits alternately arranged along a first direction, and the first pixel circuits and the second pixel circuits are symmetrically arranged along a second direction;
  • the anode layer includes a first anode corresponding to the first sub-pixel and a second anode corresponding to the second sub-pixel.
  • the first anode is symmetrical about the first boundary of the first pixel circuit
  • the second anode is symmetrical about the second boundary of the second pixel circuit
  • the first boundary of the first pixel circuit is parallel to the second boundary of the second pixel circuit;
  • the second signal line includes a first part corresponding to the first pixel circuit and a second part corresponding to the second pixel circuit.
  • the part located in the first sub-pixel area is symmetrical about the first boundary of the first pixel circuit
  • the part located in the second sub-pixel area is symmetrical about the second boundary of the second pixel circuit.
  • the distance between the first signal line and the second signal line is greater than or equal to 2.5 ⁇ m, or the distance between the second signal line and the third signal line is greater than or equal to 2.5 ⁇ m, and the widths of the first signal line, the second signal line and the third signal line are independently greater than or equal to 2 ⁇ m.
  • the first auxiliary metal line is arranged at a projected position of a first boundary of the first pixel circuit, and the first auxiliary metal line is symmetrical about the first boundary of the first pixel circuit, or the first auxiliary metal line is arranged on a second boundary of the second pixel circuit, and the first auxiliary metal line is symmetrical about the second boundary of the second pixel circuit.
  • the width of the first auxiliary metal line is greater than or equal to 2 ⁇ m.
  • the anode layer further includes a third anode corresponding to a third sub-pixel, an orthographic projection of the third anode on the substrate overlaps with the first pixel circuit and the second pixel circuit respectively, and the third anode has a symmetry axis extending along the first direction;
  • the substrate further includes a first reset power line, a second reset power line, and a third reset power line, and the first reset power line, the second reset power line, and the third reset power line are mesh-connected.
  • the second metal layer also includes a second auxiliary metal line and a third auxiliary metal line, and the orthographic projections of the second auxiliary metal line and the third auxiliary metal line on the substrate have at least partial overlaps with the orthographic projection of the third anode on the substrate; the second auxiliary metal line and the third auxiliary metal line are symmetrically distributed along the second direction.
  • the display panel further includes first to third gate layers stacked sequentially on the base substrate, the first to third gate layers are all located between the base substrate and the first metal layer, and the projection of the third gate layer in the projection area of the third anode is symmetrical with the projection of the second metal layer in the projection area of the third anode along the first direction.
  • the display panel further includes a pixel defining layer, the pixel defining layer having first to third openings, the first opening corresponding to the first anode, the second opening corresponding to the second anode, and the third opening corresponding to the third anode.
  • the first opening and the second opening include 3 via holes in the projection area of the base substrate, and the third opening includes 1.5 via holes in the projection area of the base substrate.
  • the first signal line is a driving power line of the display panel
  • the second signal line is an auxiliary driving power line
  • the third signal line is a data signal line of the display panel.
  • the first metal layer is a second source-drain electrode layer
  • the second metal layer is a first source-drain electrode layer
  • the pixel circuit comprises:
  • a gate of the first transistor is connected to a first reset signal line, a first electrode of the first transistor is connected to a first reset power supply line, and a second electrode of the first transistor is connected to a third node;
  • a gate of the second transistor is connected to a first gate signal line included in the display panel, a first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to the third node;
  • a third transistor wherein a gate of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to the third node;
  • a fourth transistor wherein a gate of the fourth transistor is connected to a second gate signal line included in the display panel, and a first electrode of the fourth transistor is connected to a data signal line included in the display panel, The second electrode of the fourth transistor is connected to the second node;
  • a fifth transistor wherein a gate of the fifth transistor is connected to the light emitting control signal line, a first electrode of the fifth transistor is connected to a driving power line included in the display panel, and a second electrode of the fifth transistor is connected to the second node;
  • a sixth transistor wherein a gate of the sixth transistor is connected to the light-emitting control signal line, a first electrode of the sixth transistor is connected to the third node, and a second electrode of the sixth transistor is connected to the light-emitting unit;
  • a seventh transistor wherein a gate of the seventh transistor is connected to a second gate signal line included in the display panel, a first electrode of the seventh transistor is connected to a second reset power line, and a second electrode of the seventh transistor is connected to the light emitting unit;
  • an eighth transistor wherein a gate of the eighth transistor is connected to the second reset signal line, a first electrode of the eighth transistor is connected to a third reset power line included in the display panel, and a second electrode of the eighth transistor is connected to the second node;
  • a storage capacitor one end of which is connected to the driving power line, and the other end of which is connected to the first node.
  • a display device in a second aspect of the present application, includes the display panel.
  • FIG1 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of a partial structure of another display panel provided in an embodiment of the present application.
  • FIG3 is a schematic diagram of a partial structure of the first source and drain layer corresponding to FIG2 ;
  • FIG4 is a schematic diagram of a partial structure of a second source and drain layer corresponding to FIG2 ;
  • FIG5 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application.
  • FIG6 is a timing diagram corresponding to FIG5;
  • FIG7 is a cross-sectional view of an AA (or BB) region provided in an embodiment of the present application.
  • FIG8 is a cross-sectional view of another AA (or BB) region provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of a circuit structure provided in an embodiment of the present application.
  • FIG10 is a schematic diagram of a circuit structure provided in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer and an oxide layer of a display panel provided in an embodiment of the present application;
  • FIG. 12 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer and a third gate layer of a display panel provided in an embodiment of the present application;
  • FIG. 13 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a display panel provided in an embodiment of the present application;
  • FIG. 14 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first source-drain electrode layer, a second source-drain electrode layer, an anode layer, and a pixel defining layer of a display panel provided in an embodiment of the present application;
  • FIG15 is a cross-sectional view of a CC region provided in an embodiment of the present application.
  • FIG16 is a schematic diagram of a partial structure of a first source and drain layer provided in an embodiment of the present application.
  • 17 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer and a first source and drain electrode layer of another display panel provided in an embodiment of the present application;
  • FIG18 is a partial schematic diagram of a first source-drain electrode layer of another display panel provided in an embodiment of the present application.
  • 19 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of another display panel provided by an embodiment of the present application;
  • 20 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first source-drain electrode layer, a second source-drain electrode layer, an anode layer, and a pixel defining layer of another display panel provided in an embodiment of the present application;
  • 21 is a schematic diagram of partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, and a first source and drain electrode layer of another display panel provided in an embodiment of the present application;
  • 22 and 23 are partial superimposed schematic diagrams of a via hole and an opening of a pixel defining layer of a display panel in the related art
  • 24 and 25 are schematic diagrams of partial superposition of a via hole and an opening of a pixel defining layer of a display panel provided in an embodiment of the present application.
  • the transistors used in all embodiments of the present application can be field effect transistors or other devices with the same characteristics.
  • the transistors used in the embodiments of the present application are mainly switch transistors. Since the source and drain of the switch transistor used here are symmetrical, the source and drain are interchangeable.
  • the source is referred to as the first pole
  • the drain is referred to as the second pole
  • the drain is referred to as the first pole
  • the source is referred to as the second pole.
  • the middle end of the transistor is defined as the gate
  • the signal input end is the source
  • the signal output end is the drain.
  • the switch transistor used in the embodiment of the present application may include any one of a P-type switch transistor and an N-type switch transistor, wherein the P-type switch transistor is turned on when the gate is low and is turned off when the gate is high, and the N-type switch transistor is turned on when the gate is high and is turned off when the gate is low.
  • multiple signals in each embodiment of the present application correspond to effective potentials and invalid potentials. The effective potential and invalid potential only represent that the potential of the signal has two state quantities, and do not represent that the effective potential or invalid potential in the full text has a specific value.
  • the display panel 10 may include a substrate 101 and a plurality of pixel units 102 .
  • At least one of the plurality of pixel units 102 includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel each include a pixel circuit and a light-emitting element.
  • the pixel circuits in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the gate signal line, the data signal line, and the light-emitting signal line, and the pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the gate signal line and the light-emitting signal line, and output a corresponding current to the light-emitting element.
  • the light-emitting elements of the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the pixel circuits of the sub-pixels in which they are located, and the light-emitting elements are configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which they are located.
  • FIG. 2 is a schematic diagram of a partial structure of another display panel provided by an embodiment of the present application.
  • a plurality of pixel circuits are arranged along a first direction X
  • a plurality of second pixel circuits 1022 are arranged along a second direction Y.
  • the first direction X is perpendicular to the second direction Y, for example, the first direction X is a pixel row direction
  • the second direction Y is a pixel column direction.
  • the plurality of first pixel circuits are arranged along a first direction X
  • a plurality of second pixel circuits 1021 are arranged along a second direction Y.
  • the first pixel circuits 1021 and the second pixel circuits 1022 are alternately arranged along the first direction, and each of the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 includes a first boundary and a second boundary extending along the second direction.
  • a pixel unit may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel.
  • the shape of the sub-pixels in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the pixel units may be arranged horizontally in parallel, vertically in parallel, or in a herringbone manner.
  • FIG. 2 shows the positions of the first sub-pixel, the second sub-pixel, and the third sub-pixel arranged in a herringbone manner. Among them.
  • the first sub-pixel 1031 is a red sub-pixel
  • the second sub-pixel 1032 is a blue sub-pixel
  • the third sub-pixel 1033 is a green sub-pixel.
  • the first pixel circuit 1021 and the second pixel circuit 1022 do not necessarily correspond to the first sub-pixel and the second sub-pixel, that is, the first pixel circuit 1021 and the first sub-pixel 1031 connected thereto do not necessarily correspond to each other.
  • the first pixel circuit 1021 can be a pixel circuit for controlling the first sub-pixel 1031, or a pixel circuit for controlling the third sub-pixel 1033, or a control circuit for other pixels, which is determined by the layout design of the pixel circuit and is not specifically limited in this application.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • Figure 5 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application. As shown in Figure 5, the pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a storage capacitor Cst.
  • the gate of the seventh transistor T7 can be connected to the first reset signal line Reset_H, the first electrode of the seventh transistor T7 can be connected to the second reset power line Vinit2, and the second electrode of the seventh transistor T7 can be connected to the light emitting unit.
  • the seventh transistor T7 can also be called a reset transistor.
  • the gate of the fourth transistor T4 can be connected to the first gate signal line Gate_P, the first electrode of the fourth transistor T4 can be connected to the data signal line Data, and the second electrode of the fourth transistor T4 can be connected to the second node N2. That is, the fourth transistor T4 can be a data writing transistor in the pixel circuit.
  • the gate of the fifth transistor T5 can be connected to the light emitting control signal line EM, the first electrode of the fifth transistor T5 can be connected to the driving power line VDD, and the second electrode of the fifth transistor T5 can be connected to the second node N2.
  • the transistor T5 may also be referred to as a light emission control transistor.
  • the gate of the first transistor T1 may be connected to the second reset signal line Reset_P, the first electrode of the first transistor T1 may be connected to the first reset power line Vinit1, and the second electrode of the first transistor T1 may be connected to the third node N3.
  • the first transistor T1 may also be called a reset transistor.
  • the gate of the sixth transistor T6 can be connected to the light emitting control signal line EM, the first electrode of the sixth transistor T6 can be connected to the third node N3, and the second electrode of the fifth transistor can be connected to the light emitting unit. Since the gate of the sixth transistor T6 is connected to the light emitting control signal line EM, the sixth transistor T6 can also be called a light emitting control transistor.
  • the gate of the second transistor T2 may be connected to the second gate signal line Gate_N, the first electrode of the second transistor T2 may be connected to the third node N3, and the second electrode of the second transistor T2 may be connected to the first node N1.
  • the second transistor T2 may also be called a compensation transistor.
  • the gate of the third transistor T3 may be connected to the first node N1, the first electrode of the third transistor T3 may be connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 may also be called a driving transistor.
  • the gate of the eighth transistor T8 can be connected to the first reset signal line Reset_H, that is, the gate of the eighth transistor T8 and the gate of the seventh transistor T7 share the first reset signal line Reset_H, the first electrode of the eighth transistor T8 can be connected to the third reset power line Vinit3, and the second electrode of the eighth transistor T8 can be connected to the second node N2.
  • the eighth transistor T8 can also be called a reset transistor.
  • the storage capacitor Cst may be connected to the driving power line VDD, and the other end of the storage capacitor Cst may be connected to the first node N1.
  • the storage capacitor Cst may include two capacitor plates Cst1 and Cst2.
  • the capacitor plate Cst1 may be referred to as one end of the storage capacitor Cst, the first end or the first storage capacitor electrode
  • the capacitor plate Cst2 may be referred to as the other end of the storage capacitor Cst, the second end or the second storage capacitor electrode.
  • the second transistor T2 is an N-type transistor
  • the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-type transistors.
  • each N-type transistor recorded in the embodiment of the present application may be an oxide transistor, and each P-type transistor may be a low temperature polysilicon (LTPS) transistor.
  • the oxide material may include indium gallium zinc oxide (IGZO), that is, the oxide transistor may be an IGZO transistor.
  • the pixel circuit composed of the eight transistors may also be referred to as an LTPO pixel circuit.
  • a display panel in which the pixel circuit in the display panel is the LTPO pixel circuit can be called an LTPO display panel.
  • the driving principle of the pixel circuit described in the embodiment of the present application is introduced as follows.
  • the potential of the second reset signal provided by the second reset signal line Reset_P, the potential of the first gate drive signal provided by the first gate signal line Gate_P, and the potential of the light control signal provided by the light control signal line EM are all the first potential.
  • the potential of the second gate drive signal provided by the second gate signal line Gate_N and the potential of the first reset signal provided by the first reset signal line Reset_H are all the second potential.
  • the seventh transistor T7 and the second transistor T2 are turned on.
  • the fourth transistor T4, the fifth transistor T5, the first transistor T1, the sixth transistor T6, the second transistor T2 and the third transistor T3 are all turned off.
  • the second reset signal of the second potential provided by the second reset power line Vinit2 can be transmitted to the anode of the light-emitting unit through the turned-on seventh transistor T7
  • the third reset signal of the second potential provided by the third reset power line Vint3 can be transmitted to the second node N2 through the turned-on eighth transistor T8, so as to achieve the reset of the anode of the light-emitting unit and the second node N2.
  • the potential of the second reset signal provided by the second reset signal line Reset_P jumps to the second potential
  • the potential of the second gate drive signal provided by the second gate signal line Gate_N jumps to the first potential
  • the potential of the light-emitting control signal provided by the light-emitting control signal line EM remains at the first potential.
  • the first transistor T1, the second transistor T2 and the third transistor T3 are all turned on, and the seventh transistor T7, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 are turned off.
  • the first reset power supply signal is transmitted to N3 via the turned-on first transistor T1, and the second transistor T2 adjusts the potential of the first node N1 based on the potential of the third node N3.
  • the reset power supply signal of the second potential provided by the first reset power supply line Vinit1 can be transmitted to the first node N1 via the turned-on first transistor T1 and the second transistor T2, thereby resetting the first node N1.
  • the potential of the second reset signal provided by the second reset signal line Reset_P jumps to the first potential
  • the first reset signal provided by the first reset signal line Reset_H remains at the first potential
  • the potential of the first gate drive signal provided by the first gate signal line Gate_P jumps to the second potential
  • the second gate signal line Gate_N remains at the first potential
  • the potential of the light-emitting control signal provided by the light-emitting control signal line EM remains at the first potential.
  • the potential of the first node N1 remains at the second potential.
  • the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned on, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 are turned on.
  • the transistor T7 and the eighth transistor T8 are both turned off. In this way, the data signal provided by the data signal line Data can be transmitted to the first node N1 through the turned-on fourth transistor T4, the third transistor T3 and the second transistor T2 in sequence.
  • the potential of the second reset signal provided by the second reset signal line Reset_P maintains the first potential
  • the first reset signal provided by the first reset signal line Reset_H maintains the first potential
  • the potential of the first gate drive signal provided by the first gate signal line Gate_P jumps to the second potential
  • the second gate signal line Gate_N jumps to the second potential
  • the potential of the light-emitting control signal provided by the light-emitting control signal line EM jumps to the second potential.
  • the potential of the first node N1 remains the second potential of the data signal line Data.
  • the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 are all turned off.
  • the driving power signal provided by the driving power line VDD is transmitted to the second node N2 through the turned-on fifth transistor T5, and the third transistor T3 can transmit a driving current to the third node N3 based on the potential of the first node N1 and the potential transmitted to the second node N2.
  • the driving current can be transmitted to the anode of the light emitting unit through the turned-on sixth transistor T6, and a voltage difference is generated between the anode and cathode layers of the light emitting unit, so that the light emitting unit emits light.
  • the cathode layer is connected to the driving power line VSS.
  • the light emitting element may be an organic light emitting diode (OLED), including an anode layer, an organic light emitting layer and a cathode layer.
  • OLED organic light emitting diode
  • the flatness of the anode layer of the light emitting element will affect the color separation when the light emitting element emits light.
  • the display panel may include a pixel circuit and a portion of the pixel circuit extending away from the substrate.
  • the active layer Poly the first gate insulating layer (gate insulator, GI1), the first gate layer Gate1, the second gate insulating layer GI2, the second gate layer Gate2, the oxide layer Oxid, the third gate insulating layer GI3, the third gate layer Gate3, the first interlevel dielectric layer (inter level dielectric, ILD0), the second interlevel dielectric layer ILD, the first source and drain layer SD1, the first planarization layer (planarization layer, PLN1), the second source and drain layer SD2, the second planarization layer PLN2, the third planarization layer PLN3, the anode layer (anode, Anode) and the pixel definition layer (pixel definition layer, PDL) are stacked in sequence in the direction of the substrate 101.
  • the first metal layer may be the second source-drain electrode layer SD2, and the second metal layer may be the first source-drain electrode layer SD1.
  • Figures 3 and 4 show schematic structural diagrams of the first source-drain electrode layer and the second source-drain electrode layer in Figure 2.
  • the first metal layer may be a second source and drain layer SD2
  • the first signal line 411 and the second signal line 412 may be configured as a driving power line VDD
  • the third signal line 413 may be configured as a data signal line Data.
  • the second signal line 412 includes a first part corresponding to the first pixel circuit 1021, and a second part corresponding to the second pixel circuit 1022, and the first part and the second part are symmetrical about the first boundary of the first pixel circuit 1021 in the orthographic projection on the substrate within the first sub-pixel area, and are symmetrical about the second boundary of the second pixel circuit 1022 in the second sub-pixel area.
  • the distance between two adjacent third signal lines, the distance between the first signal line and the second signal line, or the distance between the second signal line and the third signal line is equal (as shown in FIG8 a) and is greater than or equal to 2.5 ⁇ m, and the widths of the first signal line, the second signal line, and the third signal line are equal (as shown in FIG8 b) and are greater than or equal to 2 ⁇ m.
  • the embodiment of the present application effectively increases the overlap area of the second source-drain layer SD2 and the anode layer by adding a second signal line to the second source-drain layer SD2 under the first sub-pixel and the second sub-pixel.
  • the first metal layer with the aforementioned symmetrical structure can further improve the flatness of the anode at the corresponding position and provide a symmetrical metal wiring environment. This is conducive to further improving the performance of the display panel including the flatness.
  • providing a symmetrical pattern can provide a more consistent bottom layer environment in the patterning process such as etching, and the deposition process of forming the light-emitting layer, thereby improving the etching or deposition effect.
  • the anode layer further includes a third anode 1033 corresponding to the third sub-pixel, the third anode 1033 partially overlaps the first pixel circuit 1021 and the second pixel circuit 1022, respectively, and the third anode 1033 is symmetrical along the first direction.
  • the third anode 1033 can be flattened and optimized.
  • Figure 9 is a cross-sectional view of the CC region in Figure 2 provided by an embodiment of the present application.
  • the first signal line is configured as a driving power line VDD of an integrated structure.
  • a second signal line is added to the second source-drain layer SD2 in the projection area of the first sub-pixel and the second sub-pixel to enhance the flatness of the anode of the first sub-pixel and the second sub-pixel
  • the driving power line VDD of the second source-drain layer SD2 in the projection area of the third sub-pixel is set as an integrated structure to enhance the flatness of the anode of the third sub-pixel. Therefore, by improving the second source-drain layer SD2, the flatness of the anodes of the first sub-pixel, the second sub-pixel and the third sub-pixel can be improved respectively, and the color separation caused by the uneven anode is effectively avoided.
  • FIG10 is a schematic diagram of a circuit structure provided by an embodiment of the present application.
  • the connection structure shown in FIG10 is a connection structure corresponding to the first pixel circuit 1021 and the second pixel circuit 1022 in FIG2.
  • the first reset power line Vinit1, the second reset power line Vinit2, and the third reset power line Vinit3 are configured as signal lines extending along the first direction X, and form a mesh connection with the signal lines extending along the second direction Y.
  • the data signal line Data and the driving power line VDD are longitudinal signal lines, wherein the transverse signal line mainly provides signals for multiple pixel circuits arranged in the transverse direction, and the longitudinal signal line mainly provides signals for multiple pixel circuits arranged in the longitudinal direction.
  • FIG. 11 is an active layer, a first gate layer, and a second gate layer of a display panel provided in an embodiment of the present application.
  • FIG12 is a schematic diagram of partial superposition of active layer, first gate layer, second gate layer, oxide layer and third gate layer of a display panel provided in an embodiment of the present application, that is, the superposition position of the third gate layer is further shown on the basis of FIG11
  • FIG13 is a schematic diagram of partial superposition of active layer, first gate layer, second gate layer, oxide layer, third gate layer, first source and drain electrode and second source and drain electrode of a display panel provided in an embodiment of the present application
  • FIG14 is a schematic diagram of partial superposition of active layer, first gate layer, second gate layer, oxide layer, third gate layer, first source and drain electrode layer, second source and drain electrode layer, anode layer and pixel defining layer of a display
  • the present application since the flatness of the anode is strongly affected by the metal layer closest to the anode (the second source and drain layer SD2), and the influence is second only to that of the metal layer as the distance from the edge increases, the present application further proposes a method for optimizing the routing of the first source and drain layer SD1 to further enhance the flatness of the sub-pixel anode.
  • a first auxiliary metal line is further provided on the first source-drain layer SD1, the first auxiliary metal line at least partially overlaps with the anode, and an overlapping area between the first auxiliary metal line and the projection of the third signal line on the first source-drain layer SD1 is less than 20% of the projection area of the third signal line on the first source-drain layer SD1.
  • the first auxiliary metal line 51 is disposed on the symmetric line of the two data signal lines Data, and forms a complementary structure with the two data signal lines Data, further enhancing the flatness of the anode. Moreover, the first auxiliary metal line 51 forms an evenly spaced routing structure with the routing structure in the original circuit, increasing the overlapping area of the first source and drain electrode layer SD1 and the anode layer, and providing a stable basic structure for further improving the flatness of the anode.
  • the structure of the first auxiliary metal wire 51 is complementary to that of the two data signal lines Data, and the width of the first auxiliary metal wire 51 (as shown in d in FIG. 15 ) is greater than or equal to 2 ⁇ m. Furthermore, the first auxiliary metal wire 51 and the wiring structure in the original circuit form an evenly spaced wiring structure, and the distance between the first auxiliary metal wire 51 and the structure in the original circuit (as shown in c in FIG. 15 ) is greater than or equal to 1.5 ⁇ m.
  • the first auxiliary metal line is arranged at the projected position of the first boundary of the first pixel circuit and is symmetrical about the first boundary of the first pixel circuit, or the first auxiliary metal line is arranged on the second boundary of the second pixel circuit and is symmetrical about the second boundary of the second pixel circuit.
  • FIG. 16 is a schematic diagram of a partial structure of a first source and drain layer provided in an embodiment of the present application
  • 17 is a schematic diagram of the partial superposition of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer and a first source and drain of another display panel provided in an embodiment of the present application.
  • the embodiment of the present application increases the overlapping area between the first source drain SD1 and the anode by adding a first auxiliary metal line to the first source drain layer SD1 in the projection area of the first sub-pixel and the second sub-pixel, so as to enhance the flatness of the anodes of the first sub-pixel and the second sub-pixel, and effectively avoids color separation caused by uneven anodes.
  • the first source-drain electrode layer SD1 can also optimize the planarity of the third anode.
  • the first source-drain layer SD1 includes a second auxiliary metal line 53 and a third auxiliary metal line 54 , which at least partially overlap with the third anode and are symmetrical along the second direction.
  • the first source and drain layer SD1 adds a second auxiliary metal wire 53 and a third auxiliary metal wire 54 in the projection area of the third anode, forming a symmetrical structure with the metal structure 55 in the original circuit, thereby achieving uniform support for the third anode, thereby effectively improving the flatness of the third anode.
  • the third gate layer can be used to compensate for it.
  • a projection of the third gate layer in the projection region of the third anode and a projection of the second metal layer in the projection region of the third anode are symmetrical along the first direction.
  • a projection 61 of the third gate layer in the projection region of the third anode is symmetrical with a projection 55 of the second metal layer in the projection region of the third anode in the first direction.
  • the via design of the interlayer dielectric layer ILD and the flat layers (including the first flat layer PLN1, the second flat layer PLN2 and the third flat layer PLN3) will also affect the flatness of the anode.
  • the pixel defining layer may have a first opening corresponding to the first anode (first sub-pixel area), a second opening corresponding to the second anode (second sub-pixel area), and a third opening corresponding to the third anode (third sub-pixel area).
  • the second sub-pixel overlaps with the first flat layer PLN1 by -0.3 ⁇ m, and the boundary of the third flat layer PLN3 to the first opening is 0.5 ⁇ m.
  • the distance d1 to the boundary is 13.6 ⁇ m
  • the distance d2 to the second opening boundary is 25.115 ⁇ m
  • the distance d3 to the third opening boundary is 11.055 ⁇ m.
  • the 2.5 holes and 4.5 holes mentioned above should be understood in a broad sense, that is, a portion of a via hole does not fall within a specific projection area, and the cross-sectional area of the via hole that does not fall within the projection area may be 30%-70%, for example, 40%-60%, of the entire cross-sectional area of the via hole.
  • the aperture ratio of the pixel defining layer is limited to 15.93%, which means that the projection areas of the first opening and the second opening include 3 via holes, and the projection area of the third opening includes 1.5 via holes.
  • the projection area of the first opening includes 3 vias
  • the projection area of the second opening includes 3 vias
  • the projection area of the third opening includes 1.5 vias.
  • the boundary of the second opening is +1.6 ⁇ m away from the boundary of the vias of the first flat layer
  • the distance d1 from the boundary of the third flat layer PLN3 to the boundary of the first opening is 14.25 ⁇ m
  • the distance d2 to the boundary of the second opening is 26.2 ⁇ m
  • the distance d3 to the boundary of the third opening is 12.625 ⁇ m.
  • the above-mentioned vias (10a-10c as shown in the figure) can be through vias formed in structures including but not limited to interlayer dielectric layers (such as the aforementioned first interlayer dielectric layer ILD0, second interlayer dielectric layer ILD) and the first flat layer PLN1, the second flat layer PLN2, and the third flat layer PLN3 in order to achieve electrical connection between various metal traces and/or between electrodes and active layers.
  • interlayer dielectric layers such as the aforementioned first interlayer dielectric layer ILD0, second interlayer dielectric layer ILD
  • the first flat layer PLN1 the first flat layer PLN1
  • the second flat layer PLN2 the third flat layer PLN3
  • the number of vias corresponding to the pixel opening projection area is further reduced, thereby achieving the purpose of improving the flatness of the anode.
  • the edge of the second sub-pixel opening is effectively prevented from overlapping with the vias on the first flat layer, further improving the flatness of the pixel anode edge.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of “multiple” is two or more, unless otherwise clearly and specifically defined.
  • the first feature “above” or “below” the second feature can include the first and second features being in direct contact, or it can include the first and second features not being in direct contact but being in contact through another feature between them.
  • the first feature “above”, “above” and “above” the second feature include the first feature being directly above and obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.
  • the first feature “below”, “below” and “below” the second feature include the first feature being directly above and obliquely above the second feature, or simply means that the first feature is lower in level than the second feature.

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Abstract

本申请公开了一种显示面板及显示装置。所述显示面板包括位于衬底基板上层叠设置的第一金属层和阳极层，所述第一金属层包括等间距设置的第一信号线、第二信号线和第三信号线；所述第二信号线在衬底基板上的正投影与所述阳极层至少部分交叠。

Description

显示面板及显示装置
相关申请的交叉引用
本申请主张在2023年06月14日在中国提交的中国专利申请号No.202310706609.X的优先权，其全部内容通过引用包含于此。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
有机发光二极管(organic light-emitting diode，OLED)显示面板由于具有自发光，驱动电压低，以及响应速度快等优点而得到了广泛的应用。OLED显示面板一般包括：多个像素单元，每个像素单元包括发光单元以及与该发光单元连接的像素电路，发光单元包括阳极、位于阳极上的发光层和位于发光层上的阴极。因此发光单元的阳极的平坦程度影响着一个发光单元的色分离情况。
然而由于阳极下方的像素电路具有较为复杂的电子元件(如晶体管、存储电容等)以及走线结构，导致阳极的平坦程度并不十分理想。因此，目前的显示面板及显示装置仍有待改进。
发明内容
本申请提供一种显示面板及其制备方法。
本申请第一方面，提供了一种显示面板，所述显示面板包括位于衬底基板上层叠设置的第一金属层和阳极层，所述第一金属层包括等间距设置的第一信号线、第二信号线和第三信号线；所述第二信号线在衬底基板上的正投影与所述阳极层至少部分交叠。
在一些实施例中，所述显示面板具有沿第一方向交替设置的第一像素电路和第二像素电路，所述第一像素电路和所述第二像素电路沿第二方向对称设置；
所述阳极层包括与第一子像素对应的第一阳极和与第二子像素对应 的第二阳极；所述第一阳极关于所述第一像素电路的第一边界对称，所述第二阳极关于所述第二像素电路的第二边界对称，所述第一像素电路的第一边界和所述第二像素电路的第二边界平行；
所述第二信号线包括与所述第一像素电路对应的第一部分，以及与所述第二像素电路对应的第二部分，所述第一部分和所述第二部分在所述衬底基板上的正投影中，位于所述第一子像素区域内的部分关于所述第一像素电路的第一边界对称，位于所述第二子像素区域内的部分关于所述第二像素电路的第二边界对称。
在一些实施例中，所述第一信号线和所述第二信号线之间的距离大于或等于2.5μm，或者所述第二信号线和所述第三信号线之间的距离大于或等于2.5μm，所述第一信号线、所述第二信号线和所述第三信号线的宽度分别独立第大于或等于2μm。
在一些实施例中，显示面板还包括第二金属层，所述第二金属层具有第一辅助金属线，所述第一辅助金属线在所述衬底基板上的正投影与所述阳极在所述衬底基板上的正投影至少部分交叠，且所述第一辅助金属线与所述第三信号线在所述衬底基板上的投影的交叠面积，小于所述第三信号线在所述衬底基板上的投影的20％。
在一些实施例中，所述第一辅助金属线设置于所述第一像素电路的第一边界的投影位置上，且所述第一辅助金属线关于所述第一像素电路的第一边界对称，或者，所述第一辅助金属线设置于所述第二像素电路的第二边界上，且所述第一辅助金属线关于所述第二像素电路的第二边界对称。
在一些实施例中，所述第一辅助金属线的宽度大于或等于2μm。
在一些实施例中，所述阳极层还包括与第三子像素对应的第三阳极，所述第三阳极在所述衬底基板上的正投影分别与所述第一像素电路和所述第二像素电路部分交叠，所述第三阳极具有沿所述第一方向延伸的对称轴；
所述第一信号线在所述第三阳极区域内的投影为一体结构。
在一些实施例中，所述衬底基板还包括第一复位电源线、第二复位电源线和第三复位电源线，所述第一复位电源线、所述第二复位电源线和所述第三复位电源线网状连接。
在一些实施例中，所述第二金属层还包括第二辅助金属线和第三辅助金属线，所述第二辅助金属线和所述第三辅助金属线在所述衬底基板上的正投影具有至少部分与所述第三阳极在所述基板上的正投影交叠；所述第二辅助金属线和所述第三辅助金属线沿所述第二方向对称分布。
在一些实施例中，显示面板进一步包括依次层叠与所述衬底基板上的第一至第三栅极层，所述第一至第三栅极层均位于所述衬底基板和所述第一金属层之间，所述第三栅极层在所述第三阳极的投影区域内的投影与所述第二金属层在所述第三阳极的投影区域内的投影沿所述第一方向对称。
在一些实施例中，所述显示面板还包括像素界定层，所述像素界定层具有第一至第三开口，所述第一开口和所述第一阳极对应，所述第二开口和所述第二阳极对应，所述第三开口和所诉第三阳极对应，
所述第一开口和所述第二开口在所述衬底基板的投影区域内包括3个过孔，在所述第三开口在所述衬底基板的投影区域内包括1.5个过孔。
在一些实施例中，所述第一信号线为所述显示面板的驱动电源线，所述第二信号线为辅助驱动电源线，所述第三信号线为所述显示面板的数据信号线。
在一些实施例中，所述第一金属层为第二源漏极层，所述第二金属层为第一源漏极层。
在一些实施例中，所述像素电路包括：
第一晶体管，所述第一晶体管的栅极与第一复位信号线连接，所述第一晶体管的第一极与第一复位电源线连接，所述第一晶体管的第二极与第三节点连接；
第二晶体管，所述第二晶体管的栅极与所述显示面板包括的第一栅极信号线连接，所述第二晶体管的第一极与第一节点连接，所述第二晶体管的第二极与所述第三节点连接；
第三晶体管，所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的第一极与第二节点连接，所述第三晶体管的第二极与所述第三节点连接；
第四晶体管，所述第四晶体管的栅极与所述显示面板包括的第二栅极信号线连接，所述第四晶体管的第一极与所述显示面板包括的数据信号线连接， 所述第四晶体管的第二极与所述第二节点连接；
第五晶体管，所述第五晶体管的栅极与发光控制信号线连接，所述第五晶体管的第一极与所述显示面板包括的驱动电源线连接，第五晶体管的第二极与所述第二节点；
第六晶体管，所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一极与所述第三节点连接，所述第六晶体管的第二极与发光单元连接；
第七晶体管，所述第七晶体管的栅极与所述显示面板包括的第二栅极信号线连接，所述第七晶体管的第一极与第二复位电源线连接，所述第七晶体管的第二极与所述发光单元连接；
第八晶体管，所述第八晶体管的栅极与所述第二复位信号线连接，所述第八晶体管的第一极和所述显示面板包括的第三复位电源线连接，所述第八晶体管的第二极与所述第二节点连接；
存储电容，所述存储电容的一端与所述驱动电源线连接，所述存储电容的另一端与所述第一节点连接。
本申请第二方面，提供了一种显示装置，显示装置包括所述的显示面板。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1是本申请实施例提供的一种显示面板的局部结构示意图；
图2是本申请实施例提供的另一种显示面板的局部结构示意图；
图3是图2中对应的第一源漏极层的局部结构示意图；
图4是图2中对应的第二源漏极层的局部结构示意图；
图5是本申请实施例提供的像素电路的等效电路图；
图6是图5对应的时序图；
图7是本申请实施例提供的一种AA(或BB)区域的截面图；
图8是本申请实施例提供的另一种AA(或BB)区域的截面图；
图9是本申请实施例提供的一种电路结构示意图；
图10是本申请实施例提供的一种电路结构示意图；
图11是本申请实施例提供的一种显示面板的有源层、第一栅极层、第二栅极层和氧化物层的局部叠加示意图；
图12是本申请实施例提供的一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层和第三栅极层的局部叠加示意图；
图13是本申请实施例提供的一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层、第三栅极层、第一源漏极层和第二源漏极层的局部叠加示意图；
图14是本申请实施例提供的一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层、第三栅极层、第一源漏极层、第二源漏极层、阳极层和像素界定层的局部叠加示意图；
图15是本申请实施例提供的一种CC区域的截面图；
图16是本申请实施例提供的一种第一源漏极层的局部结构示意图；
图17是本申请实施例提供的另一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层、第三栅极层和第一源漏极层的局部叠加示意图；
图18是本申请实施例提供的另一种显示面板的第一源漏极层的局部示意图；
图19是本申请实施例提供的另一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层、第三栅极层、第一源漏极层和第二源漏极层的局部叠加示意图；
图20是本申请实施例提供的另一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层、第三栅极层、第一源漏极层、第二源漏极层、阳极层和像素界定层的局部叠加示意图；
图21是本申请实施例提供的另一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层、第三栅极层、第一源漏极层的局部叠加示意图；
图22和图23是相关技术中一种显示面板的过孔与像素界定层开口的局部叠加示意图；
图24和图25是本申请实施例提供的一种显示面板的过孔与像素界定层开口的局部叠加示意图。
具体实施方式
在下文中，仅简单地描述了某些示例性实施例。正如本领域技术人员可 认识到的那样，在不脱离本申请的精神或范围的情况下，可通过各种不同方式修改所描述的实施例，不同的实施例在不冲突的情况下可以任意结合。因此，附图和描述被认为本质上是示例性的而非限制性的。
本申请所有实施例中采用的晶体管均可以为场效应管或其他特性相同的器件，根据在电路中的作用本申请的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，将其中源极称为第一极，漏极称为第二极，或者，将其中漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本申请实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本申请各个实施例中的多个信号都对应有有效电位和无效电位，有效电位和无效电位仅代表该信号的电位有两个状态量，不代表全文中有效电位或无效电位具有特定的数值。
图1是本申请实施例提供的一种显示面板的局部结构示意图。该显示面板10可以包括衬底基板101和多个像素单元102。
多个像素单元102的至少一个包括第一子像素、第二子像素和第三子像素，第一子像素、第二子像素和第三子像素均包括像素电路和发光元件。第一子像素、第二子像素和第三子像素中的像素电路分别与栅极信号线、数据信号线和发光信号线连接，像素电路被配置为在栅极信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光元件输出相应的电流。第一子像素、第二子像素和第三子像素的发光元件分别与所在子像素的像素电路连接，发光元件被配置为响应所在子像素的像素电路输出的电流发出相应亮度的光。
在一种可行的实施例中，图2是本申请实施例提供的另一种显示面板的局部结构示意图。如图2所示，多个像素电路沿第一方向X排布少一个像素电路包括：沿第二方向Y排布的多个第一像素电路1021和沿第二方向y排布的多个第二像素电路1022。其中，第一方向X和第二方向Y垂直，例如第一方向X为像素行方向，第二方向Y为像素列方向。其中，多个第一像素电路 1021和第二像素电路1022沿第一方向交替设置，且多个第一像素电路1021和多个第二像素电路1022中每个像素电路包括沿第二方向延伸的第一边界和第二边界。
在一种可行的实施例中，像素单元中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素。在一些实施例方式中，像素单元中子像素的形状可以是矩形、菱形、五边形或六边形。像素单元可以采用水平并列、竖直并列或品字方式排列。图2示出了成品字排列的第一子像素、第二子像素和第三子像素的位置。其中。第一子像素1031为红色子像素、第二子像素1032为蓝色子像素，第三子像素1033为绿色子像素。
应当理解的是，第一像素电路1021和第二像素电路1022不必然与第一子像素和第二子像素存在对应关系，即，第一像素电路1021与跨接在其上的第一子像素1031不一定存在对应关系，换言之，第一像素电路1021可以是用于控制第一子像素1031对应的像素电路，也可是用于控制第三子像素1033对应的像素电路，或者其他像素的控制电路，具体根据像素电路的布图设计决定，本申请不做具体限定。
在一种可行的实施例中，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C等结构。图5是本申请实施例提供的像素电路的等效电路图。如图5所示，像素电路可以包括第一晶体管T1，第二晶体管T2，第三晶体管T3，第四晶体管T4，第五晶体管T5，第六晶体管T6，第七晶体管T7，第八晶体管T8以及存储电容Cst。
其中，第七晶体管T7的栅极可以与第一复位信号线Reset_H连接，第七晶体管T7的第一极可以与第二复位电源线Vinit2连接，第七晶体管T7的第二极可以与发光单元连接。该第七晶体管T7还可以称为复位晶体管。
第四晶体管T4的栅极可以与第一栅极信号线Gate_P连接，第四晶体管T4的第一极可以与数据信号线Data连接，第四晶体管T4的第二极可以与第二节点N2连接。也即是，第四晶体管T4可以为像素电路中的数据写入晶体管。
第五晶体管T5的栅极可以与发光控制信号线EM连接，第五晶体管T5的第一极可以与驱动电源线VDD连接，第五晶体管T5的第二极可以与第二节点N2连接。由于该第五晶体管T5的栅极与发光控制信号EM连接，因此该第五 晶体管T5还可以称为发光控制晶体管。
第一晶体管T1的栅极可以与第二复位信号线Reset_P连接，第一晶体管T1的第一极可以与第一复位电源线Vinit1连接，第一晶体管T1的第二极可以与第三节点N3连接。该第一晶体管T1还可以称为复位晶体管。
第六晶体管T6的栅极可以与发光控制信号线EM连接，第六晶体管T6的第一极可以与第三节点N3连接，第五晶体管的第二极可以与发光单元连接。由于该第六晶体管T6的栅极与发光控制信号线EM连接，因此该第六晶体管T6还可以称为发光控制晶体管。
第二晶体管T2的栅极可以与第二栅极信号线Gate_N连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极可以与第一节点N1连接。该第二晶体管T2还可以称为补偿晶体管。
第三晶体管T3的栅极可以与第一节点N1连接，第三晶体管T3的第一极可以与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。该第三晶体管T3还可以称为驱动晶体管。
第八晶体管T8的栅极可以与第一复位信号线Reset_H连接，即第八晶体管T8的栅极和第七晶体管T7的栅极共用第一复位信号线Reset_H，第八晶体管T8的第一极可以与第三复位电源线Vinit3连接，第八晶体管T8的第二极可以与第二节点N2连接。该第八晶体管T8还可以称为复位晶体管。
存储电容Cst的一端可以与驱动电源线VDD连接，存储电容Cst的另一端可以与第一节点N1连接。可选的，存储电容Cst可以包括两个电容极板Cst1和Cst2，在本申请实施例中，电容极板Cst1可以称为存储电容Cst的一端，第一端或第一存储电容电极，电容极板Cst2可以称为存储电容Cst的另一端、第二端或第二存储电容电极。
结合上述实施例可知，在本申请实施例中，第二晶体管T2为N型晶体管，第一晶体管T1、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7均为P型晶体管。
可选的，本申请实施例记载的各个N型晶体管可以均为氧化物晶体管，各个P型晶体管可以均为低温多晶硅(LTPS)晶体管。氧化物材料可以包括铟镓锌氧化物(indium gallium zinc oxide，IGZO)，即氧化物晶体管可以为IGZO晶体管。由该8个晶体管构成的像素电路也可以称为LTPO像素电路。 显示面板中的像素电路为该LTPO像素电路的显示面板可以称为LTPO显示面板。
以图5所示的像素电路，第一电位相对于第二电位为高电位为例，对本申请实施例记载的像素电路的驱动原理进行如下介绍。时序如图6所示。
在初始化阶段t1，第二复位信号线Reset_P提供的第二复位信号的电位、第一栅极信号线Gate_P提供的第一栅极驱动信号的电位以及发光控制信号线EM提供的发光控制信号的电位均为第一电位。第二栅极信号线Gate_N提供的第二栅极驱动信号的电位和第一复位信号线Reset_H提供的第一复位信号的电位均为第二电位。相应的，第七晶体管T7和第二晶体管T2开启。第四晶体管T4、第五晶体管T5、第一晶体管T1、第六晶体管T6、第二晶体管T2和第三晶体管T3均关断。如此，第二复位电源线Vinit2提供的第二电位的第二复位信号可以经过开启的第七晶体管T7传输至发光单元的阳极，第三复位电源线Vint3提供的第二电位的第三复位信号可以经开启的第八晶体管T8传输至第二节点N2，实现对发光单元的阳极和第二节点N2的复位。
在补偿阶段t2，第二复位信号线Reset_P提供的第二复位信号的电位跳变为第二电位，第二栅极信号线Gate_N提供的第二栅极驱动信号的电位跳变为第一电位，且发光控制信号线EM提供的发光控制信号的电位保持为第一电位。相应的，第一晶体管T1、第二晶体管T2和第三晶体管T3均开启，第七晶体管T7、第四晶体管T4、第五晶体管T5、第六晶体管T6和第八晶体管T8关断。如此，第一复位电源信号经开启的第一晶体管T1传输至N3，第二晶体管T2基于第三节点N3的电位调节第一节点N1的电位。此外，第一复位电源线Vinit1提供的第二电位的复位电源信号可以经开启的第一晶体管T1和第二晶体管T2传输至第一节点N1，实现对第一节点N1的复位。
在写入阶段t3，第二复位信号线Reset_P提供的第二复位信号的电位跳变为第一电位，第一复位信号线Reset_H提供的第一复位信号保持为第一电位，第一栅极信号线Gate_P提供的第一栅极驱动信号的电位跳变为第二电位，第二栅极信号线Gate_N保持为第一电位，发光控制信号线EM提供的发光控制信号的电位保持为第一电位。在存储电容Cst的自举作用下，第一节点N1的电位保持为第二电位。相应的，第二晶体管T2、第三晶体管T3和第四晶体管T4开启，第一晶体管T1、第五晶体管T5、第六晶体管T6、第七晶 体管T7和第八晶体管T8均关断。如此，数据信号线Data提供的数据信号线能够依次经开启的第四晶体管T4，第三晶体管T3和第二晶体管T2传输至第一节点N1。
在发光阶段t4，第二复位信号线Reset_P提供的第二复位信号的电位保持第一电位，第一复位信号线Reset_H提供的第一复位信号保持为第一电位，第一栅极信号线Gate_P提供的第一栅极驱动信号的电位跳变为第二电位，第二栅极信号线Gate_N跳变为第二电位，发光控制信号线EM提供的发光控制信号的电位跳变为第二电位。在存储电容Cst的自举作用下，第一节点N1的电位保持为数据信号线Data的第二电位。相应的，第三晶体管T3、第五晶体管T5以及第六晶体管T6开启，第一晶体管T1、第二晶体管T2、第四晶体管T4、第七晶体管T7以及第八晶体管T8均关断。如此，驱动电源线VDD提供的驱动电源信号经开启的第五晶体管T5传输至第二节点N2，第三晶体管T3能够基于第一节点N1的电位和传输至第二节点N2的电位，向第三节点N3传输驱动电流。然后，该驱动电流可以再经开启的第六晶体管T6传输至发光单元的阳极，发光单元的阳极与阴极层间产生压差，发光单元发光。其中，阴极层与驱动电源线VSS连接。
在一个可行的实施例中，发光元件可以是有机致电发光二极管(OLED)，包括设置的阳极层、有机发光层和阴极层。如前所述，发光元件阳极层的平坦程度会影响发光元件发光时色分离的情况。
图7是图2在AA区域的局部结构截面图。如图7所示，该显示面板包括第一金属层和阳极层(图中未示出)，第一金属层具有等间距设置的第一信号线411、第二信号线412和第三信号线413，其中第二信号线412在衬底基板上的正投影与阳极层至少部分交叠。
由此，发光元件的阳极层在第一信号线、第二信号线和第三信号线的承托作用下，能够呈现更好的平坦效果。
此处需要特别说明的是，在本申请中，第一至第三信号线、金属线等结构和其他膜层，如阳极层“交叠”或“部分交叠”，特指二者在衬底基板上的正投影之间具有交叠或部分交叠的位置关系，而非二者之间具有直接接触的层叠关系。
在一种可行的实施例中，显示面板可以包括构成像素电路且沿远离衬底 基板101的方向依次层叠的有源层Poly，第一栅极绝缘层(gate insulator，GI1)，第一栅极层Gate1，第二栅极绝缘层GI2，第二栅极层Gate2，氧化物层Oxid，第三栅极绝缘层GI3，第三栅极层Gate3，第一层间介电层(inter level dielectric，ILD0)，第二层间介电层ILD，第一源漏极层SD1，第一平坦层(planarization layer，PLN1)、第二源漏极层SD2、第二平坦层PLN2、第三平坦层PLN3、阳极层(anode layer，Anode)和像素界定层(pixel definition layer，PDL)。
示例性的，第一金属层可以为第二源漏极层SD2，第二金属层可以为第一源漏极层SD1。图3以及图4示出了图2中第一源漏极层和第二源漏极层的结构示意图。
示例性的，如图8所示，第一金属层可以为第二源漏极层SD2，第一信号线411和第二信号线412可以配置为驱动电源线VDD，第三信号线413可以配置为数据信号线Data。
需要说明的是，图2中还示出了第一像素电路1021和第二像素电路1022沿第一方向交替设置，第一像素电路1021和第二像素电路1022沿第二方向对称，阳极层包括与第一子像素对应的第一阳极1031和第二子像素对应的第二阳极1032，第一阳极1031关于第一像素电路1021的第一边界对称，第二阳极1032关于第二像素电路1022的第二边界对称，第一像素电路1021的第一边界和第二像素电路1022的第二边界平行。
进一步地，第二信号线412包括与第一像素电路1021对应的第一部分，以及与第二像素电路1022对应的第二部分，第一部分和第二部分在衬底基板上的正投影中位于第一子像素区域内的部分关于第一像素电路1021的第一边界对称，在第二子像素的区域内的部分关于第二像素电路1022的第二边界对称。
在一个可行的实施例中，如图8所示，相邻的两个第三信号线之间的距离、第一信号线和第二信号线之间的距离或者第二信号线和第三信号线之间的距离相等(如图8所示a)且大于或等于2.5μm，第一信号线、第二信号线和第三信号线的宽度相等(如图8所示b)大于或等于2μm。
由此，本申请实施例通过在第一子像素和第二子像素下的第二源漏极层SD2增加设置第二信号线，有效增加了第二源漏极层SD2与阳极层的交叠面 积，提高了第一子像素和第二子像素对应阳极的平坦程度。并且具有前述的对称结构的第一金属层可以进一步提高相应位置处阳极的平坦程度，并提供对称的金属走线环境。从而有利于进一步提升包括平坦程度在内的该显示面板的性能，例如提供对称的图形可以在刻蚀等构图工艺制程，以及形成发光层等结构的沉积工艺中提供更加一致的底层环境，从而提升刻蚀或是沉积的效果。
在一个可行的实施例中，阳极层还包括和第三子像素对应的第三阳极1033，第三阳极1033分别与第一像素电路1021和第二像素电路1022部分交叠，第三阳极1033沿第一方向对称。为了进一步提升该显示面板的性能，可在对第一子像素1031和第二子像素1032进行基于第二源漏极层SD2的平坦处理后，对第三阳极1033进行平坦优化。
可选的，第一信号线在第三阳极的投影为一体结构。示例性的，图9是本申请实施例提供的一种图2中CC区域的截面图。如图9所示，第一信号线被配置为一体结构的驱动电源线VDD。
由此，本申请实施例通过对在第一子像素和第二子像素的投影区域的第二源漏极层SD2增加第二信号线，以增强第一子像素和第二子像素阳极的平坦程度，并在第三子像素的投影区域的第二源漏极层SD2的驱动电源线VDD设置为一体结构，以增强第三子像素阳极的平坦程度。由此，通过对第二源漏极层SD2的改进，能够分别实现第一子像素、第二子像素和第三子像素阳极的平坦程度改进，有效避免了因阳极不平坦产生色分离的情况。
在一个可行的实施例中，图10是本申请实施例提供的一种电路结构示意图。其中，图10所示的连接结构为图2中第一像素电路1021和第二像素电路1022对应的连接结构。如图10所示，在第一像素电路1021和第二像素电路1022的下部，第一复位电源线Vinit1、第二复位电源线Vinit2和第三复位电源线Vinit3被配置为沿第一方向X延伸的信号线，与沿第二方向Y延伸的信号线形成网状连接。
需要说明的是，数据信号线Data和驱动电源线VDD为纵向信号线，其中，横向信号线主要为横向方向设置的多个像素电路提供信号，纵向信号线主要为纵向方向设置的多个像素电路提供信号。
图11是本申请实施例提供的一种显示面板的有源层、第一栅极层、第二 栅极层和氧化物层的局部叠加示意图，其中Vinit1、Vinit2和Vinit3均由第一栅极层Gate1金属形成；图12是本申请实施例提供的一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层和第三栅极层的局部叠加示意图，即在图11的基础上进一步示出了第三栅极层的叠加位置；图13是本申请实施例提供的一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层、第三栅极层、第一源漏极和第二源漏极的局部叠加示意图；图14是本申请实施例提供的显示面板的有源层、第一栅极层、第二栅极层、氧化物层、第三栅极层、第一源漏极层、第二源漏极层、阳极层和像素界定层的局部叠加示意图。上述金属层的层叠顺序如前所述，在此不再赘述。
在本申请一个可行的实施例中，由于阳极平坦度受与阳极最近的金属层(第二源漏极层SD2)的影响较强，随着距离边缘影响次之，因此，本申请还进一步提出对第一源漏极层SD1走线的优化方法，以进一步增强子像素阳极的平坦程度。
可选的，第一源漏极层SD1上还设置有第一辅助金属线，第一辅助金属线与阳极至少部分交叠，且第一辅助金属线与第三信号线在第一源漏极层SD1的投影的交叠面积小于第三信号线在第一源漏极层SD1上的投影面积的20％。
示例性的，如图15所示，第一辅助金属线51设置在两个数据信号线Data的对称线上，与两个数据信号线Data形成互补结构，进一步增强阳极的平坦程度。而且，第一辅助金属线51与原电路中的走线结构形成等间距均匀走线结构，增加了第一源漏极层SD1与阳极层的交叠面积，为进一步提高阳极平坦提供稳定的基础结构。
优选的，第一辅助金属线51与两个数据信号线Data的结构互补，第一辅助金属线51的宽度(如图15所示d)大于或等于2μm，进一步地，第一辅助金属线51与原电路中的走线结构形成等间距均匀走线结构，第一辅助金属线51与原电路中的结构之间的距离(如图15所示c)大于或等于1.5μm。
应当理解的是，由于第一子像素和第二子像素跨接在第一像素电路和第二像素电路上，因此，第一辅助金属线设置于第一像素电路的第一边界的投影位置上，且关于第一像素电路的第一边界对称，或者，第一辅助金属线设置于第二像素电路的第二边界上，且关于第二像素电路的第二边界对称。
图16是本申请实施例提供的一种第一源漏极层的局部结构示意图，图 17是本申请实施例提供的另一种显示面板的有源层、第一栅极层、第二栅极层、氧化物层、第三栅极层和第一源漏极的局部叠加示意图。
由此，本申请实施例通过在第一子像素和第二子像素投影区域的第一源漏极层SD1增加第一辅助金属线，增大了第一源漏极SD1与阳极之间的交叠面积，以增强第一子像素和第二子像素阳极的平坦程度，有效避免了因阳极不平坦产生色分离的情况。
在一个可行的实施例中，与第二源漏极层SD2一致的，第一源漏极层SD1层还可对第三阳极进行平坦优化。
可选的，参考图17-20，第一源漏极层SD1包括第二辅助金属线53和第三辅助金属线54，第二辅助金属线53和第三辅助金属线54至少部分的与第三阳极交叠，第二辅助金属线53和第三辅助金属线54沿第二方向对称。
示例性的，如图18所示，第一源漏极层SD1在第三阳极的投影区域增加了第二辅助金属线53和第三辅助金属线54，与原电路中的金属结构55形成对称结构，实现对第三阳极的均匀支撑，从而有效提高第三阳极的平坦程度。
进一步地，由于随着金属层距离阳极的越远影响越小，在第一源漏极SD1在第一方向的对称性不佳的情况下，还可以利用第三栅极层进行弥补。
可选的，第三栅极层在第三阳极的投影区域内的投影与第二金属层在第三阳极的投影区域内的投影沿第一方向对称。
示例性的，如图21所示，第三栅极层在第三阳极的投影区域内的投影61与第二金属层在第三阳极的投影区域内的投影55第一方向对称。
在一个可行的实施例中，除通过走线优化阳极平坦程度外，层间介电层ILD的过孔和平坦层(包括第一平坦层PLN1、第二平坦层PLN2和第三平坦层PLN3)的过孔设计也会影响阳极的平坦程度。
相关技术中，如图22和图23所示，当像素界定层的开口在平行于显示面板上的截面宽度为22μm时，开口率为20.56％。像素界定层(如图中所示出的PDL)可具有和第一阳极(第一子像素区域)对应的第一开口，和第二阳极(第二子像素区域)对应的第二开口，以及和第三阳极(第三子像素区域)对应的第三开口。其中，第一开口的投影区域内有3个孔，第二开口的投影区域内有2.5个孔，第三开口的投影区域内有4.5个孔，第二子像素与第一平坦层PLN1有-0.3μm的交叠，其中第三平坦层PLN3边界到第一开口 边界的距离d1为13.6μm，到第二开口边界的距离d2为25.115μm，到第三开口边界的距离d3为11.055μm。
本领域技术人员能够理解的是，前文所述的2.5个孔、4.5个孔应做广义理解。即某一过孔的部分区域未落在特定的投影区域内，未落在投影区域内的过孔的横截面面积可以为该过孔整体横截面面积的30％-70％，例如为40％-60％。
在本申请实施例中，将像素界定层的开口率限制为15.93％，可以是使第一开口和第二开口的投影区域包括3个过孔，第三开口的投影区域包括1.5个过孔。
示例性的，如图24和图25所示，经过限制的像素界定层，第一开口的投影区域包括3个过孔，第二开口的投影区域包括3个过孔，第三开口的投影区域包括1.5个过孔。第二开口的边界与第一平坦层的过孔边界有+1.6μm的间距，第三平坦层PLN3边界到第一开口边界的距离d1为14.25μm，到第二开口边界的距离d2为26.2μm，到第三开口边界的距离d3为12.625μm。
此处需要特别说明的是，上述过孔(如图中所示出的10a-10c)可以为为了实现各金属走线之间和/或电极与有源层等结构的电连接关系，而在包括但不限于层间介电层(如前述的第一层间介电层ILD0，第二层间介电层ILD)以及第一平坦层PLN1、第二平坦层PLN2、第三平坦层PLN3中形成的贯穿性过孔。
由此，通过限制像素限定层的开口率，进一步减少了像素开口投影区域对应的过孔数量，从而实现提高阳极平坦的目的。同时，有效避免了第二子像素开口的边缘与第一平坦层上的过孔交叠，进一步提高了像素阳极边缘的平坦程度。
在本说明书的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“长度”、“宽度”、“左”、“右”、“竖直”、“水平”、“顶”、“底”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所 述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接，还可以是通信；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度小于第二特征。
上文的申请提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请，上文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到其各种变化或替换，这些都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (15)

  1. 一种显示面板，包括位于衬底基板上层叠设置的第一金属层和阳极层，
    所述第一金属层包括等间距设置的第一信号线、第二信号线和第三信号线；
    所述第二信号线在衬底基板上的正投影与所述阳极层至少部分交叠。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板具有沿第一方向交替设置的第一像素电路和第二像素电路，所述第一像素电路和所述第二像素电路沿第二方向对称设置；
    所述阳极层包括与第一子像素对应的第一阳极和与第二子像素对应的第二阳极；所述第一阳极关于所述第一像素电路的第一边界对称，所述第二阳极关于所述第二像素电路的第二边界对称，所述第一像素电路的第一边界和所述第二像素电路的第二边界平行；
    所述第二信号线包括与所述第一像素电路对应的第一部分，以及与所述第二像素电路对应的第二部分，所述第一部分和所述第二部分在所述衬底基板上的正投影中，位于所述第一子像素区域内的部分关于所述第一像素电路的第一边界对称，位于所述第二子像素区域内的部分关于所述第二像素电路的第二边界对称。
  3. 根据权利要求2所述的显示面板，其中，所述第一信号线和所述第二信号线之间的距离大于或等于2.5μm，
    或者所述第二信号线和所述第三信号线之间的距离大于或等于2.5μm，所述第一信号线、所述第二信号线和所述第三信号线的宽度分别独立第大于或等于2μm。
  4. 根据权利要求2所述的显示面板，其中，还包括第二金属层，所述第二金属层具有第一辅助金属线，所述第一辅助金属线在所述衬底基板上的正投影与所述阳极在所述衬底基板上的正投影至少部分交叠，且所述第一辅助金属线与所述第三信号线在所述衬底基板上的投影的交叠面积，小于所述第三信号线在所述衬底基板上的投影的20％。
  5. 根据权利要求4所述的显示面板，其中，所述第一辅助金属线设 置于所述第一像素电路的第一边界的投影位置上，且所述第一辅助金属线关于所述第一像素电路的第一边界对称，或者，
    所述第一辅助金属线设置于所述第二像素电路的第二边界上，且所述第一辅助金属线关于所述第二像素电路的第二边界对称。
  6. 根据权利要求5所述的显示面板，其中，所述第一辅助金属线的宽度大于或等于2μm。
  7. 根据权利要求2所述的显示面板，其中，所述阳极层还包括与第三子像素对应的第三阳极，所述第三阳极在所述衬底基板上的正投影分别与所述第一像素电路和所述第二像素电路部分交叠，所述第三阳极具有沿所述第一方向延伸的对称轴；
    所述第一信号线在所述第三阳极区域内的投影为一体结构。
  8. 根据权利要求2所述的显示面板，其中，所述衬底基板还包括第一复位电源线、第二复位电源线和第三复位电源线，所述第一复位电源线、所述第二复位电源线和所述第三复位电源线网状连接。
  9. 根据权利要求8所述的显示面板，其中，第二金属层还包括第二辅助金属线和第三辅助金属线，所述第二辅助金属线和所述第三辅助金属线在所述衬底基板上的正投影具有至少部分与第三阳极在所述基板上的正投影交叠；所述第二辅助金属线和所述第三辅助金属线沿所述第二方向对称分布。
  10. 根据权利要求8所述的显示面板，其中，进一步包括依次层叠与所述衬底基板上的第一至第三栅极层，所述第一至第三栅极层均位于所述衬底基板和所述第一金属层之间，所述第三栅极层在第三阳极的投影区域内的投影与第二金属层在所述第三阳极的投影区域内的投影沿所述第一方向对称。
  11. 根据权利要求8所述的显示面板，其中，所述显示面板还包括像素界定层，所述像素界定层具有第一至第三开口，所述第一开口和所述第一阳极对应，所述第二开口和所述第二阳极对应，所述第三开口和所诉第三阳极对应，
    所述第一开口和所述第二开口在所述衬底基板的投影区域内包括3个过孔，在所述第三开口在所述衬底基板的投影区域内包括1.5个过孔。
  12. 根据权利要求2-11中任一所述的显示面板，其中，所述第一信号线为所述显示面板的驱动电源线，所述第二信号线为辅助驱动电源线，所述第三信号线为所述显示面板的数据信号线。
  13. 根据权利要求1-11中任一所述的显示面板，其中，所述第一金属层为第二源漏极层，第二金属层为第一源漏极层。
  14. 根据权利要求1-11中任一所述的显示面板，其中，像素电路包括：
    第一晶体管，所述第一晶体管的栅极与第一复位信号线连接，所述第一晶体管的第一极与第一复位电源线连接，所述第一晶体管的第二极与第三节点连接；
    第二晶体管，所述第二晶体管的栅极与所述显示面板包括的第一栅极信号线连接，所述第二晶体管的第一极与第一节点连接，所述第二晶体管的第二极与所述第三节点连接；
    第三晶体管，所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的第一极与第二节点连接，所述第三晶体管的第二极与所述第三节点连接；
    第四晶体管，所述第四晶体管的栅极与所述显示面板包括的第二栅极信号线连接，所述第四晶体管的第一极与所述显示面板包括的数据信号线连接，所述第四晶体管的第二极与所述第二节点连接；
    第五晶体管，所述第五晶体管的栅极与发光控制信号线连接，所述第五晶体管的第一极与所述显示面板包括的驱动电源线连接，第五晶体管的第二极与所述第二节点；
    第六晶体管，所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一极与所述第三节点连接，所述第六晶体管的第二极与发光单元连接；
    第七晶体管，所述第七晶体管的栅极与所述显示面板包括的第二栅极信号线连接，所述第七晶体管的第一极与第二复位电源线连接，所述第七晶体管的第二极与所述发光单元连接；
    第八晶体管，所述第八晶体管的栅极与所述第二复位信号线连接，所述第八晶体管的第一极和所述显示面板包括的第三复位电源线连接，所述 第八晶体管的第二极与所述第二节点连接；
    存储电容，所述存储电容的一端与所述驱动电源线连接，所述存储电容的另一端与所述第一节点连接。
  15. 一种显示装置，所述显示装置包括权利要求1-14中任一所述的显示面板。
PCT/CN2024/094323 2023-06-14 2024-05-21 显示面板及显示装置 Ceased WO2024255543A1 (zh)

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CN116685171A (zh) * 2023-06-14 2023-09-01 京东方科技集团股份有限公司 显示面板及显示装置
CN118411942A (zh) * 2024-04-26 2024-07-30 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置

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