WO2024229879A1 - 晶体管及其制造方法、存储器和电子设备 - Google Patents

晶体管及其制造方法、存储器和电子设备 Download PDF

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Publication number
WO2024229879A1
WO2024229879A1 PCT/CN2023/094294 CN2023094294W WO2024229879A1 WO 2024229879 A1 WO2024229879 A1 WO 2024229879A1 CN 2023094294 W CN2023094294 W CN 2023094294W WO 2024229879 A1 WO2024229879 A1 WO 2024229879A1
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Prior art keywords
drain
source
active layer
initial
layer
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English (en)
French (fr)
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王桂磊
项金娟
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs

Definitions

  • the present application relates to the field of semiconductor technology, and more specifically, to a transistor and a manufacturing method thereof, a memory and an electronic device.
  • Transistors have the advantages of high mobility, good stability, and simple manufacturing process, and have become a research hotspot. However, as the size of transistors continues to shrink, transistors are prone to leakage problems or obvious short channel effects.
  • the present application proposes a transistor and a manufacturing method thereof, a memory and an electronic device to solve the technical problems that the existing transistors are prone to leakage or obvious short channel effect.
  • an embodiment of the present application provides a transistor, wherein the transistor is a vertical transistor, comprising: a first source/drain, a first dielectric layer, a second source/drain, and a second dielectric layer stacked above a substrate, and an active layer extending in a first direction perpendicular to the substrate;
  • the active layer is disposed through the second dielectric layer, the second source/drain, and the first dielectric layer, and through part or all of the first source/drain, and the active layer is in contact with the first source/drain and the second source/drain;
  • the work function of the material of the first source/drain electrode is different from the work function of the material of the second source/drain electrode;
  • the active layer is a metal oxide semiconductor layer.
  • one of the materials of the first source/drain electrode and the materials of the second source/drain electrode is a metal oxide material, and the other is a metal material.
  • the work function of the metal oxide material is smaller than the work function of the active layer material, and the work function of the metal material is larger than the work function of the active layer material.
  • one of the first source/drain and the second source/drain is in non-Schottky contact with the active layer, and the other of the first source/drain and the second source/drain is in Schottky contact with the active layer.
  • the metal material of the metal oxide semiconductor layer is selected from at least one of indium, gallium, zinc, tin, titanium and aluminum.
  • an interface between one of the first source/drain and the second source/drain and the active layer comprises at least one of indium tin oxide, indium zinc oxide, and tungsten-doped indium oxide.
  • the other interface of the first source/drain and the second source/drain in contact with the active layer comprises a metal or metal nitride of at least one of titanium, tungsten, ruthenium and molybdenum.
  • an interface of one of the first source/drain and the second source/drain in contact with the active layer comprises indium tin oxide or indium zinc oxide, and an interface of the other one in contact with the active layer comprises titanium nitride.
  • At least one of the first source/drain and the second source/drain comprises a main structure, and the main structure and the active layer comprise the interface in contact with the active layer.
  • the main structure and the interface are made of the same material, which is indium tin oxide.
  • the main structure and the interface are made of different materials, and the metal material of the main structure is selected from at least one of tungsten, copper, aluminum and silver.
  • the active layer is a hollow cylinder, the outer surface of the active layer is coupled to the first source/drain and the second source/drain, and the average oxygen concentration of the area of the active layer close to the first source/drain or the second source/drain is the same as the average oxygen concentration of the area far away from the first source/drain or the second source/drain.
  • an embodiment of the present application provides a memory comprising at least one transistor as described in the first aspect.
  • an embodiment of the present application provides an electronic device, comprising the memory described in the second aspect.
  • an embodiment of the present application provides a method for manufacturing a transistor, comprising:
  • the initial second dielectric layer, the initial second source/drain, the initial first dielectric layer and a partial or full thickness of the initial first source/drain are patterned to form a second dielectric layer, a second source/drain, a first dielectric layer and a first source/drain, and a hole penetrating the second dielectric layer, the second source/drain, the first dielectric layer and a partial or full thickness of the first source/drain; the first direction is perpendicular to the substrate;
  • a conformal initial active layer is fabricated in the hole and above the second dielectric layer away from the substrate.
  • the method further comprises:
  • An initial gate insulating layer and an initial gate are sequentially conformally manufactured on the inner surface of the initial active layer located in the hole and on the upper surface of the initial active layer located above the second dielectric layer away from the substrate.
  • the method further includes:
  • the initial active layer, the initial gate insulating layer and the initial gate located above the second dielectric layer away from the substrate are patterned to obtain an active layer, a gate insulating layer and a gate.
  • the work function of the material of the first source/drain is different from the work function of the material of the second source/drain, which means that the work function of the material of the first source/drain can be higher than the work function of the material of the second source/drain, or the work function of the material of the first source/drain can be lower than the work function of the material of the second source/drain.
  • the material with a higher work function contacts the active layer and can form a Schottky contact, generate a depletion layer, and suppress channel leakage, thereby improving the retention characteristics of the transistor;
  • the material with a lower work function contacts the active layer and can form an ohmic contact without a depletion layer, which can have It is helpful to suppress the short channel effect, which in turn is helpful to improve the leakage performance of the transistor, thereby helping to reduce the self-heating effect of the transistor and improving the reliability of the transistor.
  • the active layer and the gate are both extended along the first direction (vertical direction), which can reduce the size of the transistor as much as possible.
  • FIG1 is a schematic cross-sectional view of a film layer of a transistor provided in an embodiment of the present application.
  • FIG2 is a schematic cross-sectional view of a film layer of another transistor provided in an embodiment of the present application.
  • FIG3 is a schematic cross-sectional view of a film layer of another transistor provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of a process flow of a method for manufacturing a transistor provided in an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional view of a film layer obtained after sequentially manufacturing an initial first source/drain, an initial first dielectric layer, an initial second source/drain, and an initial second dielectric layer above a substrate in a method for manufacturing a transistor provided in an embodiment of the present application;
  • FIG. 6 is a schematic diagram of a cross-sectional view of a film layer after patterning an initial second dielectric layer, an initial second source/drain, an initial first dielectric layer, and a partial or full thickness of an initial first source/drain to form a second dielectric layer, a second source/drain, a first dielectric layer, and a first source/drain, and forming a hole penetrating the second dielectric layer, the second source/drain, the first dielectric layer, and a partial or full thickness of the first source/drain in a method for manufacturing a transistor provided in an embodiment of the present application;
  • FIG. 7 is a schematic cross-sectional view of a film layer after manufacturing a conformal initial active layer in a hole and above a second dielectric layer away from a substrate in a method for manufacturing a transistor provided in an embodiment of the present application;
  • Figure 8 is a schematic cross-sectional diagram of a film layer after sequentially conformingly manufacturing an initial gate insulating layer and an initial gate on the inner surface of an initial active layer located in a hole and on the upper surface of an active layer located above a second dielectric layer away from a substrate in a transistor manufacturing method provided in an embodiment of the present application.
  • An embodiment of the present application provides a transistor, which is a vertical transistor.
  • the structural schematic diagram of the transistor is shown in Figures 1 to 3, including: a stacked first source/drain 2, a first dielectric layer 3, a second source/drain 4, and a second dielectric layer 5 arranged above a substrate 1, and an active layer 6 extending along a first direction perpendicular to the substrate 1.
  • the active layer 6 penetrates the second dielectric layer 5 , the second source/drain 4 , the first dielectric layer 3 , and penetrates part or all of the first source/drain 2 .
  • the active layer 6 contacts the first source/drain 2 and the second source/drain 4 .
  • the work function of the material of the first source/drain electrode 2 is different from the work function of the material of the second source/drain electrode 4 .
  • the active layer 6 is a metal oxide semiconductor layer.
  • the first direction is a direction perpendicular to the substrate 1, that is, a vertical direction.
  • the first source/drain 2 can be a source or a drain, and correspondingly, the second source/drain 4 can be a drain or a source, which can be specifically limited according to actual needs and is not limited here.
  • the first source/drain 2 and the second source/drain 4 are stacked in a vertical direction, which can reduce the size of the transistor as much as possible.
  • the active layer 6 passes through the second dielectric layer 5, the second source/drain 4, the first dielectric layer 3 and part of the first source/drain 2, and the bottom of the active layer 6 contacts the first source/drain 2 with a partial thickness.
  • the active layer 6 passes through the second dielectric layer 5, the second source/drain 4, the first dielectric layer 3 and the entire first source/drain 2, and the bottom of the active layer 6 penetrates the first source/drain 2.
  • the active layer 6 between the first source/drain 2 and the second source/drain 4 can form a channel when an external electric field is applied, and the part of the active layer 6 that serves as the channel is arranged in the vertical direction, which can further reduce the size of the transistor.
  • the bottom surface of the active layer 6 is closer to the substrate 1 than the upper surface of the first source/drain 2, thereby increasing the contact area between the active layer 6 and the first source/drain 2 and avoiding poor contact between the active layer 6 and the first source/drain 2 when an external electric field is applied.
  • the work function of the material of the first source/drain 2 is different from the work function of the material of the second source/drain 4, which means that the work function of the material of the first source/drain 2 can be higher than the work function of the material of the second source/drain 4, or the work function of the material of the first source/drain 2 can be lower than the work function of the material of the second source/drain 4.
  • one of the first source/drain 2 and the second source/drain 4 is in non-Schottky contact with the active layer 6
  • the other of the first source/drain 2 and the second source/drain 4 is in Schottky contact with the active layer 6 .
  • the non-Schottky contact is an ohmic contact.
  • the metal material with a higher work function in one of the first source/drain 2 and the second source/drain 4 contacts the active layer 6, which is a Schottky contact. Since the Fermi level of the metal material with a higher work function is lower than the Fermi level of the active layer 6, the electrons in the active layer 6 flow to the metal material with a higher work function, and the energy band of the active layer 6 bends upward.
  • the active layer 6 with an upwardly bent energy band forms an electron depletion layer due to electron depletion, and an energy barrier is formed at the interface between the metal material with a higher work function in one of the first source/drain 2 and the second source/drain 4 and the active layer 6.
  • the energy barrier is not conducive to electron transport, so it can reduce channel leakage, thereby improving the retention characteristics of the transistor.
  • the material with a lower work function in one of the first source/drain 2 and the second source/drain 4 contacts the active layer 6, which is an ohmic contact. Since the Fermi level of the metal material with a lower work function is higher than the Fermi level of the active layer 6, the electrons in the metal material with a lower work function flow to the active layer 6, and the energy band of the active layer 6 bends downward.
  • the active layer with a downwardly bent energy band has no depletion layer and a small contact resistance, which is beneficial to increasing the on-state current of the channel.
  • the threshold voltage will not change as the channel length decreases, so it can be beneficial to suppress the short channel effect; due to the suppression of the short channel effect, it is beneficial to improve the leakage performance of the transistor, thereby reducing the self-heating effect of the transistor and improving the reliability of the transistor.
  • the present application utilizes the asymmetric first source/drain 2 and the second source/drain 4 to directly achieve comprehensive optimization of parameters in terms of channel leakage, channel on-state current, retention characteristics and short channel effect.
  • one of the material of the first source/drain electrode 2 and the material of the second source/drain electrode 4 is a metal oxide material, and the other is a metal material.
  • the material of the first source/drain 2 may be a metal oxide material or a metal material
  • the material of the second source/drain 4 may be a metal material or a metal oxide conductive material
  • the metal oxide material is a conductive material.
  • the work function of the metal oxide material is smaller than the work function of the material of the active layer 6 ; the work function of the metal material is larger than the work function of the material of the active layer 6 .
  • the work function of the metal oxide material is less than the work function of the material of the active layer 6, and the work function of the metal material is greater than the work function of the material of the active layer 6.
  • the work function of the metal oxide material is not less than 2.5eV and less than 4.5eV; the work function of the metal material is not less than 4.5eV and not more than 5.5eV.
  • the work function of the metal oxide material within the above range can be conducive to the ohmic contact between the metal oxide material and the active layer 6, which is conducive to suppressing the short channel effect, reducing the transistor leakage and self-heating effect; the work function of the metal material within the above range can be conducive to the Schottky contact between the metal material and the active layer 6, which is conducive to suppressing channel leakage and improving the retention characteristics of the transistor.
  • the work function of the active layer 6 material is related to the composition ratio of its own material, and the work function of the active layer 6 material can be within a certain range of about 4.5eV, for example, the work function of the active layer 6 material is not less than 4.4eV and not more than 4.6eV.
  • the metal oxide material includes at least one of indium tin oxide, indium zinc oxide and tungsten-doped indium oxide; and the metal material includes at least one of titanium nitride, tungsten, ruthenium and molybdenum.
  • indium tin oxide, indium zinc oxide and tungsten-doped indium oxide in the metal oxide materials are all low work function oxide materials (low work function means that the work function of the material is lower than the work function of the material of the active layer 6).
  • Titanium nitride, tungsten, ruthenium and molybdenum in the metal materials are all high work function metal materials (high work function means that the work function of the material is higher than the work function of the material of the active layer 6).
  • the metal material of the metal oxide semiconductor layer is selected from at least one of indium, gallium, zinc, tin, titanium and aluminum.
  • the metal material of the metal oxide semiconductor layer can be selected from at least one of the above.
  • the material of the metal oxide semiconductor layer can include one or more combinations of indium gallium zinc oxide, indium aluminum zinc oxide, indium tin oxide and tungsten-doped indium oxide.
  • the interface 101 at which one of the first source/drain electrode 2 and the second source/drain electrode 4 contacts the active layer 6 comprises at least one of indium tin oxide, indium zinc oxide, and tungsten-doped indium oxide.
  • the interface 101 includes at least one metal or metal nitride of titanium, tungsten, ruthenium, and molybdenum.
  • the interface 101 of the present application may be a part of one of the first source/drain 2 and the second source/drain 4 , or a separate part.
  • the interface 101 at which one of the first source/drain 2 and the second source/drain 4 contacts the active layer 6 comprises at least one of indium tin oxide, indium zinc oxide, and tungsten-doped indium oxide, and indium tin oxide, indium zinc oxide, and tungsten-doped indium oxide are all low work function oxide materials (low work function means that the work function of the material is lower than the work function of the active layer 6 material).
  • Another interface 101 of the first source/drain 2 and the second source/drain 4 in contact with the active layer 6 comprises at least one metal or metal nitride of titanium, tungsten, ruthenium, and molybdenum.
  • the metals or metal nitrides of titanium, tungsten, ruthenium, and molybdenum are all high work function metal materials (high work function means that the work function of the material is higher than the work function of the active layer 6 material).
  • the material with a higher work function is in contact with the active layer 6 to form a Schottky contact and produce a depletion layer, which can suppress channel leakage and thus improve the retention characteristics of the transistor;
  • the material with a lower work function is in contact with the active layer 6 to form an ohmic contact without a depletion layer, which can help suppress the short channel effect, and further help improve the leakage performance of the transistor, thereby helping to reduce the self-heating effect of the transistor and improve the reliability of the transistor.
  • the interface 101 of one of the first source/drain electrode 2 and the second source/drain electrode 4 in contact with the active layer 6 comprises indium tin oxide or indium zinc oxide, and the interface 101 of the other in contact with the active layer 6 comprises titanium nitride.
  • At least one of the first source/drain 2 and the second source/drain 4 includes a main structure 102 , and an interface 101 in contact with the active layer 6 is included between the main structure 102 and the active layer 6 .
  • At least one of the first source/drain 2 and the second source/drain 4 includes two independent parts: a main structure 102 and an interface 101 .
  • the main structure 102 and the interface 101 are made of the same material, which is indium tin oxide.
  • the material of the main structure 102 and the material of the interface 101 can both be indium tin oxide.
  • the indium tin oxide material is a metal oxide material and does not have oxygen absorption properties. It can ensure that oxygen in the active layer 6 is not absorbed to avoid causing electrical drift.
  • the interface 101 can form a Schottky contact or an ohmic contact with the active layer 6, which is conducive to saving manufacturing processes and time.
  • the main structure 102 and the interface 101 are made of different materials, and the metal material of the main structure 102 is selected from at least one of tungsten, copper, aluminum, and silver.
  • the metal material of the main structure 102 is selected from at least one of tungsten, copper, aluminum, and silver, that is, the resistivity of the main structure 102 is lower than the resistivity of the interface 101, which can be beneficial to improving the current rate.
  • the active layer 6 is a hollow cylinder, and the outer surface of the active layer 6 is coupled to the first source/drain 2 and the second source/drain 4, and the average oxygen concentration of the area close to the first source/drain 2 or the second source/drain 4 in the active layer 6 is the same as the average oxygen concentration of the area far away from the first source/drain 2 or the second source/drain 4.
  • the active layer 6 is hollow and cylindrical, and the longitudinal section of the active layer 6 includes a "U" shape.
  • the outer surface of the active layer 6 is in contact with the first source/drain 2 and the second source/drain 4 or is signal-connected.
  • the average oxygen concentration of the region near the first source/drain 2 or the second source/drain 4 in the active layer 6 is the same as the average oxygen concentration of the region far away from the first source/drain 2 or the second source/drain 4, thereby avoiding electrical drift of the active layer 6.
  • the material of one of the first source/drain 2 and the second source/drain 4 is a metal oxide material, which does not have oxygen absorption properties, and can ensure that the average oxygen concentration of the region near the first source/drain 2 or the second source/drain 4 in the active layer 6 is the same as the average oxygen concentration of the region far away from the first source/drain 2 or the second source/drain 4 as much as possible.
  • the transistor further includes a gate insulating layer 7 and a gate 8 extending along the first direction, and the gate insulating layer 7 and the gate 8 are conformally arranged on a side of the active layer 6 away from the substrate 1 and located in the hollow cylindrical active layer 6 .
  • the gate insulating layer 7 is prepared in a hollow cylindrical active layer 6, and the longitudinal section of the gate insulating layer 7 also includes a U-shape.
  • the gate 8 is arranged between the two side walls of the gate insulating layer 7, that is, the gate 8 along the vertical direction is arranged in the gate insulating layer 7 with a U-shape in the longitudinal section.
  • the gate 8 is also arranged in the vertical direction, which can reduce the size of the transistor.
  • the material of the gate insulating layer 7 includes at least one of hafnium oxide, aluminum oxide, hafnium aluminum oxide, and lanthanum-doped hafnium oxide (HfLaO).
  • the gate 8 material includes at least one of indium zinc oxide, indium tin oxide, and tungsten.
  • the materials of the gate insulating layer 7, such as hafnium oxide, aluminum oxide, hafnium aluminum oxide and lanthanum-doped hafnium oxide, are all high dielectric constant materials. Compared with silicon dioxide materials, high dielectric constant materials can maintain the driving current, reduce the leakage current density, and maintain excellent leakage performance. Indium zinc oxide, indium tin oxide and tungsten are all conductive materials in the gate 8 materials.
  • an embodiment of the present application provides a memory, comprising at least one transistor provided by the above embodiment.
  • the beneficial effects of the memory include the beneficial effects of the transistor provided in the above embodiment, which will not be repeated here.
  • the memory comprises a plurality of transistors arranged in a stack.
  • an embodiment of the present application provides an electronic device, including the memory provided by the above embodiment.
  • the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
  • electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set the memory provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in the embodiments of the present application.
  • an embodiment of the present application provides a method for manufacturing a transistor.
  • the flowchart of the method for manufacturing a transistor is shown in FIG4 .
  • the method includes the following steps S1 to S3:
  • FIG5 is a schematic cross-sectional view of the film layer obtained after sequentially manufacturing the initial first source/drain 21, the initial first dielectric layer 31, the initial second source/drain 41 and the initial second dielectric layer 51 on the substrate 1.
  • the initial first source/drain 21 and the initial second source/drain 41 are stacked in a vertical direction, which can minimize the size of the transistor.
  • the work function of the material of the initial first source/drain 21 and the work function of the material of the initial second source/drain 41 Different work functions mean that the work function of the material of the first source/drain 2 manufactured subsequently is different from the work function of the material of the second source/drain 4.
  • the work function of the material of the first source/drain 2 may be higher than the work function of the material of the second source/drain 4, or the work function of the material of the first source/drain 2 may be lower than the work function of the material of the second source/drain 4.
  • the material with a higher work function contacts the active layer 6 manufactured subsequently, and can form a Schottky contact, generate a depletion layer, and suppress channel leakage, thereby improving the retention characteristics of the transistor;
  • the material with a lower work function contacts the active layer 6 manufactured subsequently, and can form an ohmic contact without a depletion layer, which can help suppress the short channel effect, thereby helping to improve the leakage performance of the transistor, thereby helping to reduce the self-heating effect of the transistor, and helping to improve the reliability of the transistor.
  • Figure 6 is a schematic diagram of the film layer cross-section after patterning the initial second dielectric layer 51, the initial second source/drain 41, the initial first dielectric layer 31 and the initial first source/drain 21 of partial or full thickness to form the second dielectric layer 5, the second source/drain 4, the first dielectric layer 3 and the first source/drain 2, and forming a hole that penetrates the second dielectric layer 5, the second source/drain 4, the first dielectric layer 3 and the first source/drain 2 of partial or full thickness.
  • the second dielectric layer 5, the second source/drain 4, the first dielectric layer 3 and a partial or full thickness of the first source/drain 2 are patterned, including a photolithography process and an etching process.
  • etching the first source/drain 2 a partial or full thickness of the first source/drain 2 is etched away, which can increase the contact area between the subsequently manufactured active layer 6 and the first source/drain 2, and is conducive to increasing the contact stability between the subsequently manufactured active layer 6 and the first source/drain 2.
  • one of the materials of the first source/drain 2 and the second source/drain 4 is a metal oxide material, and the other is a metal material; the work function of the metal oxide material is smaller than the work function of the active layer 6 material; the work function of the metal material is larger than the work function of the active layer 6 material.
  • the material of the first source/drain 2 can be a metal oxide material or a metal material
  • the material of the second source/drain 4 can be a metal material or a metal oxide material. Chemical materials.
  • the work function of the metal oxide material is less than the work function of the material of the active layer 6 to be manufactured later; the work function of the metal material is greater than the work function of the material of the active layer 6 to be manufactured later.
  • the work function of the metal oxide conductive material is not less than 2.5 eV and less than 4.5 eV; the work function of the metal material is not less than 4.5 eV and not greater than 5.5 eV.
  • the interface 101 at which one of the first source/drain electrode 2 and the second source/drain electrode 4 contacts the active layer 6 comprises at least one of indium tin oxide, indium zinc oxide, and tungsten-doped indium oxide.
  • another interface 101 of the first source/drain electrode 2 and the second source/drain electrode 4 that contacts the active layer 6 comprises at least one metal or metal nitride of titanium, tungsten, ruthenium, and molybdenum.
  • the interface 101 of the present application may be a part of one of the first source/drain 2 and the second source/drain 4 .
  • the interface 101 at which one of the first source/drain 2 and the second source/drain 4 contacts the active layer 6 comprises at least one of indium tin oxide, indium zinc oxide, and tungsten-doped indium oxide, and indium tin oxide, indium zinc oxide, and tungsten-doped indium oxide are all low work function oxide materials (low work function means that the work function of the material is lower than the work function of the active layer 6 material).
  • Another interface 101 of the first source/drain 2 and the second source/drain 4 in contact with the active layer 6 comprises at least one metal or metal nitride of titanium, tungsten, ruthenium, and molybdenum.
  • the metals or metal nitrides of titanium, tungsten, ruthenium, and molybdenum are all high work function metal materials (high work function means that the work function of the material is higher than the work function of the active layer 6 material).
  • the material with a higher work function is in contact with the active layer 6 to form a Schottky contact and produce a depletion layer, which can suppress channel leakage and thus improve the retention characteristics of the transistor;
  • the material with a lower work function is in contact with the active layer 6 to form an ohmic contact without a depletion layer, which can help suppress the short channel effect, and further help improve the leakage performance of the transistor, thereby helping to reduce the self-heating effect of the transistor and improve the reliability of the transistor.
  • the metal oxide material includes at least one of indium tin oxide, indium zinc oxide and tungsten-doped indium oxide; the metal material includes at least one of titanium nitride, tungsten, ruthenium and molybdenum.
  • indium tin oxide, indium zinc oxide and tungsten-doped indium oxide in the metal oxide conductive materials are all low work function oxide materials.
  • Titanium nitride, tungsten, ruthenium and molybdenum in the metal materials are all high work function metal materials.
  • Fig. 7 is a schematic cross-sectional view of a film layer after manufacturing a conformal initial active layer 61 in the hole 9 and above the second dielectric layer 5 away from the substrate 1.
  • the initial active layer 61 includes a first vertical portion located in the hole 9 and a first horizontal portion located above the second dielectric layer 5 away from the substrate 1.
  • the bottom surface of the initial active layer 61 is closer to the substrate 1 than the upper surface of the first source/drain 2, thereby increasing the contact area between the subsequently manufactured active layer 6 and the first source/drain 2, and avoiding the phenomenon of poor contact between the subsequently manufactured active layer 61 and the first source/drain 2 when an external electric field is applied.
  • the active layer 6 manufactured later between the first source/drain 2 and the second source/drain 4 can form a channel under the application of an external electric field.
  • the active layer 6 manufactured later as part of the channel is arranged in a vertical direction, which can further reduce the size of the transistor.
  • An initial gate insulating layer 71 and an initial gate 81 are sequentially conformally manufactured on the inner surface of the initial active layer 61 located in the hole 9 and on the upper surface of the active layer 61 located above the second dielectric layer 5 away from the substrate 1 .
  • FIG8 is a schematic cross-sectional view of the film layers after the initial gate insulating layer 71 and the initial gate 81 are sequentially formed on the inner surface of the initial active layer 61 located in the hole 9 and the upper surface of the active layer 61 located above the second dielectric layer 5 away from the substrate 1.
  • the initial active layer 61 includes a first vertical portion located in the hole 9 and a first horizontal portion located above the second dielectric layer 5 away from the substrate 1.
  • the first vertical portion extends in a first direction
  • the first horizontal portion extends in a direction parallel to the substrate 1.
  • the initial gate insulating layer 71 of the present application includes a second vertical portion and a second horizontal portion, the second vertical portion being a portion of the first vertical portion of the initial active layer 61 located away from the substrate 1 and the second horizontal portion being a portion of the first horizontal portion of the initial active layer 61 located away from the substrate 1.
  • the initial gate 81 includes a third vertical portion and a third horizontal portion, the third vertical portion is located between the two side walls of the second vertical portion of the initial gate insulating layer 71, and the third horizontal portion is located on the upper side of the second horizontal portion of the initial gate insulating layer 71 away from the substrate 1.
  • the gate 8 obtained by subsequent manufacturing is also arranged in the vertical direction, which can reduce the size of the transistor.
  • the method further includes:
  • the initial active layer 61 , the initial gate insulating layer 71 and the initial gate 81 located above the second dielectric layer 5 away from the substrate 1 are patterned to obtain the active layer 6 , the gate insulating layer 7 and the gate 8 .
  • FIG. 1 is a schematic cross-sectional view of the film layers after patterning the initial active layer 61 , the initial gate insulating layer 71 and the initial gate 81 located above the second dielectric layer 5 away from the substrate 1 to obtain the active layer 6 , the gate insulating layer 7 and the gate 8 .
  • the initial active layer 61, the initial gate insulating layer 71 and the initial gate 81 located on the second dielectric layer 5 away from the substrate 1 are partially removed, that is, the first horizontal portion of the initial active layer 61, the second horizontal portion of the initial gate insulating layer 71 and the two ends of the third horizontal portion of the initial gate 81 are removed, thereby avoiding a short circuit after contact with other transistors.
  • the metal material of the metal oxide semiconductor layer is selected from at least one of indium, gallium, zinc, tin, titanium and aluminum.
  • the material of the active layer 6 includes at least one of indium gallium zinc oxide, indium aluminum zinc oxide, indium tin oxide and tungsten-doped indium oxide.
  • the material of the active layer 6 includes one or more of indium gallium zinc oxide, indium aluminum zinc oxide, indium tin oxide and tungsten-doped indium oxide in a stacked arrangement, which can be specifically selected according to actual conditions.
  • the material of the gate insulating layer 7 includes at least one of hafnium oxide, aluminum oxide, hafnium aluminum oxide and lanthanum-doped hafnium oxide.
  • the material of the gate 8 includes at least one of indium zinc oxide, indium tin oxide and tungsten.
  • the materials of the gate insulating layer 7, such as hafnium oxide, aluminum oxide, hafnium aluminum oxide and lanthanum-doped hafnium oxide, are all high dielectric constant materials. Compared with silicon dioxide materials, high dielectric constant materials can maintain the driving current, reduce the leakage current density, and maintain excellent leakage performance.
  • high dielectric constant materials can maintain the driving current, reduce the leakage current density, and maintain excellent leakage performance.
  • indium zinc oxide, indium tin oxide and tungsten are all conductive materials.
  • part of the active layer serving as the channel is arranged in the vertical direction, which can further reduce the size of the transistor.
  • the work function of the material of the first source/drain is different from the work function of the material of the second source/drain, which means that the work function of the material of the first source/drain can be higher than the work function of the material of the second source/drain, or the work function of the material of the first source/drain can be lower than the work function of the material of the second source/drain.
  • the material with a higher work function contacts the active layer to form a Schottky contact, generate a depletion layer, and suppress channel leakage, thereby improving the retention characteristics of the transistor;
  • the material with a lower work function contacts the active layer to form an ohmic contact without a depletion layer, which can help suppress the short channel effect, thereby helping to improve the leakage performance of the transistor, thereby helping to reduce the self-heating effect of the transistor and improve the reliability of the transistor.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, “plurality” means two or more.
  • the term "installed”, “connected” and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components.

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  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

本申请提供了一种晶体管及其制造方法、存储器和电子设备。属于半导体器件及制作领域。该晶体管为垂直晶体管，包括设置于衬底上方的层叠的第一源/漏极、第一介质层、第二源/漏极和第二介质层，以及沿垂直于衬底的第一方向延伸的有源层。有源层穿设于第二介质层、第二源/漏极、第一介质层和部分或全部的第一源/漏极，有源层的底部贯穿第一源/漏极或与部分的第一源/漏极接触。第一源/漏极的材料的功函数与第二源/漏极的材料的功函数不同。有源层为金属氧化物半导体层。本申请能够抑制沟道漏电同时有利于抑制短沟道效应。

Description

晶体管及其制造方法、存储器和电子设备 技术领域
本申请涉及半导体技术领域，具体而言，本申请涉及一种晶体管及其制造方法、存储器和电子设备。
背景技术
晶体管具有高迁移率、稳定性好、制作工艺简单等优点，成为研究热点。然而，随着晶体管尺寸的不断微缩，晶体管容易出现漏电问题，或者短沟道效应明显。
发明内容
本申请针对现有方式的缺点，提出一种晶体管及其制造方法、存储器和电子设备，用以解决现有晶体管容易出现漏电或者短沟道效应明显的技术问题。
第一个方面，本申请实施例提供了一种晶体管，所述晶体管为垂直晶体管，包括：设置于衬底上方的层叠的第一源/漏极、第一介质层、第二源/漏极和第二介质层，以及沿垂直于所述衬底的第一方向延伸的有源层；
所述有源层穿设于所述第二介质层、所述第二源/漏极、所述第一介质层，穿设于部分或全部的所述第一源/漏极，所述有源层与所述第一源/漏极和所述第二源/漏极接触；
所述第一源/漏极的材料的功函数与所述第二源/漏极的材料的功函数不同；
所述有源层为金属氧化物半导体层。
可选地，所述第一源/漏极的材料和所述第二源/漏极的材料中其中一个为金属氧化物材料，另一个为金属材料。
可选地，所述金属氧化物材料的功函数小于所述有源层材料的功函数，所述金属材料的功函数大于所述有源层材料的功函数。
可选地，所述第一源/漏极和第二源/漏极的其中之一与所述有源层之间为非肖特基接触，所述第一源/漏极和第二源/漏极的另一个与所述有源层之间为肖特基接触。
可选地，所述金属氧化物半导体层的金属材料选自铟、镓、锌、锡、钛、铝中的至少一种。
可选地，所述第一源/漏极和第二源/漏极的其中之一与所述有源层接触的界面包含氧化铟锡、氧化铟锌、掺钨氧化铟中至少一种。
可选地，所述第一源/漏极和第二源/漏极的另一个与所述有源层接触的界面包含钛、钨、钌、钼中至少之一的金属或金属氮化物。
可选地，所述第一源/漏极和第二源/漏极的其中之一与所述有源层接触的界面包含氧化铟锡或氧化铟锌，另一与所述有源层接触的界面包含氮化钛。
可选地，所述第一源/漏极和所述第二源/漏极至少之一包含主体结构，所述主体结构和所述有源层之间包含与所述有源层接触的所述界面。
可选地，所述主体结构和所述界面包含的材料为相同的材料，均为氧化铟锡。
可选地，所述主体结构和所述界面包含的材料为不相同的材料，所述主体结构的金属材料选自钨、铜、铝、银中至少一种。
可选地，所述有源层为中空的筒状，所述有源层的外侧表面与所述第一源/漏极和第二源/漏极耦合连接，所述有源层中靠近所述第一源/漏极或所述第二源/漏极接触的区域的平均氧浓度与远离所述第一源/漏极或所述第二源/漏极的区域的平均氧浓度相同。
第二个方面，本申请实施例提供了一种存储器，包括至少一个如第一个方面所述的晶体管。
第三个方面，本申请实施例提供了一种电子设备，包括第二个方面所述的存储器。
第四个方面，本申请实施例提供了一种晶体管的制造方法，包括：
在衬底的上方依次制造初始第一源/漏极、初始第一介质层、初始第二源/漏极和初始第二介质层；所述初始第一源/漏极的材料的功函数与所述初始第二源/漏极的材料的功函数不同；
对所述初始第二介质层、所述初始第二源/漏极、所述初始第一介质层和部分或全部厚度的所述初始第一源/漏极进行图案化，形成第二介质层、第二源/漏极、第一介质层和第一源/漏极，以及形成贯穿所述第二介质层、第二源/漏极、第一介质层和部分或全部厚度的第一源/漏极的孔；所述第一方向垂直于所述衬底；
在所述孔内和所述第二介质层远离所述衬底的上方，制造随形的初始有源层。
可选地，在所述孔内和所述第二介质层远离所述衬底的上方，制造随形的初始有源层之后，还包括：
在位于所述孔内的所述初始有源层的内表面和位于所述第二介质层远离所述衬底上方的所述初始有源层的上表面依次随形制造初始栅极绝缘层和初始栅极。
可选地，在位于所述孔内的所述初始有源层的内表面和位于所述第二介质层远离所述衬底上方的所述初始有源层的表面随形制造初始栅极绝缘层和初始栅极之后，还包括：
对位于所述第二介质层远离所述衬底上方的所述初始有源层、所述初始栅极绝缘层和所述初始栅极进行图案化，得到有源层、栅极绝缘层和栅极。
本申请实施例提供的技术方案带来的有益技术效果包括：
第一源/漏极的材料的功函数与第二源/漏极的材料的功函数不同，意味着第一源/漏极的材料的功函数可以高于第二源/漏极的材料的功函数，或者第一源/漏极的材料的功函数可以低于第二源/漏极的材料的功函数。在施加外部电场的情况下，较高功函数的材料与有源层接触，能够形成肖特基接触，产生耗尽层，能够抑制沟道漏电，从而提高晶体管的保持特性；较低功函数的材料与有源层接触，能够形成欧姆接触，无耗尽层，能够有 利于抑制短沟道效应，进而有利于提高晶体管的漏电性能，从而有利于降低晶体管的自热效应，有利于提高晶体管的可靠性。
而且，有源层和栅极均是沿第一方向(竖直方向)延伸设置的，能够尽可能地缩小晶体管的尺寸。
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本申请实施例提供的一种晶体管的膜层剖面示意图；
图2为本申请实施例提供的另一种晶体管的膜层剖面示意图；
图3为本申请实施例提供的又一种晶体管的膜层剖面示意图；
图4为本申请实施例提供的一种晶体管的制造方法的流程示意图；
图5为本申请实施例提供的一种晶体管的制造方法中在衬底的上方依次制造初始第一源/漏极、初始第一介质层、初始第二源/漏极和初始第二介质层后得到的膜层剖面示意图；
图6为本申请实施例提供的一种晶体管的制造方法中对初始第二介质层、初始第二源/漏极、初始第一介质层和部分或全部厚度的初始第一源/漏极进行图案化，形成第二介质层、第二源/漏极、第一介质层和第一源/漏极，以及形成贯穿第二介质层、第二源/漏极、第一介质层和部分或全部厚度的第一源/漏极的孔后的膜层剖面示意图；
图7为本申请实施例提供的一种晶体管的制造方法中在孔内和第二介质层远离衬底的上方，制造随形的初始有源层后的膜层剖面示意图；
图8为本申请实施例提供的一种晶体管的制造方法中在位于孔内的初始有源层的内表面和位于第二介质层远离衬底的上方的有源层的上表面依次随形制造初始栅极绝缘层和初始栅极后的膜层剖面示意图。
附图标记说明：
1-衬底；
2-第一源/漏极；21-初始第一源/漏极；
3-第一介质层；31-初始第一介质层；
4-第二源/漏极；41-初始第二源/漏极；
5-第二介质层；51-初始第二介质层；
6-有源层；61-初始有源层；
7-栅极绝缘层；71-初始栅极绝缘层；
8-栅极；81-初始栅极；
9-孔；
101-界面；
102-主体结构。
具体实施方式
下面结合本申请中的附图描述本申请的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本申请实施例的技术方案的示例性描述，对本申请实施例的技术方案不构成限制。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但不排除实现为本技术领域所支持其他特征、信息、数据、步骤、操作、元件、组件和/或它们的组合等。这里使用的术语“和/或”指该术语所限定的项目中的至少一个，例如“A和/或B”可以实现为“A”，或者实现为“B”，或者实现为“A和B”。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。需要指出的是，下述实施方式之间可以相互参考、借鉴或结合，对于不同实施方式中相同的术语、相似的特征 以及相似的实施步骤等，不再重复描述。
本申请实施例提供了一种晶体管，该晶体管为垂直晶体管，该晶体管的结构示意图如图1至图3所示，包括：设置于衬底1上方的层叠的第一源/漏极2、第一介质层3、第二源/漏极4和第二介质层5，以及沿垂直于衬底1的第一方向延伸的有源层6。
有源层6穿设于第二介质层5、第二源/漏极4、第一介质层3，穿设于部分或全部的第一源/漏极2，有源层6与第一源/漏极2和第二源/漏极4接触。
第一源/漏极2的材料的功函数与第二源/漏极4的材料的功函数不同。
有源层6为金属氧化物半导体层。
需要说明的是，第一方向为垂直于衬底1的方向，即垂直方向。第一源/漏极2可以为源极或者漏极，相对应地，第二源/漏极4可以为漏极或者源极，可以根据实际需要进行具体的限定，在此不作任何限定。
本申请实施例提供的晶体管中，第一源/漏极2和第二源/漏极4沿垂直方向层叠设置，能够尽可能减小晶体管的尺寸。
本申请实施例中，参考图1，有源层6穿过第二介质层5、第二源/漏极4、第一介质层3和部分的第一源/漏极2，有源层6的底部与部分厚度的第一源/漏极2接触。参考图2，有源层6穿过第二介质层5、第二源/漏极4、第一介质层3和全部的第一源/漏极2，有源层6的底部贯穿第一源/漏极2。在图1和图2两种情况下，第一源/漏极2和第二源/漏极4之间的有源层6在施加外部电场的情况下能够形成沟道，则作为沟道的部分有源层6是沿竖直方向设置的，能够进一步地缩小晶体管的尺寸。
再参考图1，有源层6的底面比第一源/漏极2的上表面更靠近衬底1，由此能够增大有源层6与第一源/漏极2的接触面积，避免在施加外部电场的情况下，有源层6与第一源/漏极2接触不良的现象。
本申请实施例中，第一源/漏极2的材料的功函数与第二源/漏极4的材料的功函数不同，意味着第一源/漏极2的材料的功函数可以高于第二源/漏极4的材料的功函数，或者第一源/漏极2的材料的功函数可以低于第二源/漏极4的材料的功函数。
可选地，第一源/漏极2和第二源/漏极4的其中之一与有源层6之间为非肖特基接触，第一源/漏极2和第二源/漏极4的另一个与有源层6之间为肖特基接触。
本申请实施例中，非肖特基接触为欧姆接触。
在施加外部电场的情况下，第一源/漏极2和第二源/漏极4的其中之一中的较高功函数的金属材料与有源层6接触，即为肖特基接触。由于较高功函数的金属材料的费米能级低于有源层6的费米能级，有源层6中的电子流向较高功函数的金属材料，则有源层6的能带向上弯曲。能带向上弯曲的有源层6由于电子耗尽形成电子耗尽层，在第一源/漏极2和第二源/漏极4的其中之一中的较高功函数的金属材料与有源层6的界面形成能量势垒，该能量势垒不利于电子运输，因此能够降低沟道漏电，从而提高晶体管的保持特性。
在施加外部电场的情况下，第一源/漏极2和第二源/漏极4的其中之一中的较低功函数的材料与有源层6接触，即为欧姆接触。由于较低功函数的金属材料的费米能级高于有源层6的费米能级，较低功函数的金属材料中的电子流向有源层6，则有源层6的能带向下弯曲。能带向下弯曲的有源层无耗尽层，接触电阻较小，有利于提升沟道的开态电流。由于无耗尽区的产生，阈值电压不会随着沟道长度减小而变化，因此能够有利于抑制短沟道效应；由于短沟道效应的抑制，有利于提高晶体管的漏电性能，从而有利于降低晶体管的自热效应，有利于提高晶体管的可靠性。
综上，本申请利用非对称的第一源/漏极2和第二源/漏极4，可以在沟道漏电、沟道开态电流、保持特性和短沟道效应等方面直接实现参数的综合优化。
可选地，第一源/漏极2的材料和第二源/漏极4的材料中其中一个为金属氧化物材料，另一个为金属材料。
本申请实施例中，第一源/漏极2的材料可以为金属氧化物材料或者金属材料，相对应地，第二源/漏极4的材料可以为金属材料或者金属氧化物导电材料。
需要说明的是，金属氧化物材料为导电材料。
可选地，金属氧化物材料的功函数小于有源层6的材料的功函数；金属材料的功函数大于有源层6的材料的功函数。
本申请实施例中，金属氧化物材料的功函数小于有源层6的材料的功函数，金属材料的功函数大于有源层6材料的功函数。具体地，金属氧化物材料的功函数不小于2.5eV且小于4.5eV；金属材料的功函数不小于4.5eV且不大于5.5eV。金属氧化物材料的功函数在上述范围内能够有利于金属氧化物材料与有源层6之间为欧姆接触，有利于抑制短沟道效应，降低晶体管漏电情况和自热效应；金属材料的功函数在上述范围内能够有利于金属材料与有源层6之间为肖特基接触，有利于抑制沟道漏电，有利于提高晶体管的保持特性。
可以理解的是，有源层6材料的功函数与其本身材料的成分比例有关，有源层6材料的功函数可以在4.5eV上下一定范围内，比如有源层6材料的功函数不小于4.4eV且不大于4.6eV。
可选地，金属氧化物材料包括氧化铟锡、氧化铟锌和掺钨氧化铟中至少一种；金属材料包括氮化钛、钨、钌和钼中至少一种。
本申请实施例中，金属氧化物材料中氧化铟锡、氧化铟锌和掺钨氧化铟均属于低功函数氧化物材料(低功函数的意思是材料的功函数低于有源层6材料的功函数)。金属材料中氮化钛、钨、钌和钼均属于高功函数金属材料(高功函数的意思是材料的功函数高于有源层6材料的功函数)。
可选地，金属氧化物半导体层的金属材料选自铟、镓、锌、锡、钛、铝中的至少一种。
本申请实施例中，金属氧化物半导体层的金属材料可以选自以上中至少一种，具体地，金属氧化物半导体层的材料可以包括氧化铟镓锌、氧化铟铝锌、氧化铟锡和掺钨氧化铟中一种或者多种组合叠层设置。
可选地，第一源/漏极2和第二源/漏极4的其中之一与有源层6接触的界面101包含氧化铟锡、氧化铟锌、掺钨氧化铟中至少一种。
可选地，第一源/漏极2和第二源/漏极4的另一个与有源层6接触的 界面101包含钛、钨、钌、钼中至少之一的金属或金属氮化物。
参考图1，本申请的界面101可以是第一源/漏极2和第二源/漏极4的其中之一的一部分，或者是单独的一部分。
本申请实施例中，第一源/漏极2和第二源/漏极4的其中之一与有源层6接触的界面101包含氧化铟锡、氧化铟锌、掺钨氧化铟中至少一种，氧化铟锡、氧化铟锌和掺钨氧化铟均属于低功函数氧化物材料(低功函数的意思是材料的功函数低于有源层6材料的功函数)。第一源/漏极2和第二源/漏极4的另一个与有源层6接触的界面101包含钛、钨、钌、钼中至少之一的金属或金属氮化物，钛、钨、钌和钼的金属或金属氮化物均属于高功函数金属材料(高功函数的意思是材料的功函数高于有源层6材料的功函数)，较高功函数的材料与有源层6接触，能够形成肖特基接触，产生耗尽层，能够抑制沟道漏电，从而提高晶体管的保持特性；较低功函数的材料与有源层6接触，能够形成欧姆接触，无耗尽层，能够有利于抑制短沟道效应，进而有利于提高晶体管的漏电性能，从而有利于降低晶体管的自热效应，有利于提高晶体管的可靠性。
可选地，第一源/漏极2和第二源/漏极4的其中之一与有源层6接触的界面101包含氧化铟锡或氧化铟锌，另一与有源层6接触的界面101包含氮化钛。
可选地，第一源/漏极2和第二源/漏极4的至少之一包含主体结构102，主体结构102和有源层6之间包含与有源层6接触的界面101。
本申请实施例中，参考图3，第一源/漏极2和第二源/漏极4的至少之一包括主体结构102与界面101两个独立的部分。
可选地，主体结构102和界面101包含的材料为相同的材料，均为氧化铟锡。
本申请实施例中，主体结构102的材料和界面101的材料均可以为氧化铟锡，氧化铟锡材料属于金属氧化物材料，本身不具有吸氧特性，能够保证不吸收有源层6中的氧，避免引起电性漂移。而且该界面101能与有源层6形成肖特基接触或者欧姆接触，有利于节省制造工艺，节省时间。
可选地，主体结构102和界面101包含的材料为不相同的材料，主体结构102的金属材料选自钨、铜、铝、银中至少一种。
本申请实施例中，当主体结构102和界面101包含的材料为不相同的材料，主体结构102的金属材料选自钨、铜、铝、银中至少一种，即主体结构102的电阻率低于界面101的电阻率，能够有利于提升电流速率。
可选地，有源层6为中空的筒状，有源层6的外侧表面与第一源/漏极2和第二源/漏极4耦合连接，有源层6中靠近第一源/漏极2或第二源/漏极4的区域的平均氧浓度与远离第一源/漏极2或第二源/漏极4的区域的平均氧浓度相同。
本申请实施例中，有源层6为中空的筒状，有源层6的纵截面包含“U”型状。有源层6的外侧表面与第一源/漏极2和第二源/漏极4接触或者信号连接。
有源层6中靠近第一源/漏极2或第二源/漏极4的区域的平均氧浓度与远离第一源/漏极2或第二源/漏极4的区域的平均氧浓度相同，由此能够避免有源层6的电性漂移。第一源/漏极2和第二源/漏极4中之一的材料为金属氧化物材料，不具有吸氧特性，能够尽可能保证有源层6中靠近第一源/漏极2或第二源/漏极4的区域的平均氧浓度与远离第一源/漏极2或第二源/漏极4的区域的平均氧浓度相同。
可选地，晶体管还包括沿第一方向延伸设置的栅极绝缘层7和栅极8，栅极绝缘层7和栅极8随形设置于有源层6远离衬底1的一侧且位于中空的筒状有源层6内。
本申请实施例中，栅极绝缘层7在中空的筒状有源层6内随形制备得到，栅极绝缘层7的纵截面也包含U型状。栅极8设置在栅极绝缘层7的两侧壁之间，即沿竖直方向的栅极8设置在纵截面呈U型状的栅极绝缘层7内。栅极8也沿竖直方向设置，能够缩小晶体管的尺寸。
可选地，栅极绝缘层7的材料包括氧化铪、氧化铝、铪铝氧、镧掺杂的氧化铪(HfLaO)中至少一种。
栅极8材料包括氧化铟锌、氧化铟锡、钨中至少一种。
本申请实施例中，栅极绝缘层7的材料中的氧化铪、氧化铝、铪铝氧和镧掺杂的氧化铪均为高介电常数材料，相对于二氧化硅材料，高介电常数材料能够维持驱动电流，减小漏电流密度，能够保持优良的漏电性能。栅极8材料中氧化铟锌、氧化铟锡和钨均为导电材料。
基于同一发明构思，本申请实施例提供了一种存储器，包括至少一个上述实施例提供的晶体管。
本申请实施例中，因该存储器包括晶体管，所以该存储器的有益效果包括上述实施例提供的晶体管的有益效果，在此不再赘述。
可选地，存储器包括多个堆叠设置的晶体管。
基于同一发明构思，本申请实施例提供了一种电子设备，包括上述实施例提供的存储器。
本申请实施例中，由于电子设备采用了前述各实施例提供的存储器，其原理和技术效果请参阅前述各实施例，在此不再赘述。
可选地，电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
应该说明的是，电子设备并不局限于上述几种，本领域技术人员可以根据实际的应用需求，在不同的设备中设置本申请上述实施例所提供的存储器，从而得到本申请实施例所提供的电子设备。
基于同一发明构思，本申请实施例提供了一种晶体管的制造方法，该晶体管的制造方法的流程示意图如图4所示，该方法包括如下步骤S1至S3：
S1：在衬底1的上方依次制造初始第一源/漏极21、初始第一介质层31、初始第二源/漏极41和初始第二介质层51；初始第一源/漏极21的材料的功函数与初始第二源/漏极41的材料的功函数不同。
本申请实施例中，图5为在衬底1的上方依次制造初始第一源/漏极21、初始第一介质层31、初始第二源/漏极41和初始第二介质层51后得到的膜层剖面示意图。如图5所示，初始第一源/漏极21和初始第二源/漏极41沿垂直方向层叠设置，能够尽可能减小晶体管的尺寸。
初始第一源/漏极21的材料的功函数与初始第二源/漏极41的材料的 功函数不同，意味着后续制造得到的第一源/漏极2的材料的功函数和第二源/漏极4的材料的功函数不同。第一源/漏极2的材料的功函数可以高于第二源/漏极4的材料的功函数，或者第一源/漏极2的材料的功函数可以低于第二源/漏极4的材料的功函数。在施加外部电场的情况下，较高功函数的材料与后续制造的有源层6接触，能够形成肖特基接触，产生耗尽层，能够抑制沟道漏电，从而提高晶体管的保持特性；较低功函数的材料与后续制造的有源层6接触，能够形成欧姆接触，无耗尽层，能够有利于抑制短沟道效应，进而有利于提高晶体管的漏电性能，从而有利于降低晶体管的自热效应，有利于提高晶体管的可靠性。
S2：对初始第二介质层51、初始第二源/漏极41、初始第一介质层31和部分或全部厚度的初始第一源/漏极21进行图案化，形成第二介质层5、第二源/漏极4、第一介质层3和第一源/漏极2，以及形成贯穿第二介质层5、第二源/漏极4、第一介质层3和部分或全部厚度的第一源/漏极2的孔；第一方向垂直于衬底1。
本申请实施例中，图6为对初始第二介质层51、初始第二源/漏极41、初始第一介质层31和部分或全部厚度的初始第一源/漏极21进行图案化，形成第二介质层5、第二源/漏极4、第一介质层3和第一源/漏极2，以及形成贯穿第二介质层5、第二源/漏极4、第一介质层3和部分或全部厚度的第一源/漏极2的孔后的膜层剖面示意图。
本申请中对第二介质层5、第二源/漏极4、第一介质层3和部分或全部厚度的第一源/漏极2进行图案化，包括光刻工艺和刻蚀工艺。在对第一源/漏极2进行刻蚀时，会刻蚀掉部分或全部厚度的第一源/漏极2，能够增大后续制造的有源层6与第一源/漏极2的接触面积，有利于增加后续制造的有源层6和第一源/漏极2的接触稳定性。
可选地，第一源/漏极2的材料和第二源/漏极4的材料中其中一个为金属氧化物材料，另一个为金属材料；金属氧化物材料的功函数小于有源层6材料的功函数；金属材料的功函数大于有源层6材料的功函数。
本申请实施例中，第一源/漏极2的材料可以为金属氧化物材料或者金属材料，相对应地，第二源/漏极4的材料可以为金属材料或者金属氧 化物材料。
金属氧化物材料的功函数小于后续制造的有源层6材料的功函数；金属材料的功函数大于后续制造的有源层6材料的功函数。具体地，金属氧化物导电材料的功函数不小于2.5eV且小于4.5eV；金属材料的功函数不小于4.5eV且不大于5.5eV。
可选地，第一源/漏极2和第二源/漏极4的其中之一与有源层6接触的界面101包含氧化铟锡、氧化铟锌、掺钨氧化铟中至少一种。
可选地，第一源/漏极2和第二源/漏极4的另一个与有源层6接触的界面101包含钛、钨、钌、钼中至少之一的金属或金属氮化物。
参考图1，本申请的界面101可以是第一源/漏极2和第二源/漏极4的其中之一的一部分。
本申请实施例中，第一源/漏极2和第二源/漏极4的其中之一与有源层6接触的界面101包含氧化铟锡、氧化铟锌、掺钨氧化铟中至少一种，氧化铟锡、氧化铟锌和掺钨氧化铟均属于低功函数氧化物材料(低功函数的意思是材料的功函数低于有源层6材料的功函数)。第一源/漏极2和第二源/漏极4的另一个与有源层6接触的界面101包含钛、钨、钌、钼中至少之一的金属或金属氮化物，钛、钨、钌和钼的金属或金属氮化物均属于高功函数金属材料(高功函数的意思是材料的功函数高于有源层6材料的功函数)，较高功函数的材料与有源层6接触，能够形成肖特基接触，产生耗尽层，能够抑制沟道漏电，从而提高晶体管的保持特性；较低功函数的材料与有源层6接触，能够形成欧姆接触，无耗尽层，能够有利于抑制短沟道效应，进而有利于提高晶体管的漏电性能，从而有利于降低晶体管的自热效应，有利于提高晶体管的可靠性。
具体地，金属氧化物材料包括氧化铟锡、氧化铟锌和掺钨氧化铟中至少一种；金属材料包括氮化钛、钨、钌和钼中至少一种。
本申请实施例中，金属氧化物导电材料中氧化铟锡、氧化铟锌和掺钨氧化铟均属于低功函数氧化物材料。金属材料中氮化钛、钨、钌和钼均属于高功函数金属材料。
S3：在孔9内和第二介质层5远离衬底1的上方，制造随形的初始有 源层61。
本实施例中，图7为在孔9内和第二介质层5远离衬底1的上方，制造随形的初始有源层61后的膜层剖面示意图。参考图7，初始有源层61包括位于孔9内的第一竖直部分和位于第二介质层5远离衬底1上方的第一水平部分。
初始有源层61的底面比第一源/漏极2的上表面更靠近衬底1，由此能够增大后续制造的有源层6与第一源/漏极2的接触面积，避免在施加外部电场的情况下，后续制造的有源层61与第一源/漏极2接触不良的现象。
而且，在第一源/漏极2和第二源/漏极4之间的后续制造的有源层6在施加外部电场的情况下能够形成沟道。作为沟道的部分的后续制造的有源层6是沿竖直方向设置的，能够进一步地缩小晶体管的尺寸。
可选地，在上述步骤S3之后还包括：
在位于孔9内的初始有源层61的内表面和位于第二介质层5远离衬底1的上方的有源层61的上表面依次随形制造初始栅极绝缘层71和初始栅极81。
本实施例中，图8为在位于孔9内的初始有源层61的内表面和位于第二介质层5远离衬底1的上方的有源层61的上表面依次随形制造初始栅极绝缘层71和初始栅极81后的膜层剖面示意图。
参考图8，初始有源层61包括位于孔9内的第一竖直部分和位于第二介质层5远离衬底1上方的第一水平部分。第一竖直部分沿第一方向延伸，第一水平部分沿平行于衬底1的方向延伸。
参考图8，本申请的初始栅极绝缘层71包括第二竖直部分和第二水平部分，第二竖直部分为位于初始有源层61的第一竖直部分远离衬底1上方的部分，第二水平部分为位于初始有源层61的第一水平部分远离衬底1上方的部分。
再参考图8，初始栅极81包括第三竖直部分和第三水平部分，第三竖直部分为位于初始栅极绝缘层71的第二竖直部分的两侧壁之间的部分，第三水平部分为位于初始栅极绝缘层71的第二水平部分远离衬底1的上 方的部分。后续制造得到的栅极8也沿竖直方向设置，能够缩小晶体管的尺寸。
可选地，在上述步骤中在位于孔9内的初始有源层61的内表面和位于第二介质层5远离衬底1的上方的有源层61的上表面依次随形制造初始栅极绝缘层71和初始栅极81之后，还包括：
对位于第二介质层5远离所述衬底1上方的初始有源层61、初始栅极绝缘层71和初始栅极81进行图案化，得到有源层6、栅极绝缘层7和栅极8。
本实施例中，图1为对位于第二介质层5远离所述衬底1上方的初始有源层61、初始栅极绝缘层71和初始栅极81进行图案化，得到有源层6、栅极绝缘层7和栅极8后的膜层剖面示意图。
参考图1，去除部分位于第二介质层5远离所述衬底1上方的初始有源层61、初始栅极绝缘层71和初始栅极81，即去除初始有源层61的第一水平部分、初始栅极绝缘层71的第二水平部分和初始栅极81的第三水平部分的两端，由此能够避免与其他晶体管接触后出现短路的情况。
可选地，金属氧化物半导体层的金属材料选自铟、镓、锌、锡、钛、铝中的至少一种。
具体地，有源层6的材料包括氧化铟镓锌、氧化铟铝锌、氧化铟锡和掺钨氧化铟中至少一种。
本申请实施例中，有源层6的材料包括氧化铟镓锌、氧化铟铝锌、氧化铟锡和掺钨氧化铟中一种或者多种组合叠层设置。可以根据实际情况具体选择。
可选地，栅极绝缘层7的材料包括氧化铪、氧化铝、铪铝氧和镧掺杂的氧化铪中至少一种。栅极8材料包括氧化铟锌、氧化铟锡和钨中至少一种。
本实施例中，栅极绝缘层7的材料中的氧化铪、氧化铝、铪铝氧和镧掺杂的氧化铪均为高介电常数材料，相对于二氧化硅材料，高介电常数材料能够维持驱动电流，减小漏电流密度，能够保持优良的漏电性能。栅极 8材料中氧化铟锌、氧化铟锡和钨均为导电材料。
应用本申请实施例，至少能够实现如下有益效果：
1.本申请实施例中作为沟道的部分有源层是沿竖直方向设置的，能够进一步地缩小晶体管的尺寸。
2.本申请实施例中第一源/漏极的材料的功函数与第二源/漏极的材料的功函数不同，意味着第一源/漏极的材料的功函数可以高于第二源/漏极的材料的功函数，或者第一源/漏极的材料的功函数可以低于第二源/漏极的材料的功函数。在施加外部电场的情况下，较高功函数的材料与有源层接触，能够形成肖特基接触，产生耗尽层，能够抑制沟道漏电，从而提高晶体管的保持特性；较低功函数的材料与有源层接触，能够形成欧姆接触，无耗尽层，能够有利于抑制短沟道效应，进而有利于提高晶体管的漏电性能，从而有利于降低晶体管的自热效应，有利于提高晶体管的可靠性。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
在本申请的描述中，词语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方向或位置关系，为基于附图所示的示例性的方向或位置关系，是为了便于描述或简化描述本申请的实施例，而不是指示或暗示所指的装置或部件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术 语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
应该理解的是，虽然附图的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤的实施顺序并不受限于箭头所指示的顺序。除非本文中有明确的说明，否则在本申请实施例的一些实施场景中，各流程中的步骤可以按照需求以其他的顺序执行。而且，各流程图中的部分或全部步骤基于实际的实施场景，可以包括多个子步骤或者多个阶段。这些子步骤或者阶段中的部分或全部可以在同一时刻被执行，也可以在不同的时刻被执行在执行时刻不同的场景下，这些子步骤或者阶段的执行顺序可以根据需求灵活配置，本申请实施例对此不限制。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请的方案技术构思的前提下，采用基于本申请技术思想的其他类似实施手段，同样属于本申请实施例的保护范畴。

Claims (18)

  1. 一种晶体管，其特征在于，所述晶体管为垂直晶体管，包括：设置于衬底上方的层叠的第一源/漏极、第一介质层、第二源/漏极和第二介质层，以及沿垂直于所述衬底的第一方向延伸的有源层；
    所述有源层穿设于所述第二介质层、所述第二源/漏极、所述第一介质层，穿设于部分或全部的所述第一源/漏极，所述有源层与所述第一源/漏极和第二源/漏极接触；
    所述第一源/漏极的材料的功函数与所述第二源/漏极的材料的功函数不同；
    所述有源层为金属氧化物半导体层。
  2. 根据权利要求1所述的晶体管，其特征在于，所述第一源/漏极的材料和所述第二源/漏极的材料中其中一个为金属氧化物材料，另一个为金属材料。
  3. 根据权利要求2所述的晶体管，其特征在于，所述金属氧化物材料的功函数小于所述有源层的材料的功函数，所述金属材料的功函数大于所述有源层的材料的功函数。
  4. 根据权利要求1所述的晶体管，其特征在于，所述第一源/漏极和第二源/漏极的其中之一与所述有源层之间为非肖特基接触，所述第一源/漏极和第二源/漏极的另一个与所述有源层之间为肖特基接触。
  5. 根据权利要求4所述的晶体管，其特征在于，所述金属氧化物半导体层的金属材料选自铟、镓、锌、锡、钛、铝中的至少一种。
  6. 根据权利要求5所述的晶体管，其特征在于，所述第一源/漏极和第 二源/漏极的其中之一与所述有源层接触的界面包含氧化铟锡、氧化铟锌、掺钨氧化铟中的至少一种。
  7. 根据权利要求6所述的晶体管，其特征在于，所述第一源/漏极和第二源/漏极的另一个与所述有源层接触的界面包含钛、钨、钌、钼中至少之一。
  8. 根据权利要求5所述的晶体管，其特征在于，所述第一源/漏极和第二源/漏极的其中之一与所述有源层接触的界面包含氧化铟锡或氧化铟锌，另一与所述有源层接触的界面包含氮化钛。
  9. 根据权利要求6所述的晶体管，其特征在于，所述第一源/漏极和所述第二源/漏极至少之一包含主体结构，所述主体结构和所述有源层之间包含与所述有源层接触的所述界面。
  10. 根据权利要求9所述的晶体管，其特征在于，所述主体结构和所述界面包含的材料为相同的材料，均为氧化铟锡。
  11. 根据权利要求10所述的晶体管，其特征在于，所述主体结构和所述界面包含的材料为不相同的材料，所述主体结构的金属材料选自钨、铜、铝、银中至少一种。
  12. 根据权利要求6所述的晶体管，其特征在于，所述有源层为中空的筒状，所述有源层的外侧表面与所述第一源/漏极和第二源/漏极耦合连接，所述有源层中靠近所述第一源/漏极或所述第二源/漏极接触的区域的平均氧浓度与远离所述第一源/漏极或所述第二源/漏极的区域的平均氧浓度相同。
  13. 根据权利要求7所述的晶体管，其特征在于，还包括沿所述第一方向延伸设置的栅极绝缘层和栅极，所述栅极绝缘层和栅极依次随形设置于所述有源层远离衬底的一侧且位于所述中空的筒状有源层内。
  14. 一种存储器，其特征在于，包括至少一个如权利要求1-13中任一所述的晶体管。
  15. 一种电子设备，其特征在于，包括权利要求14所述的存储器。
  16. 一种晶体管的制造方法，其特征在于，包括：
    在衬底的上方依次制造初始第一源/漏极、初始第一介质层、初始第二源/漏极和初始第二介质层；所述初始第一源/漏极的材料的功函数与所述初始第二源/漏极的材料的功函数不同；
    对所述初始第二介质层、所述初始第二源/漏极、所述初始第一介质层和部分或全部厚度的所述初始第一源/漏极进行图案化，形成第二介质层、第二源/漏极、第一介质层和第一源/漏极，以及形成贯穿所述第二介质层、第二源/漏极、第一介质层和部分或全部厚度的第一源/漏极的孔；所述第一方向垂直于所述衬底；
    在所述孔内和所述第二介质层远离所述衬底的上方，制造随形的初始有源层。
  17. 根据权利要求16所述的制造方法，其特征在于，在所述孔内和所述第二介质层远离所述衬底的上方，制造随形的初始有源层之后，还包括：
    在位于所述孔内的所述初始有源层的内表面和位于所述第二介质层远离所述衬底上方的所述初始有源层的上表面依次随形制造初始栅极绝缘层和初始栅极。
  18. 根据权利要求17所述的制造方法，其特征在于，在位于所述孔内 的所述初始有源层的内表面和位于所述第二介质层远离所述衬底上方的所述初始有源层的表面随形制造初始栅极绝缘层和初始栅极之后，还包括：
    对位于所述第二介质层远离所述衬底上方的所述初始有源层、所述初始栅极绝缘层和所述初始栅极进行图案化，得到有源层、栅极绝缘层和栅极。
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