WO2024228284A1 - 配線基板、電子モジュール、及び配線基板の製造方法 - Google Patents

配線基板、電子モジュール、及び配線基板の製造方法 Download PDF

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Publication number
WO2024228284A1
WO2024228284A1 PCT/JP2024/004285 JP2024004285W WO2024228284A1 WO 2024228284 A1 WO2024228284 A1 WO 2024228284A1 JP 2024004285 W JP2024004285 W JP 2024004285W WO 2024228284 A1 WO2024228284 A1 WO 2024228284A1
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WIPO (PCT)
Prior art keywords
wiring board
conductor
insulating film
conductor pattern
board according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/004285
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English (en)
French (fr)
Japanese (ja)
Inventor
英樹 上田
伸郎 池本
知大 古村
直貴 南谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
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Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2025518099A priority Critical patent/JPWO2024228284A1/ja
Priority to CN202480020692.8A priority patent/CN120981913A/zh
Publication of WO2024228284A1 publication Critical patent/WO2024228284A1/ja
Priority to US19/370,813 priority patent/US20260053022A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0141—Liquid crystal polymer [LCP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/032—Materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/0939—Curved pads, e.g. semi-circular or elliptical pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/072—Electroless plating, e.g. finish plating or initial plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0723—Electroplating, e.g. finish plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a wiring board, an electronic module, and a method for manufacturing a wiring board.
  • Patent Documents 1, 2, and 3 Various wiring boards for mounting electronic components are known (Patent Documents 1, 2, and 3).
  • the wiring boards disclosed in Patent Documents 1 and 2 include an inner layer conductor pattern on the board, and a laminated layer (insulating layer) that covers the inner layer conductor pattern.
  • An opening is provided in the laminated layer, and a part of the surface of the inner layer conductor pattern is exposed at the bottom of the opening.
  • the surface of the inner layer conductor pattern exposed in the opening is covered with a surface treatment portion (surface layer).
  • the part of the inner layer conductor pattern exposed in the opening is used as a terminal for mounting an electronic component.
  • the surface treatment portion functions as a connecting conductor for connecting the solder bumps of the electronic component and the inner layer conductor pattern.
  • the inner layer conductor pattern disclosed in Patent Document 1 uses copper foil, and the surface treatment part uses solder, alloy, gold, silver, nickel, etc.
  • the inner layer conductor pattern disclosed in Patent Document 2 uses a metal mainly composed of copper, and the surface layer uses Ni-Au plating or Sn (solder) plating. The surface layer protects the inner layer conductor pattern underneath.
  • connection conductor is filled into a through hole facing the first resin layer.
  • the connection conductor is connected to an inner layer conductor pattern on the lower layer.
  • a second resin layer is disposed on top of the first resin layer, and an opening is provided in the second resin layer to expose the connection conductor.
  • the connection conductor exposed in the opening is used as a terminal for mounting an electronic component.
  • a melting point changing bonding material is used for the connection conductor.
  • An object of the present invention is to provide a wiring board in which cracks are unlikely to occur at the interface between the conductor pattern and the connecting conductor.
  • Another object of the present invention is to provide an electronic module using this wiring board.
  • Yet another object of the present invention is to provide a method for manufacturing this wiring board.
  • a first insulating film having a through hole penetrating in a thickness direction; a first conductor pattern disposed on a first surface that is one surface of the first insulating film and closing an opening of the through hole on the first surface side; a first connection conductor disposed in the through hole, connected to the first conductor pattern, and having a dimension in a thickness direction smaller than a dimension in a thickness direction of the first insulating film; There is provided a wiring board in which the metal element having the maximum content in the first conductor pattern is the same as the metal element having the maximum content in the first connecting conductor.
  • the solder bumps are provided on an electronic module which are connected to the connecting conductors.
  • a first insulating film is prepared, the first insulating film having a first conductor pattern formed on a first surface, the first insulating film being one surface of the first insulating film; forming a through hole reaching the first conductor pattern from a surface of the first insulating film opposite to the first surface; a method for manufacturing a wiring board, the method comprising forming a first connection conductor in the through hole by a plating method using the first conductor pattern as a seed, the metal element having the maximum content in the first conductor pattern is the same as the metal element having the maximum content in the first connecting conductor, There is provided a method for manufacturing a wiring board, in which the dimension in the thickness direction of the first connection conductor is smaller than the dimension in the thickness direction of the first insulating film on the first conductor pattern.
  • the discontinuity of the material at the interface between the two is mitigated. This makes it possible to suppress the occurrence of cracks and peeling caused by stress concentration at the interface between the conductor pattern and the connecting conductor.
  • FIG. 1 is a cross-sectional view of a wiring board according to a first embodiment.
  • 2A and 2B are cross-sectional views of the wiring board according to the first embodiment during the manufacturing process.
  • FIG. 3 is a cross-sectional view of a wiring board according to the second embodiment.
  • FIG. 4 is a cross-sectional view of a wiring board for explaining the excellent effects of the second embodiment.
  • FIG. 5 is a cross-sectional view of an electronic module according to a third embodiment.
  • FIG. 6 is a cross-sectional view of a wiring board according to a fourth embodiment.
  • FIG. 7 is a cross-sectional view of a wiring board according to a modified example of the fourth embodiment.
  • FIG. 8 is a cross-sectional view of a wiring board according to another modified example of the fourth embodiment.
  • FIG. 9 is a cross-sectional view of a wiring board according to still another modified example of the fourth embodiment.
  • FIG. 10 is a cross-sectional view of a wiring board according to the fifth embodiment.
  • FIG. 11 is a cross-sectional view of a wiring board according to a modification of the fifth embodiment.
  • FIGS. 1 to 2B A wiring board according to a first embodiment will be described with reference to FIGS. 1 to 2B.
  • the wiring board 50 according to the first embodiment includes a first insulating film 21 having a through hole 21A formed therein, a first conductor pattern 20, a first connecting conductor 22 disposed in the through hole 21A, and a surface treatment layer 23 disposed on the surface of the first connecting conductor 22.
  • a plurality of through holes 21A are provided, but FIG. 1 shows only one through hole 21A.
  • the first conductor pattern 20 is disposed on the first surface 21B, which is one surface of the first insulating film 21.
  • the first conductor pattern 20 covers the opening of the through hole 21A on the first surface 21B side.
  • the surface of the various components facing in the opposite direction to the first surface 21B will be referred to as the upper surface.
  • the direction perpendicular to the first surface 21B may be referred to as the thickness direction.
  • through hole 21A The side of through hole 21A is inclined so that the area of the planar cross section (cross section parallel to first surface 21B) of through hole 21A increases the further upward from first conductor pattern 20.
  • through hole 21A has an inverted tapered shape that narrows downward.
  • the first connecting conductor 22 arranged in the through hole 21A is in contact with the first conductor pattern 20.
  • the first connecting conductor 22 and the first conductor pattern 20 are formed of the same metal, for example, copper.
  • the surface treatment layer 23 formed on the upper surface of the first connecting conductor 22 contains at least one material selected from the group consisting of Ni, Au, solder, and flux.
  • the first surface 21B is used as a reference height
  • the height h2 to the upper surface of the first connecting conductor 22 and the height h3 to the upper surface of the surface treatment layer 23 are lower than the height h1 to the upper surface of the first insulating film 21. Therefore, a recess 51 appears on the upper surface of the wiring board 50.
  • the surface treatment layer 23 is exposed at the bottom of this recess 51.
  • Figures 2A and 2B are cross-sectional views of the wiring board 50 according to the second embodiment at an intermediate stage in the manufacturing process.
  • the conductor foil of the resin sheet with conductor foil is patterned to form a laminated structure having a first insulating film 21 and a first conductor pattern 20.
  • copper foil is used as the conductor foil
  • a sheet mainly made of thermoplastic polyimide (PI) is used as the resin sheet.
  • PI thermoplastic polyimide
  • PEEK polyetheretherketone
  • PEI polyetherimide
  • PPS polyphenylene sulfide
  • LCP liquid crystal polymer
  • through holes 21A are formed in the first insulating film 21 from the surface opposite to the surface on which the first conductor pattern 20 is arranged, and reach the first conductor pattern 20.
  • a laser processing method using, for example, a carbon dioxide laser can be used to form the through holes 21A. This laser processing is performed under conditions that cause little damage to the first conductor pattern 20.
  • the first conductor pattern 20 is used as a seed to perform copper plating on the first conductor pattern 20 exposed in the through hole 21A, thereby forming the first connecting conductor 22.
  • This plating is performed using an electroless plating method or an electrolytic plating method.
  • the resin sheet constituting the first insulating film 21 is hardened by applying pressure and heating.
  • the wiring board 50 according to the first embodiment is used, for example, as the top layer of a mounting board for mounting electronic components having solder bumps or the like.
  • the solder bumps of the electronic components are connected to the first connecting conductors 22 via the surface treatment layer 23, thereby mounting the electronic components on the wiring board 50.
  • the surface treatment layer 23 has the function of protecting the surface of the first connecting conductors 22 and the function of improving mountability when mounting the electronic components.
  • the interface between the first connecting conductor 22 and the first conductor pattern 20 is discontinuous in shape, stress is likely to concentrate at the interface between the first connecting conductor 22 and the first conductor pattern 20 due to the difference in thermal expansion coefficient between the wiring board 50 and the electronic component.
  • stress is likely to concentrate at the interface between the first connecting conductor 22 and the first conductor pattern 20 due to the difference in thermal expansion coefficient between the wiring board 50 and the electronic component.
  • discontinuity in material also occurs at the interface between the two. If stress concentrates at the interface where discontinuity in material occurs, cracks and peeling are likely to occur.
  • the first conductor pattern 20 and the first connecting conductor 22 are both made of copper, so there is no material discontinuity at the interface between them. This increases the mechanical strength of the interface between the first conductor pattern 20 and the first connecting conductor 22. As a result, cracks, peeling, and the like are less likely to occur at the interface between the two.
  • solder paste is used for the first connecting conductor 22
  • the metal constituting the first conductor pattern 20 will dissolve into the solder (sometimes called "solder erosion").
  • the first connecting conductor 22 and the first conductor pattern 20 are made of the same metal, so solder erosion does not occur.
  • a recess 51 occurs in the area where the first connecting conductor 22 is arranged.
  • the first connecting conductor 22 is filled into a portion of the lower side of the through hole 21A, so that the center positions of the through hole 21A and the first connecting conductor 22 in a plan view are approximately the same.
  • the solder bump of the electronic component is positioned in the recess 51 that occurs at the position of the through hole 21A.
  • the first connecting conductor 22 and the solder bump of the electronic component can be positioned with high precision.
  • the height h2 of the first connecting conductor 22 is equal to or greater than the thickness of the first conductor pattern 20.
  • the height h2 of the first connecting conductor 22 is equal to or less than 90% of the height h1 of the first insulating film 21. It is preferable that the total height h2 of the first connecting conductor 22 and the surface treatment layer 23 is less than the height h1 of the first insulating film 21.
  • first conductor pattern 20 and the first connecting conductor 22 copper is used for the first conductor pattern 20 and the first connecting conductor 22, but other metals may be used for the first conductor pattern 20 and the first connecting conductor 22. For example, silver, gold, etc. may be used.
  • the first conductor pattern 20 and the first connecting conductor 22 may be made of an alloy mainly composed of copper, silver, or gold.
  • an alloy is used for the first conductor pattern 20 and the first connecting conductor 22, it is preferable that the constituent elements of the alloy are the same, and it is even more preferable that the content ratio of the constituent elements is the same.
  • the metal element with the maximum content in the first conductor pattern 20 is the same as the metal element with the maximum content in the first connecting conductor 22.
  • the first connecting conductor 22 is formed using a plating method, but the first connecting conductor 22 may be formed using other methods.
  • a conductive paste may be placed in the through hole 21A, and then the conductive paste may be hardened to form the first connecting conductor 22.
  • binder resin remains in the first connecting conductor 22. In this case, it is preferable to use the same metal for the conductive particles contained in the first connecting conductor 22 and the first conductor pattern 20.
  • the first connection conductor 22 can be filled in the lower part of the through hole 21A with good reproducibility even if the size of the through hole 21A in a plan view is made small, compared to the case where the conductive paste is used. Whether to use the plating method or the conductive paste may be determined based on the size of the through hole 21A, etc. In addition, when the plating method is used, the first connection conductor 22 made of metal that does not contain binder resin, etc. can be formed. When the wiring board 50 is used as the uppermost layer of the mounting board, the thickness of the first insulating film 21 is at most about 40 ⁇ m, so that the plating method does not significantly increase the cost compared to the method using the conductive paste.
  • FIG. 3 is a cross-sectional view of a wiring board 50 according to the second embodiment.
  • the wiring board 50 according to the second embodiment includes a base substrate 10, a first conductor pattern 20, a first insulating film 21, a first connecting conductor 22, and a surface treatment layer 23.
  • the configurations of the first conductor pattern 20, the first insulating film 21, the first connecting conductor 22, and the surface treatment layer 23 are the same as those of the wiring board 50 according to the first embodiment (FIG. 1).
  • the first insulating film 21 is disposed on the upper surface of the base substrate 10 with the first surface 21B of the first insulating film 21 facing the base substrate 10.
  • the first conductor pattern 20 is disposed between the base substrate 10 and the first insulating film 21.
  • the wiring board 50 according to the second embodiment is used, for example, as a mounting substrate for mounting electronic components equipped with solder bumps or the like.
  • the first insulating film 21 is bonded to the base substrate 10 with the first surface 21B of the first insulating film 21 before heat treatment, on which the first conductor pattern 20 and the first connecting conductor 22 are provided, facing the upper surface of the base substrate 10, such as a resin sheet.
  • the laminate including the base substrate 10, the first conductor pattern 20, and the first insulating film 21 is heated and pressurized to form an integrated laminate.
  • the surface treatment layer 23 may be formed after this heat treatment.
  • the mechanical strength of the interface between the first conductor pattern 20 and the first connecting conductor 22 is increased, making the interface less susceptible to cracks, peeling, and the like.
  • the solder bumps of the electronic component are positioned in the depressions 51 generated at the positions of the through holes 21A.
  • the first connecting conductor 22 and the solder bumps of the electronic component can be positioned with high precision.
  • FIG. 4 is a cross-sectional view of wiring board 50 for explaining another excellent effect of the second embodiment.
  • solder paste 30 may be filled into recesses 51 formed on the surface of wiring board 50.
  • the side surfaces of through hole 21A are inclined so that the area of the planar cross section of through hole 21A increases with increasing distance from first conductor pattern 20 upward. This provides an excellent effect that air voids are less likely to occur when solder paste 30 is filled into recess 51.
  • the electronic module according to the third embodiment includes the wiring board 50 according to the second embodiment (Fig. 3) and electronic components mounted on this wiring board 50.
  • FIG. 5 is a cross-sectional view of an electronic module according to a third embodiment.
  • a wiring board 50 is provided with a plurality of first connection conductors 22 and a surface treatment layer 23.
  • Each of a plurality of terminals 41 of an electronic component 40 is connected to a first conductor pattern 20 via a solder bump 45, the surface treatment layer 23, and the first connection conductor 22.
  • a portion of each of the plurality of solder bumps 45 on the wiring board 50 side is recessed into a recess 51 formed on the surface of the wiring board 50.
  • the third embodiment also has the excellent effect of making it difficult for cracks or peeling to occur at the interface between the first conductor pattern 20 and the first connecting conductor 22. Furthermore, because the multiple solder bumps 45 each penetrate into the recesses 51, the excellent effect of increasing the shear strength is obtained.
  • FIG. 6 is a cross-sectional view of a wiring board 50 according to the fourth embodiment.
  • the base substrate 10 includes a second insulating film 11, a second conductor pattern 12, and a second connecting conductor 13.
  • the second conductor pattern 12 is disposed on the lower surface of the second insulating film 11.
  • a via hole penetrating the second insulating film 11 in the thickness direction is provided.
  • the second connecting conductor 13 is filled in the via hole.
  • the second connecting conductor 13 connects the first conductor pattern 20 and the second conductor pattern 12.
  • the second connecting conductor 13 is formed of the same conductive material as the second conductor pattern 12, for example, copper.
  • the second insulating film 11 and the first insulating film 21 may be formed of the same insulating material or different insulating materials.
  • base substrate 10 is fabricated in the same manner as in the manufacturing method of wiring substrate 50 according to the first embodiment described with reference to Figures 2A and 2B.
  • step of filling second connection conductor 13 plating is performed until its surface becomes substantially flush with the surface of second insulating film 11. At this stage, heat treatment has not yet been performed.
  • the surface treatment layer 23 is preferably formed after the heat treatment.
  • the advantageous effects of the fourth embodiment will be described.
  • the fourth embodiment similarly to the second embodiment, it is possible to suppress the occurrence of cracks and peeling at the interface between the first conductor pattern 20 and the first connecting conductor 22. Furthermore, it is possible to suppress the occurrence of cracks and peeling at the interface between the second conductor pattern 12 and the second connecting conductor 13.
  • the fourth embodiment a modified example of the fourth embodiment will be described.
  • copper is used for the second conductor pattern 12 and the second connecting conductor 13, but other metals of the same type may be used for the second conductor pattern 12 and the second connecting conductor 13. For example, silver, gold, etc. may be used.
  • the second conductor pattern 12 and the second connecting conductor 13 may be made of an alloy mainly composed of copper, silver, or gold.
  • an alloy is used for the second conductor pattern 12 and the second connecting conductor 13, it is preferable that the constituent elements of the alloy are the same, and it is even more preferable that the content ratio of the constituent elements is the same.
  • the metal element with the maximum content in the second conductor pattern 12 is the same as the metal element with the maximum content in the second connecting conductor 13.
  • FIG. Fig. 7 is a cross-sectional view of a wiring board 50 according to a modification of the fourth embodiment.
  • the base substrate 10 has a single-layer wiring structure, but in the modification shown in Fig. 7, the base substrate 10 has a multi-layer wiring structure.
  • Each layer of the multi-layer wiring structure includes a second insulating film 11, a second conductor pattern 12, and a second connecting conductor 13.
  • the base substrate 10 may have a multi-layer wiring structure.
  • FIG. Fig. 8 is a cross-sectional view of a wiring board 50 according to this modification.
  • the second connecting conductor 13 is formed by plating using the same conductive material as the second conductor pattern 12.
  • the second connecting conductor 13 is formed by hardening a conductive paste.
  • the conductive paste may be a copper paste, a silver paste, a gold paste, a solder paste, or the like.
  • the electrical connectivity at the interface between the second connecting conductor 13 and the second conductor pattern 12 that is bonded thereon by applying pressure and heat can be improved compared to when the second connecting conductor 13 is formed by plating as in the fourth embodiment.
  • FIG. Fig. 9 is a cross-sectional view of a wiring board 50 according to this modification.
  • the second connection conductor 13 is composed of a first portion 13A on the side (lower side) farther from the first insulating film 21 and a second portion 13B on the side (upper side) closer to the first insulating film 21.
  • the first portion 13A is made of the same conductive material as the second conductor pattern 12, as in the modification of the fourth embodiment shown in Fig. 7, and the second portion 13B is made of a conductive material obtained by hardening a conductive paste, as in the modification shown in Fig. 8.
  • FIG. 10 is a cross-sectional view of a wiring board 50 according to the fifth embodiment.
  • the upper surface of the first connecting conductor 22 is almost flat.
  • the upper surface of the first connecting conductor 22 has a concave shape curved downward. That is, the center of the upper surface is lower than the outer periphery.
  • the height h2 to the highest point of the upper surface of the first connecting conductor 22 is lower than the height h1 to the upper surface of the first insulating film 21.
  • Such a shape of the upper surface of the first connecting conductor 22 is obtained by adjusting the plating conditions.
  • the surface treatment layer 23 covers the curved upper surface of the first connecting conductor 22 with an almost uniform thickness.
  • the fifth embodiment also has the excellent effect of preventing cracks and peeling from occurring at the interface between the first conductor pattern 20 and the first connecting conductor 22. Furthermore, in the fifth embodiment, when mounting an electronic component with solder balls on the wiring board 50, the solder balls provided on the electronic component are positioned at the lowest position on the upper surface of the first connecting conductor 22, so that the position of the electronic component is stabilized, and the excellent effect of improving the positional accuracy during mounting is obtained.
  • FIG. 11 is a cross-sectional view of a wiring board 50 according to a modification of the fifth embodiment.
  • the upper surface of the first connecting conductor 22 is curved downward, but in the modification shown in FIG. 11, the upper surface of the first connecting conductor 22 has a convex shape curved upward. That is, when the upper surface of the first conductor pattern 20 is used as a reference for height, the height of the central part of the first connecting conductor 22 is higher than the height of the outer periphery.
  • the height h2 to the highest position of the upper surface of the first connecting conductor 22 is lower than the height h1 to the upper surface of the first insulating film 21.
  • Such a shape can be realized by adjusting plating conditions, surface treatment, etc.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
PCT/JP2024/004285 2023-05-01 2024-02-08 配線基板、電子モジュール、及び配線基板の製造方法 Ceased WO2024228284A1 (ja)

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JP2025518099A JPWO2024228284A1 (https=) 2023-05-01 2024-02-08
CN202480020692.8A CN120981913A (zh) 2023-05-01 2024-02-08 布线基板、电子模块以及布线基板的制造方法
US19/370,813 US20260053022A1 (en) 2023-05-01 2025-10-28 Wiring board, electronic module, and manufacturing method for wiring board

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JP2023075390 2023-05-01

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001257453A (ja) * 2000-03-09 2001-09-21 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP2003133711A (ja) * 2001-10-23 2003-05-09 Matsushita Electric Ind Co Ltd プリント配線板とその製造方法および電子部品の実装方法
WO2009133886A1 (ja) * 2008-04-28 2009-11-05 日本電気株式会社 多層配線基板、及びその製造方法
JP2013211479A (ja) * 2012-03-30 2013-10-10 Fujikura Ltd 多層配線基板
JP2017107934A (ja) * 2015-12-08 2017-06-15 富士通株式会社 回路基板、電子機器、及び回路基板の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7253946B2 (ja) * 2019-03-20 2023-04-07 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
US11688693B2 (en) * 2019-10-29 2023-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and method of manufacture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001257453A (ja) * 2000-03-09 2001-09-21 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP2003133711A (ja) * 2001-10-23 2003-05-09 Matsushita Electric Ind Co Ltd プリント配線板とその製造方法および電子部品の実装方法
WO2009133886A1 (ja) * 2008-04-28 2009-11-05 日本電気株式会社 多層配線基板、及びその製造方法
JP2013211479A (ja) * 2012-03-30 2013-10-10 Fujikura Ltd 多層配線基板
JP2017107934A (ja) * 2015-12-08 2017-06-15 富士通株式会社 回路基板、電子機器、及び回路基板の製造方法

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