Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
  • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

Definitions

• the present invention relates to a memory device using semiconductor elements.
• LSI Large Scale Integration
• the channel In a normal planar MOS transistor, the channel extends horizontally along the upper surface of the semiconductor substrate. In contrast, the channel of an SGT extends perpendicular to the upper surface of the semiconductor substrate (see, for example, Patent Document 1 and Non-Patent Document 1). For this reason, SGTs allow for higher density semiconductor devices compared to planar MOS transistors.
• this SGT As a selection transistor, it is possible to achieve high integration of DRAM (Dynamic Random Access Memory, see Non-Patent Document 2) connected to a capacitor, PCM (Phase Change Memory, see Non-Patent Document 3) connected to a resistive variable element, RRAM (Resistive Random Access Memory, see Non-Patent Document 4), and MRAM (Magneto-resistive Random Access Memory, see Non-Patent Document 5) that changes resistance by changing the direction of magnetic spins using electric current.
• DRAM Dynamic Random Access Memory
• PCM Phase Change Memory
• RRAM Resistive Random Access Memory
• MRAM Magnetic-resistive Random Access Memory
• DRAM memory cells that do not have a capacitor and are composed of a single MOS transistor. For example, holes and electrons generated in the channel by the impact ionization phenomenon caused by the source-drain current of an N-channel MOS transistor are retained in the channel as some or all of the holes, and logical memory data "1" is written. Then, the holes are removed from the channel and logical memory data "0" is written.
• the issues with this memory cell are how to improve the decrease in operating margin caused by floating body channel voltage fluctuations, and how to improve the decrease in data retention characteristics caused by the removal of some of the holes, which are the signal charges stored in the channel.
• Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in the SOI layer (see, for example, Patent Documents 2 and 3, and Non-Patent Document 11).
• DFM dynamic flash memory
• one memory cell is composed of two gate electrodes without a capacitor (see Non-Patent Document 12).
• the carrier concentration in the floating body is changed by manipulating the voltage of the four electrodes, creating a conductive or non-conductive state to perform memory operation.
• these memories have the problem that the volume of the floating body becomes smaller as the memory size becomes smaller, resulting in a smaller margin between "1" and "0".
• the object of the present invention is to provide a dynamic flash memory device with an expanded operating margin and high density.
• a memory device using a semiconductor element comprises: a first semiconductor region; a first impurity region on the first semiconductor region; a second semiconductor region extending vertically in contact with the first impurity region; a first gate insulating layer covering a portion of the second semiconductor region; a first gate conductor layer in contact with the first gate insulating layer; a first insulating layer formed in contact with the first gate conductor layer and the first gate insulating layer; a third semiconductor region in contact with the second semiconductor region and having a concave vertical cross section; a second gate insulating layer having a concave vertical cross section formed along at least the concave portion of the third semiconductor region; a second gate conductor layer formed inside the recess of the second gate insulating layer; a second impurity region and a third impurity region formed so as to be in contact with an upper surface of a protruding portion of the recess of the third semiconductor region, It is characterized by
• the second invention is the first invention, characterized in that the contact surface between the third semiconductor region and the second impurity region, or the contact surface between the third semiconductor region and the third impurity region, is located higher than the bottom of the second gate insulating layer.
• the third invention is the first invention, characterized in that in a horizontal cross section taken at a right angle to the direction in which the second semiconductor region extends, the horizontal cross-sectional area of the second semiconductor region is larger than the horizontal cross-sectional area of the second gate conductor layer.
• the fourth invention is the first invention, characterized in that the majority carriers in the first impurity region are different from the majority carriers in the first semiconductor region.
• the fifth invention is the first invention, characterized in that the majority carriers in the second semiconductor region are the same as the majority carriers in the first semiconductor region.
• the sixth invention is the first invention, characterized in that the majority carriers in the second impurity region and the third impurity region are the same as the majority carriers in the first impurity region.
• the seventh invention is the first invention, characterized in that the vertical distance from the bottom of the third semiconductor region to the top of the first impurity region is shorter than the vertical distance from the bottom of the third semiconductor region to the bottom of the first gate conductor layer.
• the eighth invention is the first invention, characterized in that the first impurity region is shared by a plurality of adjacent memory cells.
• the ninth invention is the first invention described above, characterized in that the threshold voltage of a MOS transistor consisting of the third semiconductor region, the second impurity region, the third impurity region, the second gate insulating layer, and the second gate conductor layer is manipulated by changing the voltage applied to the first gate conductor layer.
• a tenth aspect of the present invention is the semiconductor device according to the first aspect of the present invention, further comprising: a first wiring conductor layer connected to the second impurity region; a second wiring conductor layer connected to the third impurity region; a third wiring conductor layer connected to the second gate conductor layer; a fourth wiring conductor layer connected to the first gate conductor layer; a fifth wiring conductor layer connected to the first impurity region; a memory write operation is performed by controlling voltages applied to the first wiring conductor layer, the second wiring conductor layer, the third wiring conductor layer, the fourth wiring conductor layer, and the fifth wiring conductor layer to generate electron groups and positive hole groups in the third semiconductor region and the second semiconductor region by an impact ionization phenomenon or a gate induced drain leakage current caused by a current flowing between the third impurity region and the fourth impurity region, removing minority carriers in the third semiconductor region and the second semiconductor region from the generated electron groups and positive hole groups, and causing a part or all of the majority carriers in the third semiconductor region and
• the eleventh invention is the tenth invention, characterized in that the first wiring conductor layer connected to the third impurity region is a source line, the second wiring conductor layer connected to the fourth impurity region is a bit line, the third wiring conductor layer connected to the second gate conductor layer is a word line, the fourth wiring conductor layer connected to the first gate conductor layer is a plate line, and the fifth wiring conductor layer is a control line, and the memory write operation and the memory erase operation are performed by applying voltages to the source line, bit line, plate line, word line, and control line, respectively.
• 1A and 1B are diagrams illustrating a cross-sectional structure and a bird's-eye view of a memory device using a semiconductor element according to a first embodiment.
• 1A to 1C are diagrams for explaining the accumulation of hole carries and the cell current during a write operation of the memory device using the semiconductor element according to the first embodiment.
• 4A to 4C are diagrams illustrating an erase operation of a memory device using a semiconductor device according to a first embodiment;
• 1 is a cross-sectional structure of an additional example 1 of a memory device using a semiconductor element according to the first embodiment.
• FIG. 1A shows the vertical cross-sectional structure of a memory using a semiconductor element according to this embodiment.
• a p-layer 1 an example of the "first semiconductor region” in the claims
• silicon having a p-type conductivity containing acceptor impurities.
• n-layer 3a an example of the "first impurity region” in the claims
• donor impurities In contact with a part of the upper surface of the n-layer 3a, there is an n-layer 3b which is a part of a columnar first impurity region standing vertically.
• a columnar p-layer 4 (an example of the "second semiconductor region” in the claims) containing acceptor impurities and having a rectangular horizontal cross section.
• a first insulating layer 2 covering the p-layer 1, the n-layer 3a, the n-layer 3b, and a part of the p-layer 4.
• a first gate insulating layer 5 (an example of the "first gate insulating layer” in the claims) which is in contact with the upper surface of the first insulating layer 2 and covers a part of the side of the p-layer 4.
• a first gate conductor layer 22 (an example of the "first gate conductor layer” in the claims) is in contact with the first insulating layer 2 and the first gate insulating layer 5.
• a second insulating layer 6 (an example of the "first insulating layer” in the claims) is in contact with the upper part of the gate insulating layer 5 and the gate conductor layer 22.
• a p-layer 8 (an example of the "third semiconductor region” in the claims) containing acceptor impurities and having a concave upper surface is in contact with the upper part of the p-layer 4.
• n+ layer 7a an example of the "second impurity region” in the claims
• n+ layer 7b an example of the "third impurity region” in the claims
• a second gate insulating layer 9 (an example of the "second gate insulating layer” in the claims), which also has a concave upper portion.
• This gate insulating layer 9 is in contact with the n+ layers 7a and 7b, respectively.
• a second gate conductor layer 10 (an example of the "second gate conductor layer” in the claims).
• Figure 1(b) shows a three-dimensional bird's-eye view of a vertical cross section of the memory cell of this embodiment.
• a memory device is formed using a semiconductor element consisting of p-layer 1, first insulating layer 2, n-layer 3a, n-layer 3b, p-layer 4, n+ layer 7a, n+ layer 7b, p-layer 8, first gate insulating layer 5, second gate insulating layer 6, first gate conductor layer 22, second gate insulating layer 9, and second gate conductor layer 10.
• the n+ layer 7a is connected to the source line SL (an example of the "source line” in the claims) which is the first wiring conductive layer
• the n+ layer 7b is connected to the bit line BL (an example of the "bit line” in the claims) which is the second wiring conductive layer
• the gate conductor layer 10 is connected to the word line WL (an example of the "word line” in the claims) which is the third wiring conductive layer
• the gate conductor layer 22 is connected to the plate line PL (an example of the "plate line” in the claims) which is the fourth wiring conductive layer
• the n layer 3a is connected to the control line CDC (an example of the "control line” in the claims) which is the fifth wiring conductive layer.
• the memory is operated by manipulating the voltages applied to the source line SL, bit line BL, plate line BL, word line WL, and control line CDC.
• This memory device is hereinafter referred to as a dynamic flash memory.
• the concave shapes of the vertical cross section of the p-layer 8 are shown as straight lines, but they may be U-shaped or semi-elliptical in shape, with curved corners or vertical cross section portions. Accordingly, the surface of the p-layer 8 is curved.
• the bottom surfaces of the second gate insulating layer 9 and the second gate conductor layer 10, which are formed along this line, may also have curved shapes.
• the memory cell is described as having a rectangular vertical cross-sectional structure of the p-layer 4 and p-layer 8 relative to the page, but they may be trapezoidal, polygonal, circular, or elliptical.
• the p-layers 4 and 8 are formed perpendicular to the substrate 20 has been described, but the present invention can also be applied to cases in which they are formed by extending horizontally relative to the substrate 20.
• the n+ layer 7a connected to the source line and the n+ layer 7b connected to the bit line BL are in contact with each other on the top surface of the p layer 8, but they may also be in contact with each other on the side of the p layer 8. They may also be in contact with each other on both the top surface and the side surface.
• the first semiconductor region 1 is a p-type semiconductor, but if an n-type semiconductor substrate is used for the substrate 20 and a p-well is formed as the first semiconductor region 1, the dynamic flash memory can also be operated by arranging the memory cells of the present invention therein.
• the n-layer 3a and the n-layer 3b are shown separately, but they may be a continuous semiconductor region.
• the boundary between the n-layer 3a and the n-layer 3b is shown to coincide with the bottom of the insulating layer 2, but this boundary does not necessarily have to coincide with the bottom of the insulating layer 2.
• the top of the n-layer 3b must be at the same position as or higher than the bottom of the gate conductor layer 22, and an inversion layer must be formed when a voltage is applied to the gate electrode 22, and this inversion layer must come into contact with the n-layer 3b.
• the condition is that, as viewed from the bottom of the p-layer 8, the vertical distance to the n-layer 3b is shorter than the vertical distance to the bottom of the gate conductor layer 22.
• the n-layer 3a may be present over the entire surface of the memory cell region in a plan view, or it may not be formed.
• the n-layer 3a may be formed by an n-well in the p-layer 1. Note that, hereafter, the n-layer 3a and the n-layer 3b may be collectively referred to as the n-layer 3.
• the insulating layer 2 and the gate insulating layer 5 are shown separately in FIG. 1, they may be formed as an integrated unit.
• the p-layer 8 is a p-type semiconductor, but depending on the majority carrier concentration of the p-layer 4, the thickness of the p-layer 8, the material and thickness of the gate insulating layer 9, and the material of the gate conductor layer 10, the p-layer 8 can be any type of p-type, n-type, or i-type.
• the substrate 20 can be made of any material, whether it is an insulator, a semiconductor, or a conductor, as long as it can support the p-layer 1.
• the optimum value of the impurity concentration of p-layer 4 is determined by the amount of surplus holes stored in the memory, which is determined by parameters such as the volume of p-layer 4, the thickness of the first gate insulating layer, the material of the first gate conductor layer, and the applied voltage.
• the impurity concentration of p-layer 8 is determined by the electrical characteristics required of the MOSFET of the access transistor, which mainly depends on the material of the second gate insulating layer and the second gate conductor layer, and the applied voltage. Therefore, the impurity concentration and profile are set independently for p-layer 4 and p-layer 8. Also, p-layer 4 and p-layer 8 may be formed from different semiconductor material layers.
• the impurity concentration may have a profile.
• the impurity concentrations of n layer 3a and n layer 3b may have a profile.
• the length of p layer 8 in the direction connected to n+ layers 7a and 7b may be longer or shorter than the length of p layer 4.
• an LDD (Lightly Doped Drain) region having a donor concentration lower than the donor impurity concentration of n+ layers 7a and 7b may be provided between p layer 8 and n+ layers 7a and 7b.
• first through fifth wiring conductive layers may be formed in multiple layers as long as they do not contact each other.
• the gate insulating layers 5 and 9 can be made of any insulating film used in normal MOS processes, such as a SiO2 film, a SiON film, a HfSiON film, or a laminated film of SiO2/SiN.
• the first gate conductor layer 22 can change the potential of a portion of the memory cell via the gate insulating layer 5
• the second gate conductor layer 10 can change the potential of a portion of the memory cell via the gate insulating layer 9
• they may be made of metals such as W, Pd, Ru, Al, TiN, TaN, and WN, metal nitrides, or alloys thereof (including silicides), such as a layered structure such as TiN/W/TaN, or may be made of a highly doped semiconductor.
• the first gate conductor layer 22 may surround the entire p-layer 4 via the insulating layer 5 in a plan view, or may cover a portion of it.
• the first gate conductor layer 22 may be divided into multiple pieces in a plan view.
• the first gate conductor layer 22 may also be divided into multiple pieces in the vertical direction.
• the first gate conductor layer 22 exists on both sides of the p-layer 4, but if it exists on either side, the dynamic flash memory can also operate.
• n+ layer 7a and n+ layer 7b are formed from a p+ layer semiconductor region containing a high concentration of acceptor impurities, in which holes are the majority carriers
• n-type semiconductors are used for p-layer 1, p-layer 4, and p-layer 8
• p-type semiconductors are used for n-layer 3a and n-layer 3b
• a dynamic flash memory can be operated with electrons as the write carriers.
• one or more of the dynamic flash memory cells described above are arranged two-dimensionally on the substrate 20.
• the carrier behavior, accumulation, and cell current during the write operation of the dynamic flash memory according to the first embodiment of the present invention will be described.
• the majority carriers in the n layer 3a, n layer 3b, n+ layer 7a, and n+ layer 7b are electrons, and for example, poly-Si containing a high concentration of donor impurities is used for the gate conductor layer 22 connected to the plate line PL and the gate conductor layer 10 connected to the word line WL (hereinafter, poly-Si containing a high concentration of donor impurities is referred to as "n+poly"), and a p-type semiconductor is used as the third semiconductor region 8. As shown in FIG.
• the MOSFET in this memory cell operates with the n+ layer 7a as the source, the n+ layer 7b as the drain, the gate insulating layer 9, the gate conductor layer 10 as the gate, and the p layer 8 as the substrate as its components.
• 0V is applied to the p-layer 1
• 0.5V is applied to the n-layer 3a connected to the control line CDC
• 0V is input to the n+ layer 7a connected to the source line SL
• 1.0V is input to the n+ layer 7b connected to the bit line BL
• -1V is applied to the gate conductor layer 22 connected to the plate line PL.
• the threshold voltage of the MOSFET with the gate conductor layer 10 as the gate electrode before writing is set to 1.0V when the voltage of the plate line PL is -1V.
• a partial inversion layer 12 is formed directly under the gate insulating layer 9 below the gate conductor layer 10, and a pinch-off point 13 exists.
• the MOSFET having the gate conductor layer 10 operates in the saturation region.
• the electric field becomes maximum between the pinch-off point 13 and the n+ layer 7b in the MOSFET having the gate conductor layer 10, and impact ionization occurs in this region. Due to this impact ionization, electrons accelerated from the n+ layer 7a connected to the source line SL toward the n+ layer 7b connected to the bit line BL collide with the Si lattice, and electron-hole pairs are generated by the kinetic energy. The generated holes diffuse toward the area with a lower hole concentration due to the concentration gradient. Some of the generated electrons flow into the gate conductor layer 10, but the majority flow into the n+ layer 7b connected to the bit line BL. As a result, holes 14 are accumulated in the p layer 4 and the p layer 8.
• the plate line PL is set to -1V, which prevents the depletion layer from spreading into the p-layer 4, allowing holes generated by impact ionization to accumulate, and also contributes to adjusting the threshold voltage of the MOSFET in the memory cell through the substrate bias effect.
• n+poly was used for the gate conductor layer 22 to bias a negative voltage, but the same effect as applying a negative voltage can be achieved by using a material with a higher work function than the material for the gate conductor layer 10.
• the width of the p-layer 4 is made wider than the width of the second gate conductor layer 10 in a plan view to increase the amount of excess holes that can be accumulated.
• a gate-induced drain leakage (GIDL) current may be passed to generate a group of holes (see, for example, Non-Patent Document 7).
• FIG. 2(b) shows the hole groups 14 in the p-layer 4 and p-layer 8 immediately after writing when the plate line PL is -1V, the word line WL, source line SL, and bit line BL are biased at 0V, and the control line CDC is biased at 0.5V.
• the generated hole group 14 is the majority carrier of the p-layer 4 and p-layer 8, but the generated hole concentration temporarily becomes high in the p-layer 8 region, and moves by diffusion toward the p-layer 4 due to the concentration gradient.
• the p-layer 4 is accumulated at a higher concentration near the first gate insulating layer 5.
• the p-layer 8 which is essentially the substrate of the MOSFET having the gate conductor layer 10, is charged with a positive bias.
• the threshold voltage of the MOSFET having the gate conductor layer 10 is lowered by the positive substrate bias effect due to the holes temporarily accumulated in the p-layer 4 and p-layer 8.
• the threshold voltage of the MOSFET having the gate conductor layer 10 connected to the word line WL is about 0.6 V, which is lower than before writing. This write state is assigned to the logical memory data "1".
• the voltage application conditions can be combinations such as 1.0V (V-BL)/-1V (V-PL)/2.0V (V-WL), 1.0V (V-BL)/-0.5V (V-PL)/1.2V (V-WL), and 1.5V (V-BL)/-1V (V-PL)/2.0V (V-WL), with SL set to 0V.
• the voltage relationship between the bit line BL and source line SL may also be reversed.
• the threshold voltage drops during writing, and the pinch-off point 13 gradually shifts toward the n+ layer 7b, and the MOSFET may operate linearly.
• the erase operation mechanism will be explained using FIG. 3.
• the source line SL, bit line BL, and word line WL are set to 0V, and the voltage of the control line CDC is set to 0.5V.
• the voltage of the plate line PL is set to, for example, 2V.
• the electrons lost due to recombination are replenished from the inversion layer 15 in contact with the p-layer 4 through the n-layer 3a and n-layer 3b.
• the hole concentration of the p-layer 4 and the p-layer 8 decreases over time, and the threshold voltage of the MOSFET becomes higher than when "1" was written. For example, if the plate line PL voltage is -1V here, the threshold voltage of the MOSFET becomes 1.2V.
• the MOSFET having the gate conductor layer 10 to which this word line WL is connected will enter an erased state, with almost no current flowing even when a voltage is applied.
• This state is the logical storage data "0" of the dynamic flash memory.
• the vertical cross section of the p-layer 8 is concave, so the effective distance between the n+ layer 7a and the n+ layer 7b is longer, and the leakage current of the MOSFET when the logical memory data is "0" can be reduced.
• the voltage application conditions can be combinations such as 0V (V-BL)/2V (W-PL)/-1V (V-WL), 0.4V (V-BL)/2V (V-PL)/0.5V (V-WL), or 1V (V-BL)/1.5V (V-PL)/0V (V-WL), with the source line SL at 0V and the control line CDC at 0.5V.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL mentioned above are examples for performing a memory erase operation, and other operating conditions that allow a memory erase operation may also be used.
• the insulating layer 2 and the gate insulating layer 5 can be formed simultaneously. Also, the insulating layer 2 and the gate insulating layer 5 can be formed of the same material or different materials. Also, by adjusting the thickness of the gate oxide film 5 and the insulating films 2 and 6, respectively, the voltage applied to the gate conductor layer 22 can be adjusted.
• control line CDC is set to 0.5V whether writing to or erasing memory, but the control line CDC can also be set to ground voltage, i.e. 0V.
• the memory can be erased even if a positive voltage is applied to the plate line PL during erasure, so there is a feature that information from multiple cells that share the gate conductor layer 22 can be erased at once.
• the memory cell of the present invention is formed in the area of a single MOSFET in a plan view, by sharing the source line and bit line with adjacent memory cells, a higher density memory cell array can be realized than conventional dynamic RAM.
• FIG. 4 components that are the same as or similar to those in FIG. 1 are given the same reference numerals.
• the n-layer 3a in FIG. 1 is not connected to the control line CDC.
• the rest is the same as FIG. 1.
• 0V is applied to the p-layer 1. This allows the dynamic flash memory to operate normally.
• dynamic flash memory can also be operated with a structure in which the n-layer 3 is placed at the bottom of the p-layer 4 individually in each memory cell, rather than sharing the n-layer 3 among multiple cells as in Figure 4(b).
• the write operation, erase operation, and read operation of the dynamic flash memory can be performed by applying the same voltages as in the first embodiment to the source line SL, plate line PL, word line WL, and bit line BL, excluding the control line CDC.
• the control line CDC excluding the control line CDC.
• the MOSFET which is the access transistor of the dynamic flash memory according to this embodiment, is formed by n+ layer 7a, n+ layer 7b, p layer 8, second gate insulating layer 9, and second gate conductor layer 10. Since the vertical cross section of p layer 8 is concave, the electric field lines from second gate conductor layer 10 to p layer 8, which is the channel portion of the MOSFET, are dispersed rather than concentrated. As a result, the backgate bias effect is increased, and the carrier concentration dependency of the threshold of the access transistor is increased compared to parallel plate or FIN type MOSFETs, expanding the margin of memory operation.
• Feature 3 In this embodiment, as described in Feature 2, it is possible to arrange access transistors having a short gate length in a plan view, so that a high-density memory arrangement can be realized.
• the p-layer 8 which is one of the components of the MOSFET in the dynamic flash memory according to this embodiment, is connected to the p-layer 4, the n-layers 3a and 3b, and the p-layer 1, and the threshold value of the MOSFET of the access transistor can be freely set by adjusting the voltage applied to the gate conductor layer 22. Furthermore, since the area under the MOSFET is not completely depleted, it is not greatly affected by the coupling of the gate electrode from the word line of the floating body, which is a drawback of DRAMs that do not have a capacitor. In other words, according to the present invention, it is possible to design a wide margin of the operating voltage as a dynamic flash memory.
• the components n+ layer 7a, n+ layer 7b, p layer 8, second gate insulating layer 9, and second gate conductor layer 10 can be formed in the same process as the peripheral CMOS, that is, the source, drain, substrate, gate oxide film, and gate electrode, and therefore it is possible to provide a high-density memory cell array and a structure compatible with the peripheral CMOS circuits.
• the present invention makes it possible to provide a semiconductor memory device that is denser, faster, and has a higher operating margin than conventional devices.
• First semiconductor region 2 First insulating layer 3a First impurity layer 3b Second impurity layer 3 General term for 3a and 3b 4 Second semiconductor region 5 First gate insulating layer 6 Second insulating layer 7a, 7c n+ layer 8 Third semiconductor region 9 Second gate insulating layer 10 Second gate conductor layer 12 Inversion layer 13 Pinch-off point 14 Group of holes 15 Inversion layer 16 Group of electrons 20 Substrate 22 First gate conductor layer SL Source line PL Plate line WL Word line BL Bit line CDC Control line

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