KR20250162811A - 반도체 소자를 사용한 메모리 장치 - Google Patents

반도체 소자를 사용한 메모리 장치

Info

Publication number
KR20250162811A
KR20250162811A KR1020257032939A KR20257032939A KR20250162811A KR 20250162811 A KR20250162811 A KR 20250162811A KR 1020257032939 A KR1020257032939 A KR 1020257032939A KR 20257032939 A KR20257032939 A KR 20257032939A KR 20250162811 A KR20250162811 A KR 20250162811A
Authority
KR
South Korea
Prior art keywords
conductor layer
layer
impurity region
region
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020257032939A
Other languages
English (en)
Korean (ko)
Inventor
마사카즈 가쿠무
고지 사쿠이
노조무 하라다
Original Assignee
유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 filed Critical 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드
Publication of KR20250162811A publication Critical patent/KR20250162811A/ko
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020257032939A 2023-04-11 2023-04-11 반도체 소자를 사용한 메모리 장치 Pending KR20250162811A (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2023/014698 WO2024214180A1 (ja) 2023-04-11 2023-04-11 半導体素子を用いたメモリ装置

Publications (1)

Publication Number Publication Date
KR20250162811A true KR20250162811A (ko) 2025-11-19

Family

ID=93016351

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020257032939A Pending KR20250162811A (ko) 2023-04-11 2023-04-11 반도체 소자를 사용한 메모리 장치

Country Status (5)

Country Link
US (1) US12588186B2 (https=)
JP (1) JPWO2024214180A1 (https=)
KR (1) KR20250162811A (https=)
TW (1) TWI892578B (https=)
WO (1) WO2024214180A1 (https=)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02188966A (ja) 1989-01-17 1990-07-25 Toshiba Corp Ｍｏｓ型半導体装置
US20030111681A1 (en) 2001-12-14 2003-06-19 Kabushiki Kaisha Toshiba Semiconductor memory device and its manufacturing method
US20080137394A1 (en) 2006-12-12 2008-06-12 Renesas Technology Corp. Semiconductor memory device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060192249A1 (en) 2004-09-20 2006-08-31 Samsung Electronics Co., Ltd. Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same
DE102006016550B4 (de) * 2005-04-09 2010-04-29 Samsung Electronics Co., Ltd., Suwon-si Feldeffekttransistoren mit vertikal ausgerichteten Gate-Elektroden und Verfahren zum Herstellen derselben
US7919800B2 (en) * 2007-02-26 2011-04-05 Micron Technology, Inc. Capacitor-less memory cells and cell arrays
KR102529073B1 (ko) * 2015-04-29 2023-05-08 제노 세미컨덕터, 인크. 백바이어스를 이용한 드레인 전류가 향상된 트랜지스터 및 메모리 셀
KR102905486B1 (ko) * 2021-08-30 2025-12-29 삼성전자주식회사 반도체 장치
KR102784170B1 (ko) 2021-09-06 2025-03-19 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 반도체 소자를 사용한 메모리 장치
WO2023148799A1 (ja) * 2022-02-01 2023-08-10 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02188966A (ja) 1989-01-17 1990-07-25 Toshiba Corp Ｍｏｓ型半導体装置
US20030111681A1 (en) 2001-12-14 2003-06-19 Kabushiki Kaisha Toshiba Semiconductor memory device and its manufacturing method
US20080137394A1 (en) 2006-12-12 2008-06-12 Renesas Technology Corp. Semiconductor memory device

Non-Patent Citations (13)

* Cited by examiner, † Cited by third party
Title
E. Yoshida : "A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory," IEEE IEDM (2006).
F. Morishita, H. Noda, I. Hayashi, T. Gyohten, M. Oksmoto, T. Ipposhi, S. Maegawa, K. Dosaka, and K. Arimoto : "Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI," IEICE Trans. Electron., Vol.E90-c., No.4 pp.765 - 771 (2007)
H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J. Kim, Y. C. Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung : "4F2 DRAM Cell with Vertical Pillar Transistor(VPT)," 2011 Proceeding of the European Solid-State Device Research Conference, (2011)
H. S. Philip Wong, S. Raoux, S. Kim, Jiale Liang, J. R. Reifenberg, B. Rajendran, M. Asheghi and K. E. Goodson : "Phase Change Memory," Proceeding of IEEE, Vol.98, No 12, December, pp.2201 - 2227 (2010)
Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka : IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573 - 578 (1991)
J. Wan, L. Rojer, A. Zaslavsky, and S. Critoloveanu : "A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration," Electron Device Letters, Vol.35, No.2, pp.179 - 181 (2012)
K. Sakui, N. Harada, "Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)," Proc. IEEE IMW, pp.72 - 75 (2021)
M. G. Ertosum, K. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat : "Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electron," IEEE Electron Device Letter, Vol.31, No.5, pp.405 - 407 (2010)
T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y. Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, A. Nitayama : "Floating Body RAM Technology and its Scalability to 32㎚ Node and Beyond," IEEE IEDM (2006).
T. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama : "Low Power and high Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V," IEDM (2007)
Takashi Ohasawa and Takeshi Hamamoto, "Floating Body Cell -a Novel Body Capacitorless DRAM Cell", Pan Stanford Publishing (2011).
W. Kang, L. Zhang, J. Klein, Y. Zhang, D. Ravelosona, and W. Zhao : "Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology," IEEE Transaction on Electron Devices, pp.1 - 9 (2015)
Yuan Taur and Tak. H. Ning, "Fundamentals of Modern VLSI Devices" (2021).

Also Published As

Publication number Publication date
JPWO2024214180A1 (https=) 2024-10-17
TW202450432A (zh) 2024-12-16
US20240349482A1 (en) 2024-10-17
TWI892578B (zh) 2025-08-01
WO2024214180A1 (ja) 2024-10-17
US12588186B2 (en) 2026-03-24

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