WO2024180973A1 - Ｒｃ－ｉｇｂｔおよびｒｃ－ｉｇｂｔの製造方法 - Google Patents

Ｒｃ－ｉｇｂｔおよびｒｃ－ｉｇｂｔの製造方法 Download PDF

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WO2024180973A1
WO2024180973A1 PCT/JP2024/002747 JP2024002747W WO2024180973A1 WO 2024180973 A1 WO2024180973 A1 WO 2024180973A1 JP 2024002747 W JP2024002747 W JP 2024002747W WO 2024180973 A1 WO2024180973 A1 WO 2024180973A1
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region
igbt
diode
regions
boundary
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French (fr)
Japanese (ja)
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敦史 後田
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Rohm Co Ltd
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/128—Anode regions of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/129—Cathode regions of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment

Definitions

  • This disclosure relates to a reverse conducting-insulated gate bipolar transistor (RC-IGBT) and a method for manufacturing the RC-IGBT.
  • RC-IGBT reverse conducting-insulated gate bipolar transistor
  • a known semiconductor device is the RC-IGBT, which includes an IGBT region in which an IGBT is formed and a diode region in which a free wheel diode is formed (see, for example, Patent Document 1).
  • the RC-IGBT further includes a boundary region formed between the IGBT region and the diode region.
  • a lifetime control region may be formed in the diode region of the RC-IGBT to reduce switching loss.
  • a lifetime control region is also formed in the boundary region, taking into consideration misalignment of the lifetime control region, etc.
  • the boundary region has a different configuration from both the IGBT region and the diode region, it is difficult for it to contribute to both the electrical characteristics of the IGBT and the electrical characteristics of the diode. For this reason, it is preferable to have a small number of boundary regions.
  • the RC-IGBT comprises a semiconductor substrate, an active region provided in the semiconductor substrate, and a peripheral region provided in the semiconductor substrate and surrounding the active region when viewed in the thickness direction of the semiconductor substrate, the active region including an IGBT region and a plurality of diode regions arranged in a first direction, and a boundary region formed between the IGBT region adjacent in the first direction and a diode region that is one of the plurality of diode regions, and a lifetime control region provided in the semiconductor substrate and overlapping the peripheral region, the plurality of diode regions, and the boundary region when viewed in the thickness direction, the plurality of diode regions including first end diode regions, the first end diode regions being formed at both ends of the active region in the first direction when viewed in the thickness direction and being continuous with the peripheral region, and the lifetime control region including a first end region formed across the first end diode region and a portion of the peripheral region that is continuous with the first end diode region.
  • a method for manufacturing an RC-IGBT includes the steps of: preparing a wafer having a first wafer main surface and a second wafer main surface opposite to the first wafer main surface, the wafer being partitioned into an active region and a peripheral region surrounding the active region; forming, in the active region, an IGBT region and a plurality of diode regions aligned in a first direction, and a boundary region formed between the IGBT region and a diode region that is one of the plurality of diode regions adjacent to each other in the first direction; and providing, in the wafer, a lifetime control region that overlaps with the peripheral region, the plurality of diode regions, and the boundary region as viewed in the thickness direction of the wafer, the plurality of diode regions including a first end diode region, the first end diode region being formed at both ends of the active region in the first direction as viewed in the thickness direction and being continuous with the peripheral region; and in the step of providing the lifetime control
  • the above RC-IGBT and manufacturing method for the RC-IGBT can reduce the number of boundary regions.
  • FIG. 1 is a schematic plan view of the RC-IGBT of the first embodiment.
  • FIG. 2 is a schematic plan view of a semiconductor substrate of the RC-IGBT of FIG.
  • FIG. 3 is a schematic plan view showing a lifetime control region in the semiconductor substrate of FIG.
  • FIG. 4 is a schematic cross-sectional view of the RC-IGBT taken along line F4-F4 in FIG.
  • FIG. 5 is a schematic cross-sectional view of the RC-IGBT taken along line F5-F5 in FIG. 6A to 6C are schematic cross-sectional views illustrating exemplary manufacturing steps for the RC-IGBT of the first embodiment.
  • FIG. 7 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG.
  • FIG. 8 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 9 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 12 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 13 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 14 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 15 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 16 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. FIG.
  • FIG. 17 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 18 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 19 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG.
  • FIG. 20 is a schematic plan view of a semiconductor substrate in the RC-IGBT of the second embodiment.
  • FIG. 21 is a schematic plan view showing a lifetime control region in the semiconductor substrate of FIG.
  • FIG. 22 is a schematic plan view of the RC-IGBT of the third embodiment.
  • FIG. 23 is a schematic plan view of a semiconductor substrate of the RC-IGBT of FIG.
  • FIG. 24 is a schematic plan view showing a lifetime control region in the semiconductor substrate of FIG.
  • FIG. 25 is a schematic plan view of a semiconductor substrate in a modified RC-IGBT.
  • FIG. 26 is a schematic cross-sectional view of an active region of a modified RC-IGBT.
  • the statements “the width of part A is equal to the width of part B", “the depth of part A is equal to the depth of part B", “the length of part A is equal to the length of part B”, and “the dimensions of part A are equal to the dimensions of part B” mean that the difference between the width (depth, length, dimensions) of part A and the width (depth, length, dimensions) of part B is within 10% of the width (depth, length, dimensions) of part A.
  • FIG. 1 shows an example of a planar structure of the RC-IGBT 10.
  • Figure 2 shows an example of a planar structure of a semiconductor substrate 12 of the RC-IGBT 10, which will be described later.
  • Figure 3 shows a lifetime control region 30, which will be described later, in Figure 2.
  • an emitter electrode EM and a gate electrode GT which will be described later, are indicated by two-dot chain lines in order to facilitate understanding of the drawings.
  • the Z direction of the mutually orthogonal XYZ axes shown in FIG. 1 corresponds to the thickness direction of the RC-IGBT 10.
  • the term "planar view” used in this specification refers to viewing the RC-IGBT 10 along the Z direction, unless otherwise explicitly stated.
  • the RC-IGBT 10 is a semiconductor device that is configured on a single chip with an IGBT and a freewheeling diode (freewheeling diode: FWD) connected in anti-parallel to the IGBT.
  • FWD freewheeling diode
  • the RC-IGBT 10 includes a rectangular flat semiconductor substrate 12 whose thickness direction is in the Z direction.
  • the semiconductor substrate 12 may also be referred to as a "chip” or a "semiconductor chip.”
  • the semiconductor substrate 12 has a single-layer structure made of, for example, a silicon single crystal substrate.
  • the semiconductor substrate 12 has a first main surface 14, a second main surface 16 (see FIG. 4) opposite the first main surface 14 in the Z direction, and first to fourth side surfaces 18A to 18D connecting the first main surface 14 and the second main surface 16.
  • Both the first main surface 14 and the second main surface 16 are formed in a rectangular shape when viewed in a plane.
  • the first side surface 18A and the second side surface 18B form both end surfaces of the semiconductor substrate 12 in the X direction
  • the third side surface 18C and the fourth side surface 18D form both end surfaces of the semiconductor substrate 12 in the Y direction.
  • the RC-IGBT 10 includes an active region 20 provided on the semiconductor substrate 12, and a peripheral region 28 provided on the semiconductor substrate 12 and surrounding the active region 20 in a plan view.
  • the active region 20 is shown by a dashed line to make the drawing easier to understand.
  • the active region 20 is formed on the first main surface 14.
  • the active region 20 is formed, for example, as a rectangular region that is slightly smaller than the first main surface 14.
  • the peripheral region 28 is a region defined by the active region 20 and the first to fourth side surfaces 18A to 18D in a plan view.
  • the RC-IGBT 10 includes an emitter electrode EM, a gate electrode GT, and a collector electrode CL (see FIG. 4).
  • the emitter electrode EM and the gate electrode GT are formed on the first main surface 14.
  • the collector electrode CL is formed on the second main surface 16.
  • the emitter electrode EM and the gate electrode GT are formed, for example, in the active region 20.
  • the emitter electrode EM is formed over most of the active region 20.
  • the gate electrode GT is formed at the end of the active region 20 closer to the fourth side surface 18D in the Y direction and at the center in the X direction. The position of the gate electrode GT can be changed as desired.
  • the gate electrode GT may be formed in one of the four corner portions of the active region 20.
  • the emitter electrode EM and the gate electrode GT have a layered structure of one metal film or multiple metal films.
  • the emitter electrode EM and the gate electrode GT may contain at least one of titanium (Ti), tungsten (W), aluminum (Al), and copper (Cu).
  • the emitter electrode EM and the gate electrode GT have a layered structure including a Ti-based metal film and an Al-based metal film. Note that, although the emitter electrode EM and the gate electrode GT are formed from the same material in the above example, this is not limiting. The emitter electrode EM and the gate electrode GT may be formed from different materials.
  • the collector electrode CL shown in FIG. 4 covers, for example, the entire second main surface 16.
  • the collector electrode CL has a layered structure of one metal film or multiple metal films.
  • the collector electrode CL includes at least one of Ti, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), and Al.
  • the collector electrode CL includes a Ti film in contact with the second main surface 16.
  • the collector electrode CL may have a layered structure including a Ti film, a Ni film, a Pd film, and an Au film, which are layered in this order from the second main surface 16 side.
  • the active region 20 includes at least one (multiple in the first embodiment) IGBT region 22 and multiple diode regions 24.
  • the active region 20 includes multiple (two in the first embodiment) IGBT regions 22 and multiple (three in the first embodiment) diode regions 24.
  • the multiple IGBT regions 22 and the multiple diode regions 24 are arranged alternately in the Y direction.
  • the active region 20 includes at least one boundary region 26 formed between adjacent IGBT regions 22 and diode regions 24.
  • the active region 20 includes multiple boundary regions 26.
  • two IGBT regions 22 and three diode regions 24 are provided, resulting in four boundary regions 26.
  • the Y direction corresponds to the "first direction.”
  • the first direction can be said to be the arrangement direction of the IGBT regions 22, diode regions 24, and boundary regions 26.
  • the IGBT region 22, the diode region 24, and the boundary region 26 are each formed in a band shape with the X direction being the longitudinal direction and the Y direction being the lateral direction. Therefore, it can also be said that the X direction is the length direction and the Y direction is the width direction of the IGBT region 22, the diode region 24, and the boundary region 26.
  • the IGBT region 22, the diode region 24, and the boundary region 26 are each arranged along the lateral direction (width direction).
  • the length dimensions of the IGBT region 22, the diode region 24, and the boundary region 26 are equal to each other.
  • the IGBT region 22, the diode region 24, and the boundary region 26 are each formed, for example, across the entire X-direction of the active region 20.
  • the length dimensions of the IGBT region 22, the diode region 24, and the boundary region 26 are equal to the dimension of the active region 20 in the X-direction.
  • the width dimension of the boundary region 26 is smaller than the width dimensions of both the IGBT region 22 and the diode region 24.
  • the width dimension of the boundary region 26 is equal to or smaller than half the width dimensions of both the IGBT region 22 and the diode region 24.
  • the relationship between the area of the IGBT region 22 and the area of the diode region 24 in the active region 20 is set according to the electrical characteristics of the RC-IGBT 10.
  • the total area of the multiple diode regions 24 is larger than the total area of the multiple IGBT regions 22.
  • the width dimension of each diode region 24 is larger than the width dimension of each IGBT region 22. Therefore, the area of each diode region 24 is larger than the area of each IGBT region 22.
  • the multiple diode regions 24 include first end diode regions 24A, 24B formed at both ends of the active region 20 in the Y direction in a plan view, and a central diode region 24C formed closer to the center of the active region 20 in the Y direction than the first end diode regions 24A, 24B.
  • the central diode region 24C is formed in the center of the active region 20 in the Y direction.
  • the first end diode region 24A is formed at the end closer to the third side surface 18C of both ends of the active region 20 in the Y direction.
  • the first end diode region 24B is formed at the end closer to the fourth side surface 18D of both ends of the active region 20 in the Y direction.
  • the first end diode regions 24A, 24B extend along the X direction.
  • the X direction corresponds to the "second direction”.
  • the X direction (second direction) is a direction perpendicular to the Y direction (first direction) in a plan view.
  • the peripheral region 28, which is formed outside the active region 20, is formed on the first main surface 14.
  • the peripheral region 28 is a region that does not include the IGBT region 22, the diode region 24, and the boundary region 26.
  • the peripheral region 28 is formed in a rectangular frame shape in a plan view.
  • the peripheral region 28 is a region in which a termination structure that improves the dielectric strength voltage of the RC-IGBT 10 is provided, for example. The termination structure will be described in detail later.
  • Each of the first end diode regions 24A and 24B is a region adjacent to the peripheral region 28 in the Y direction. Each of the first end diode regions 24A and 24B can also be said to be continuous with the peripheral region 28 in the Y direction. In a plan view, the first end diode region 24A is adjacent to the region of the peripheral region 28 between the active region 20 and the third side surface 18C in the Y direction. The first end diode region 24B is adjacent to the region of the peripheral region 28 between the active region 20 and the fourth side surface 18D in the Y direction. In a plan view, the first end diode region 24A can also be said to be continuous with the region of the peripheral region 28 between the active region 20 and the third side surface 18C in the Y direction. In a plan view, the first end diode region 24B can also be said to be continuous with the region of the peripheral region 28 between the active region 20 and the fourth side surface 18D in the Y direction.
  • each of the first end diode regions 24A and 24B is adjacent to the peripheral region 28 in the X direction. It can also be said that each of the first end diode regions 24A and 24B is continuous with the peripheral region 28 in the X direction. More specifically, the end closer to the first side 18A of both ends in the X direction of each of the first end diode regions 24A and 24B is adjacent to the region of the peripheral region 28 between the active region 20 and the first side 18A in the X direction. The end closer to the second side 18B of both ends in the X direction of each of the first end diode regions 24A and 24B is adjacent to the region of the peripheral region 28 between the active region 20 and the second side 18B in the X direction.
  • each of the first end diode regions 24A and 24B is continuous with the region of the peripheral region 28 between the active region 20 and the first side 18A in the X direction.
  • the end closest to the second side surface 18B can be said to be continuous with the region of the peripheral region 28 between the active region 20 and the second side surface 18B in the X direction.
  • central diode region 24C, the IGBT region 22, and the boundary region 26 are also adjacent to the peripheral region 28 in the X direction. It can also be said that the central diode region 24C, the IGBT region 22, and the boundary region 26 are also continuous with the peripheral region 28 in the X direction.
  • the RC-IGBT 10 includes a lifetime control region 30.
  • the lifetime control region 30 is provided in the semiconductor substrate 12. Note that in FIG. 3, the lifetime control region 30 is hatched.
  • lifetime is the average time that excess carriers exist in the semiconductor material before recombining and reaching equilibrium.
  • the lifetime control region 30 is a region where lifetime killers are intentionally formed, for example, by injecting impurities into the semiconductor substrate 12.
  • a lifetime killer is a carrier recombination center that shortens the lifetime.
  • One example of a lifetime killer is a crystal defect.
  • the lifetime control region 30 can be said to be a region where crystal defects are formed inside the semiconductor substrate 12.
  • the lifetime control region 30 is formed, for example, by injecting helium (He) into the semiconductor substrate 12.
  • the lifetime killer is not limited to crystal defects, but may be a vacancy, a divacancy, a compound defect of a vacancy or a divacancy with an element constituting the semiconductor substrate 12, a dislocation, a rare gas element such as helium or neon (Ne), a metal element such as platinum (Pt), etc.
  • the lifetime control region 30 is formed in the active region 20 and the peripheral region 28 other than the IGBT region 22 in a plan view.
  • the lifetime control region 30 is formed in a region that overlaps with the peripheral region 28, the plurality of diode regions 24, and the plurality of boundary regions 26 in a plan view. Therefore, the lifetime control region 30 includes first end regions 32A, 32B formed across the first end diode regions 24A, 24B and the portion of the peripheral region 28 that is continuous with the first end diode regions 24A, 24B, and a central region 32C formed closer to the center of the active region 20 in the Y direction than the first end regions 32A, 32B. In one example, the lifetime control region 30 is formed across the entirety of each of the plurality of diode regions 24, the plurality of boundary regions 26, and the peripheral region 28 in a plan view.
  • the first end region 32A includes a region formed across the first end diode region 24A and a portion of the outer circumferential region 28 that is continuous with the first end diode region 24A in the Y direction.
  • the first end region 32A also includes a region formed across both ends of the first end diode region 24A in the X direction and a portion of the outer circumferential region 28 that is continuous with the first end diode region 24A in the X direction.
  • the first end region 32A also includes a boundary region 26 that is continuous with the first end diode region 24A on the opposite side of the outer circumferential region 28 in the Y direction.
  • the first end region 32A is formed across the first end diode region 24A, a portion of the outer circumferential region 28 that is continuous with the first end diode region 24A, and the boundary region 26 that is continuous with the first end diode region 24A.
  • the first end region 32A includes a first outer peripheral region between the first end diode region 24A and the third side surface 18C in the Y direction in the outer peripheral region 28 in a plan view, a second outer peripheral region between the first end diode region 24A and the boundary region 26 and the first side surface 18A in the X direction, and a third outer peripheral region between the first end diode region 24A and the boundary region 26 and the second side surface 18B in the X direction.
  • the first outer peripheral region includes, for example, a corner region formed by the third side surface 18C and the first side surface 18A in a plan view, and a corner region formed by the third side surface 18C and the second side surface 18B.
  • the first end region 32A is formed over the entire first end diode region 24A, the boundary region 26 adjacent to the first end diode region 24A in the Y direction, the first outer peripheral region, the second outer peripheral region, and the third outer peripheral region in a plan view.
  • the first end region 32B includes a region formed across the first end diode region 24B and a portion of the peripheral region 28 that is continuous with the first end diode region 24B in the Y direction.
  • the first end region 32B also includes a region formed across both ends of the first end diode region 24B in the X direction and a portion of the peripheral region 28 that is continuous with the first end diode region 24B in the X direction.
  • the first end region 32B also includes a boundary region 26 that is continuous with the first end diode region 24B on the opposite side of the peripheral region 28 in the Y direction.
  • the first end region 32B is formed across the first end diode region 24B, a portion of the peripheral region 28 that is continuous with the first end diode region 24B, and the boundary region 26 that is continuous with the first end diode region 24B.
  • the first end region 32B includes a fourth outer peripheral region between the first end diode region 24B and the fourth side surface 18D in the Y direction, a fifth outer peripheral region between the first end diode region 24B and the boundary region 26 and the first side surface 18A in the X direction, and a sixth outer peripheral region between the first end diode region 24B and the boundary region 26 and the second side surface 18B in the X direction.
  • the fourth outer peripheral region includes, for example, a corner region formed by the fourth side surface 18D and the first side surface 18A in a plan view, and a corner region formed by the fourth side surface 18D and the second side surface 18B in a plan view.
  • the first end region 32B is formed over the entire first end diode region 24B, the boundary region 26 adjacent to the first end diode region 24B in the Y direction, the fourth outer peripheral region, the fifth outer peripheral region, and the sixth outer peripheral region in a plan view.
  • the central region 32C includes a region formed across the central diode region 24C and the boundary region 26 that is continuous with both sides of the central diode region 24C in the Y direction.
  • the central region 32C is continuous with the portion of the lifetime control region 30 in the peripheral region 28 that is closer to the first side 18A and the portion that is closer to the second side 18B.
  • the central region 32C includes, in a plan view, a seventh peripheral region of the peripheral region 28 between the central diode region 24C and its boundary regions 26 on both sides in the Y direction and the first side surface 18A in the X direction, and an eighth peripheral region between the central diode region 24C and its boundary regions 26 on both sides in the Y direction and the second side surface 18B in the X direction.
  • the central region 32C is formed throughout the central diode region 24C, the boundary regions 26 on both sides in the Y direction of the central diode region 24C, the seventh peripheral region, and the eighth peripheral region in a plan view.
  • the Y-direction dimension LA1 of the first end region 32A is greater than the Y-direction dimension L2 of the central region 32C.
  • the Y-direction dimension LB1 of the first end region 32B is greater than the Y-direction dimension L2 of the central region 32C.
  • Dimension LA1 is equal to dimension LB1.
  • Fig. 4 shows an example of a cross-sectional structure of the IGBT region 22, the diode region 24, and the boundary region 26.
  • the semiconductor substrate 12 includes an n-type semiconductor layer 36.
  • the semiconductor layer 36 is formed throughout the interior of the semiconductor substrate 12.
  • the semiconductor layer 36 includes a first major surface 36A and a second major surface 36B opposite to the first major surface 36A.
  • the second major surface 36B constitutes, for example, the second major surface 16 of the semiconductor substrate 12.
  • the semiconductor layer 36 may be referred to as, for example, a "drift layer” or a “drift region.”
  • the n-type impurity concentration of the semiconductor layer 36 may be, for example, 1 ⁇ 10 13 cm -3 or more and 1 ⁇ 10 15 cm -3 or less. In the first embodiment, the n-type corresponds to the "first conductivity type.”
  • the RC-IGBT 10 includes an n-type buffer region 38 formed in a surface layer portion of the second main surface 36B.
  • the buffer region 38 extends in a layered manner along the second main surface 36B and is exposed from parts of the first to fourth side surfaces 18A to 18D (see FIG. 3).
  • the buffer region 38 has a higher n-type impurity concentration than the semiconductor layer 36.
  • the n-type impurity concentration of the buffer region 38 may be, for example, not less than 1 ⁇ 10 15 cm -3 and not more than 1 ⁇ 10 17 cm -3 .
  • the semiconductor layer 36 includes a first region R1 corresponding to each IGBT region 22, a second region R2 corresponding to each diode region 24, a third region R3 corresponding to the boundary region 26, and a fourth region R4 corresponding to the peripheral region 28 (see FIG. 5).
  • Each IGBT region 22 includes a p-type collector region 40 formed in a surface layer portion of the second main surface 36B.
  • the collector region 40 is formed in the entire region of the second main surface 36B corresponding to each IGBT region 22.
  • the p-type impurity concentration of the collector region 40 may be 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type corresponds to the "second conductivity type.”
  • the collector region 40 exposed from the second main surface 36B is electrically connected to a collector electrode CL.
  • Each IGBT region 22 includes a p-type base region 42 formed in a surface layer portion of the first main surface 36A.
  • the base region 42 may be referred to as a "body region” or a "channel region.”
  • the p-type impurity concentration of the base region 42 may be higher than the n-type impurity concentration of the semiconductor layer 36.
  • the p-type impurity concentration of the base region 42 may be, for example, not less than 1 ⁇ 10 15 cm -3 and not more than 1 ⁇ 10 18 cm -3 .
  • the RC-IGBT 10 includes a first trench electrode structure 44 formed on the first main surface 36A in each IGBT region 22.
  • each IGBT region 22 may include multiple first trench electrode structures 44.
  • the first trench electrode structure 44 may be referred to as a "gate trench structure.” A gate potential is applied to the first trench electrode structure 44.
  • the multiple first trench electrode structures 44 are spaced apart from one another in the Y direction in a plan view. Each first trench electrode structure 44 is formed in a band shape extending in the X direction in a plan view. In this way, the multiple first trench electrode structures 44 are arranged in stripes extending in the X direction. Each first trench electrode structure 44 penetrates the base region 42 so as to reach the semiconductor layer 36 in a cross-sectional view cut in the YZ plane (hereinafter simply referred to as "cross-sectional view").
  • the multiple first trench electrode structures 44 may be arranged at intervals of 1 ⁇ m or more and 10 ⁇ m or less in the Y direction. Each first trench electrode structure 44 may have a width of 0.5 ⁇ m or more and 3 ⁇ m or less. Each first trench electrode structure 44 may have a depth of 1 ⁇ m or more and 10 ⁇ m or less.
  • the width of each first trench electrode structure 44 can be defined by the dimension in the X direction of the first trench electrode structure 44 in a planar view.
  • the first trench electrode structure 44 includes a first trench 46 , a first insulating film 48 , and a first buried electrode 50 .
  • the first trench 46 extends in the Z direction from the first main surface 36A to the second main surface 36B.
  • the first trench 46 defines the wall surface of the first trench electrode structure 44.
  • the first trench 46 includes a bottom wall and a side wall.
  • the side wall has a constant opening width from the opening of the first trench 46 to the bottom wall.
  • the opening width of the bottom wall narrows toward the second main surface 36B.
  • the bottom wall may be formed in a curved shape.
  • the shape of the first trench 46 in a cross-sectional view can be changed as desired.
  • the sidewalls may be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall.
  • the bottom wall may be formed, for example, parallel to the first main surface 36A.
  • the corners between the sidewalls and the bottom wall of the first trench 46 may be formed in a curved shape.
  • the wall surface includes the side surfaces that form the sidewalls and the bottom surface that forms the bottom wall.
  • the first insulating film 48 covers the wall surface of the first trench 46 in a film-like manner, thereby partitioning a recess space in the first trench 46.
  • the first insulating film 48 may include at least one of a silicon oxide film (SiO 2 ), a silicon nitride film (SiN), a silicon oxynitride film (SiON), and an aluminum oxide film (Al 2 O 3 ).
  • the first insulating film 48 includes a silicon oxide film formed by an oxide of the semiconductor substrate 12.
  • the first buried electrode 50 is embedded in the first trench 46 with the first insulating film 48 in between.
  • a gate potential is applied to the first buried electrode 50.
  • the first buried electrode 50 may include conductive polysilicon.
  • the first buried electrode 50 faces the semiconductor layer 36 and the base region 42 with the first insulating film 48 in between.
  • the RC-IGBT 10 includes two trench connection structures (not shown) electrically connected to the multiple first trench electrode structures 44 in each IGBT region 22.
  • each IGBT region 22 can be said to include two trench connection structures.
  • each first trench electrode structure 44 includes a first end and a second end that constitute both ends in the X direction.
  • One trench connection structure connects the first ends of the multiple first trench electrode structures 44 to each other.
  • the other trench connection structure connects the second ends of the multiple first trench electrode structures 44 to each other.
  • Each trench connection structure is formed in a band shape extending in the Y direction in a plan view. The configuration of each trench connection structure is, for example, the same as that of the first trench electrode structure 44.
  • the RC-IGBT 10 includes a plurality of second trench electrode structures 52 formed on the first main surface 36A in each IGBT region 22.
  • the second trench electrode structures 52 may be referred to as "emitter trench structures.”
  • a potential different from the gate potential (emitter potential in the first embodiment) is applied to the second trench electrode structures 52.
  • the RC-IGBT 10 can be said to include a first trench electrode structure 44 to which a first potential is applied, and a second trench electrode structure 52 to which a second potential different from the first potential is applied.
  • the first potential corresponds to the gate potential
  • the second potential corresponds to the emitter potential.
  • the second trench electrode structures 52 are spaced apart from one another in the Y direction in a plan view. Each second trench electrode structure 52 is formed in a band shape extending in the X direction in a plan view. In this way, the second trench electrode structures 52 are arranged in stripes extending in the X direction. Each second trench electrode structure 52 penetrates the base region 42 so as to reach the semiconductor layer 36 in a cross-sectional view.
  • the multiple first trench electrode structures 44 and the multiple second trench electrode structures 52 are arranged alternately one by one in the Y direction.
  • One second trench electrode structure 52 is formed, for example, in a mesa region partitioned by the first trench electrode structures 44 and the trench connection structure on both sides of the second trench electrode structure 52 in the Y direction.
  • the second trench electrode structure 52 is arranged spaced apart in the X direction from the trench connection structure. For this reason, the length in the X direction of each second trench electrode structure 52 is shorter than the length in the X direction of each first trench electrode structure 44.
  • the second trench electrode structures 52 may be arranged at intervals of 1.5 ⁇ m or more and 15 ⁇ m or less in the Y direction.
  • the width of each second trench electrode structure 52 is equal to the width of each first trench electrode structure 44.
  • the width of the second trench electrode structure 52 can be defined by the dimension of the second trench electrode structure 52 in the X direction in a plan view.
  • the depth of each second trench electrode structure 52 is equal to the depth of each first trench electrode structure 44.
  • Each second trench electrode structure 52 includes a second trench 54, a second insulating film 56, and a second buried electrode 58.
  • the configuration and material of the second trench 54, the second insulating film 56, and the second buried electrode 58 are the same as the configuration and material of the first trench 46, the first insulating film 48, and the first buried electrode 50.
  • the shapes of the second trench 54, the second insulating film 56, and the second buried electrode 58 in a cross-sectional view are the same as the shapes of the first trench 46, the first insulating film 48, and the first buried electrode 50 in a cross-sectional view. For this reason, detailed descriptions of the second trench 54, the second insulating film 56, and the second buried electrode 58 are omitted. However, an emitter potential is applied to the second buried electrode 58.
  • the RC-IGBT 10 includes a plurality of n-type emitter regions 60 formed in the surface layer portion of the base region 42 in each IGBT region 22. That is, it can be said that each IGBT region 22 includes an emitter region 60.
  • the emitter regions 60 are respectively disposed between the first trench electrode structure 44 and the second trench electrode structure 52 in the Y direction.
  • Each emitter region 60 is formed in a strip shape extending in the X direction along the first trench electrode structure 44 (second trench electrode structure 52).
  • Each emitter region 60 has a higher n-type impurity concentration than the semiconductor layer 36.
  • the n-type impurity concentration of each emitter region 60 may be, for example, 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the RC-IGBT 10 includes multiple n-type CS regions 62 (carrier storage regions) formed in the region directly below the base region 42 in each IGBT region 22. That is, each IGBT region 22 includes a CS region 62.
  • the multiple CS regions 62 suppress the discharge of carriers (positive holes) to the base region 42, and promote the accumulation of carriers (positive holes) in the region directly below the multiple first trench electrode structures 44.
  • the multiple CS regions 62 promote low on-resistance and low on-voltage from within the semiconductor substrate 12.
  • the CS regions 62 may be referred to as "accumulation regions" that promote carrier accumulation.
  • the CS region 62 is disposed between the first trench electrode structure 44 and the second trench electrode structure 52 in the Y direction. Each CS region 62 is formed in a strip shape extending in the X direction along the first trench electrode structure 44 (second trench electrode structure 52). The multiple CS regions 62 are formed in the region between the bottom of the base region 42 and the bottom wall of the first trench electrode structure 44 (second trench electrode structure 52) in the Z direction. In one example, the multiple CS regions 62 are formed apart from the bottom wall of the first trench electrode structure 44 (second trench electrode structure 52). In one example, the bottoms of the multiple CS regions 62 are located closer to the bottom of the first trench electrode structure 44 (second trench electrode structure 52) than the middle part of the first trench electrode structure 44 (second trench electrode structure 52) in the Z direction.
  • the multiple CS regions 62 have a lower n-type impurity concentration than the emitter region 60.
  • the n-type impurity concentration of the multiple CS regions 62 may be, for example, not less than 1 ⁇ 10 15 cm ⁇ 3 and not more than 1 ⁇ 10 17 cm ⁇ 3 .
  • each IGBT region 22 includes a transistor structure including a p-type base region 42 formed on the first main surface 36A, an n-type emitter region 60 formed in the base region 42, and a first buried electrode 50 facing the base region 42 and the emitter region 60 via a first insulating film 48.
  • the first insulating film 48 corresponds to the "gate insulating layer”
  • the first buried electrode 50 corresponds to the "gate electrode.”
  • the RC-IGBT 10 includes a plurality of contact holes 64 formed in the first main surface 36A in each IGBT region 22.
  • the contact holes 64 are formed between the first trench electrode structure 44 and the second trench electrode structure 52 in the Y direction. Each contact hole 64 may penetrate the emitter region 60 to reach the base region 42.
  • Each contact hole 64 is formed in a strip shape extending in the X direction, for example, in a plan view.
  • the RC-IGBT 10 includes a plurality of p-type contact regions 66 formed in a region different from the plurality of emitter regions 60 in the surface layer portion of the base region 42 in each IGBT region 22.
  • the IGBT region 22 includes a plurality of contact regions 66.
  • the plurality of contact regions 66 are each formed in a region along the corresponding contact hole 64 in a planar view.
  • the plurality of contact regions 66 are each formed in a band shape extending along the corresponding contact hole 64 in a planar view.
  • each contact region 66 is formed in a region between the bottom wall of the contact hole 64 and the bottom of the base region 42 in the Z direction.
  • Each contact region 66 has a higher p-type impurity concentration than the base region 42.
  • the p-type impurity concentration of each contact region 66 may be, for example, not less than 1 ⁇ 10 19 cm ⁇ 3 and not more than 1 ⁇ 10 20 cm ⁇ 3 .
  • the RC-IGBT 10 includes an n-type cathode region 68 formed in a surface layer portion of the second main surface 36B in each diode region 24. That is, each diode region 24 includes a cathode region 68.
  • the cathode region 68 penetrates the collector region 40 so as to be connected to the buffer region 38.
  • the cathode region 68 has a higher n-type impurity concentration than the semiconductor layer 36 (buffer region 38).
  • the n-type impurity concentration of the cathode region 68 may be, for example, not less than 1 ⁇ 10 19 cm -3 and not more than 1 ⁇ 10 20 cm -3 .
  • the RC-IGBT 10 includes a p-type anode region 70 formed in a surface layer portion of the first main surface 36A in each diode region 24. That is, each diode region 24 includes the anode region 70.
  • the anode region 70 faces the cathode region 68 in the Z direction. In one example, the entire area of the anode region 70 faces at least a part of the cathode region 68. In one example, the depth of the anode region 70 is equal to the depth of the base region 42.
  • the p-type impurity concentration of the anode region 70 may be, for example, not less than 1 ⁇ 10 15 cm ⁇ 3 and not more than 1 ⁇ 10 18 cm ⁇ 3 .
  • the position, depth, and impurity concentration of the anode region 70 can be changed as desired.
  • the anode region 70 may face a part of the collector region 40 and a part of the cathode region 68 in the Z direction.
  • the anode region 70 may be formed deeper than the base region 42 in the Z direction.
  • the p-type impurity concentration of the anode region 70 may be higher than the p-type impurity concentration of the base region 42.
  • the p-type impurity concentration of the anode region 70 may be lower than the p-type impurity concentration of the base region 42.
  • the anode region 70 forms a pn junction with the semiconductor layer 36. This forms a pn junction diode with the anode region 70 as the anode and the cathode region 68 (semiconductor layer 36) as the cathode.
  • the RC-IGBT 10 includes a plurality of third trench electrode structures 72 formed on the first main surface 36A in each diode region 24.
  • the third trench electrode structures 72 may be referred to as "anode trench structures.”
  • a potential different from the gate potential (anode potential in the first embodiment) is applied to the third trench electrode structures 72.
  • the anode potential may be the same potential as the emitter potential.
  • the multiple third trench electrode structures 72 penetrate the anode region 70 so as to reach the semiconductor layer 36 in a cross-sectional view.
  • the multiple third trench electrode structures 72 are arranged spaced apart from each other in the Y direction in a plan view.
  • Each third trench electrode structure 72 is formed in a band shape extending in the X direction in a plan view. In other words, the multiple third trench electrode structures 72 are arranged in a stripe shape extending in the X direction.
  • the X-direction length of each third trench electrode structure 72 is shorter than the X-direction length of the first trench electrode structure 44.
  • the X-direction length of each third trench electrode structure 72 is equal to the X-direction length of the second trench electrode structure 52.
  • the spacing between the multiple third trench electrode structures 72 is equal to the spacing in the Y direction between the first trench electrode structure 44 and the second trench electrode structure 52.
  • the width of each third trench electrode structure 72 is equal to the width of each first trench electrode structure 44.
  • the depth of each third trench electrode structure 72 is equal to the depth of each first trench electrode structure 44. Note that each of the spacing between the multiple third trench electrode structures 72, the width of each third trench electrode structure 72, and the depth of each third trench electrode structure 72 can be changed arbitrarily.
  • Each third trench electrode structure 72 includes a third trench 74, a third insulating film 76, and a third buried electrode 78.
  • the configuration and material of the third trench 74, the third insulating film 76, and the third buried electrode 78 are the same as, for example, the configuration and material of the first trench 46, the first insulating film 48, and the first buried electrode 50.
  • the shapes of the third trench 74, the third insulating film 76, and the third buried electrode 78 in a cross-sectional view are the same as, for example, the shapes of the first trench 46, the first insulating film 48, and the first buried electrode 50 in a cross-sectional view. For this reason, detailed descriptions of the third trench 74, the third insulating film 76, and the third buried electrode 78 are omitted. However, an anode potential is applied to the third buried electrode 78.
  • the RC-IGBT 10 includes two anode trench connection structures (not shown) formed on the first main surface 36A in each diode region 24 so as to be electrically connected to the multiple third trench electrode structures 72.
  • each diode region 24 can be said to include two anode trench connection structures.
  • each third trench electrode structure 72 includes a first end and a second end that constitute both ends in the X direction.
  • One anode trench connection structure connects the first ends of the multiple third trench electrode structures 72 to each other.
  • the other anode trench connection structure connects the second ends of the multiple third trench electrode structures 72 to each other.
  • Each anode trench connection structure is formed in a band shape extending in the Y direction in a plan view. The configuration of each anode trench connection structure is, for example, the same as that of the third trench electrode structure 72.
  • the RC-IGBT 10 includes a plurality of contact holes 80 formed in the first main surface 36A in each diode region 24.
  • the contact holes 80 are formed between the third trench electrode structures 72 in the Y direction.
  • Each contact hole 80 is formed so as to reach the anode region 70.
  • Each contact hole 80 is formed in a band shape extending in the X direction, for example, in a plan view.
  • the RC-IGBT 10 includes a plurality of p-type contact regions 82 formed in the surface layer portion of the anode region 70 in each diode region 24. That is, the diode region 24 includes a plurality of contact regions 82.
  • the plurality of contact regions 82 are each formed in a region that follows the corresponding contact hole 80 in a plan view.
  • the plurality of contact regions 82 are each formed in a band shape that extends along the corresponding contact hole 80 in a plan view.
  • each contact region 82 is formed in a region between the bottom wall of the contact hole 80 and the bottom of the anode region 70 in the Z direction.
  • Each contact region 82 has a higher p-type impurity concentration than the anode region 70.
  • the p-type impurity concentration of each contact region 82 is equal to the p-type impurity concentration of the contact region 66 of the IGBT region 22.
  • the p-type impurity concentration of each contact region 82 may be, for example, not less than 1 ⁇ 10 19 cm ⁇ 3 and not more than 1 ⁇ 10 20 cm ⁇ 3 .
  • the RC-IGBT 10 includes a plurality of fourth trench electrode structures 84 formed on the first main surface 36A in each boundary region 26.
  • Each of the fourth trench electrode structures 84 extends in the Z direction so as to reach the semiconductor layer 36 in a cross-sectional view.
  • the plurality of fourth trench electrode structures 84 are arranged spaced apart from each other in the Y direction in a plan view.
  • Each of the fourth trench electrode structures 84 is formed in a band shape extending in the X direction in a plan view. That is, the plurality of fourth trench electrode structures 84 are arranged in a stripe shape extending in the X direction.
  • the length in the X direction of each of the fourth trench electrode structures 84 is shorter than the length in the X direction of each of the first trench electrode structures 44.
  • Each fourth trench electrode structure 84 is electrically connected to two anode trench connection structures. More specifically, each fourth trench electrode structure 84 includes a first end and a second end that constitute both ends in the X direction. One anode trench connection structure connects the first ends of the multiple fourth trench electrode structures 84 to each other. The other anode trench connection structure connects the second ends of the multiple fourth trench electrode structures 84 to each other.
  • the spacing between the multiple fourth trench electrode structures 84 is equal to the spacing in the Y direction between the first trench electrode structure 44 and the second trench electrode structure 52.
  • the width of each fourth trench electrode structure 84 is equal to the width of each first trench electrode structure 44.
  • the depth of each fourth trench electrode structure 84 is equal to the depth of each first trench electrode structure 44. Note that each of the spacing between the multiple fourth trench electrode structures 84, the width of each fourth trench electrode structure 84, and the depth of each fourth trench electrode structure 84 can be changed arbitrarily.
  • Each fourth trench electrode structure 84 includes a fourth trench 86, a fourth insulating film 88, and a fourth buried electrode 90.
  • the configuration and material of the fourth trench 86, the fourth insulating film 88, and the fourth buried electrode 90 are the same as the configuration and material of the first trench 46, the first insulating film 48, and the first buried electrode 50.
  • the shapes of the fourth trench 86, the fourth insulating film 88, and the fourth buried electrode 90 in a cross-sectional view are the same as the shapes of the first trench 46, the first insulating film 48, and the first buried electrode 50 in a cross-sectional view. For this reason, detailed descriptions of the fourth trench 86, the fourth insulating film 88, and the fourth buried electrode 90 are omitted. However, an anode potential is applied to the fourth buried electrode 90.
  • the RC-IGBT 10 includes a plurality of p-type boundary well regions 92 formed on the first main surface 36A in each boundary region 26.
  • the boundary region 26 includes a plurality of boundary well regions 92.
  • the plurality of boundary well regions 92 are formed between the plurality of fourth trench electrode structures 84 in the Y direction.
  • the boundary well regions 92 are formed in a mesa region partitioned by a pair of fourth trench electrode structures 84 and a pair of anode trench connection structures.
  • the boundary well region 92 is formed in a layer shape extending along the first main surface 36A in each boundary region 26.
  • the boundary well region 92 faces the collector region 40 in the Z direction. In one example, the entire area of the boundary well region 92 faces the collector region 40 in the Z direction. In one example, the depth of the boundary well region 92 is equal to the depth of the base region 42.
  • the boundary well region 92 has a p-type impurity concentration higher than the p-type impurity concentration of the anode region 70.
  • the p-type impurity concentration of the boundary well region 92 may be 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the boundary well region 92 is in an electrically floating state.
  • the position, depth, and impurity concentration of the boundary well region 92 can be changed as desired.
  • the boundary well region 92 may face a part of the collector region 40 and a part of the cathode region 68 in the Z direction.
  • the boundary well region 92 may be formed deeper than the base region 42 in the Z direction.
  • the p-type impurity concentration of the boundary well region 92 may be lower than the p-type impurity concentration of the anode region 70.
  • the p-type impurity concentration of the boundary well region 92 may be equal to the p-type impurity concentration of the anode region 70.
  • the boundary well region 92 forms a boundary IE structure (Injection Enhanced structure) in each boundary region 26. More specifically, the boundary well region 92 forms a boundary IE structure together with the multiple fourth trench electrode structures 84, and separates the first trench electrode structure 44 adjacent to the boundary well region 92 (third region R3) in the IGBT region 22 (first region R1) from the third trench electrode structure 72 adjacent to the boundary well region 92 (third region R3) in the diode region 24 (second region R2).
  • the boundary IE structure promotes the accumulation of holes in the region directly below the base region 42 by restricting the movement path of holes flowing into the base region 42 in the boundary region 26.
  • the RC-IGBT 10 includes a plurality of contact holes 94 formed in the first main surface 36A in each boundary region 26.
  • the contact holes 94 are formed between the plurality of fourth trench electrode structures 84 in the Y direction.
  • Each contact hole 94 is formed to reach the boundary well region 92.
  • Each contact hole 94 is formed in a band shape extending in the X direction, for example, in a plan view.
  • the RC-IGBT 10 includes a plurality of p-type contact regions 96 formed in the surface layer of the boundary well region 92 in each boundary region 26.
  • the boundary region 26 includes a plurality of contact regions 96.
  • the plurality of contact regions 96 are each formed in a region that is aligned with the corresponding contact hole 94 in a planar view.
  • the plurality of contact regions 96 are each formed in a band shape that extends along the corresponding contact hole 94 in a planar view.
  • each contact region 96 is formed in a region between the bottom wall of the contact hole 94 and the bottom of the boundary well region 92 in the Z direction.
  • Each contact region 96 has a higher p-type impurity concentration than the boundary well region 92.
  • the p-type impurity concentration of each contact region 96 is equal to the p-type impurity concentration of the contact region 66 of the IGBT region 22.
  • the p-type impurity concentration of each contact region 96 may be, for example, not less than 1 ⁇ 10 19 cm ⁇ 3 and not more than 1 ⁇ 10 20 cm ⁇ 3 .
  • the RC-IGBT 10 includes a main surface insulating film 98 that selectively covers the first main surface 36A.
  • the main surface insulating film 98 is continuous with the insulating films 48, 56, 76, and 88 of the trench electrode structures 44, 52, 72, and 84.
  • the main surface insulating film 98 covers the emitter region 60 of each IGBT region 22, the anode region 70 of each diode region 24, and the boundary well region 92 of each boundary region 26.
  • the thickness of the main surface insulating film 98 is equal to the thickness of each insulating film 48, 56, 76, and 88.
  • the main surface insulating film 98 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film.
  • the main surface insulating film 98 includes a silicon oxide film formed by an oxide of the semiconductor substrate 12.
  • the main surface insulating film 98 has a single-layer structure constituted by a single insulating film.
  • the RC-IGBT 10 includes an interlayer insulating film 100 covering the main surface insulating film 98.
  • the interlayer insulating film 100 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film.
  • the interlayer insulating film 100 may include at least one of an NSG (Non-doped Silicate Glass) film, a PSG (Phosphor Silicate Glass) film, and a BPSG (Boron Phosphor Silicate Glass) film.
  • the interlayer insulating film 100 has a single-layer structure formed of a single insulating film, or a layered structure including multiple insulating films.
  • the interlayer insulating film 100 has a thickness thicker than the main surface insulating film 98.
  • the thickness of the interlayer insulating film 100 may be 0.5 ⁇ m or more and 5 ⁇ m or less. In one example, the thickness of the interlayer insulating film 100 is 1 ⁇ m or more.
  • the interlayer insulating film 100 covers each of the trench electrode structures 44, 52, 72, and 84.
  • the interlayer insulating film 100 selectively covers each of the emitter regions 60, each of the anode regions 70, and each of the boundary well regions 92.
  • the interlayer insulating film 100 includes a plurality of first openings 102, a plurality of second openings 104, and a plurality of third openings 106.
  • the plurality of first openings 102 expose the plurality of emitter regions 60 individually and are connected to the corresponding contact holes 64.
  • the plurality of second openings 104 expose the plurality of anode regions 70 individually and are connected to the corresponding contact holes 80.
  • the plurality of third openings 106 expose the plurality of boundary well regions 92 individually and are connected to the corresponding contact holes 94.
  • the number, shape, and size of each of the first openings 102, each of the second openings 104, and each of the third openings 106 can be changed arbitrarily.
  • the RC-IGBT 10 includes a plurality of first plug electrodes 108 embedded in the plurality of first openings 102, a plurality of second plug electrodes 110 embedded in the plurality of second openings 104, and a plurality of third plug electrodes 112 embedded in the plurality of third openings 106.
  • the first plug electrode 108 is embedded in the contact hole 64 through the first opening 102, and is thus electrically connected to the emitter region 60 and the contact region 66.
  • the second plug electrode 110 is embedded in the contact hole 80 through the second opening 104, and is thus electrically connected to the anode region 70 and the contact region 82.
  • the third plug electrode 112 is embedded in the contact hole 94 through the third opening 106, and is thus electrically connected to the boundary well region 92 and the contact region 96.
  • Each plug electrode 108, 110, 112 may have a layered structure including a first electrode portion and a second electrode portion.
  • the first electrode portion is formed in a film shape along the wall surfaces constituting each opening 102, 104, 106 and each contact hole 64, 80, 94.
  • the second electrode portion is formed so as to fill the recess space partitioned by the first electrode portion.
  • the first electrode portion has a layered structure of one metal film or multiple metal films.
  • the first electrode portion may include a titanium-based metal film.
  • the first electrode portion may have a single layer structure composed of a titanium film or a titanium nitride (TiN) film.
  • the first electrode portion may have a layered structure including a titanium film and a titanium nitride film stacked in any order.
  • the second electrode portion may include at least one of tungsten, molybdenum (Mo), nickel, pure aluminum (aluminum with a purity of 99% or more), pure copper (copper with a purity of 99% or more), an aluminum alloy, and a copper alloy.
  • the second electrode portion may include at least one of an AlCu alloy, an AlSi alloy, and an AlSiCu alloy, as an example of an aluminum alloy (copper alloy).
  • the material constituting the second electrode portion is different from the material constituting the first electrode portion.
  • the second electrode portion is formed of tungsten.
  • An emitter electrode EM is formed on the interlayer insulating film 100 in the active region 20. The emitter electrode EM is in contact with each of the plug electrodes 108, 110, and 112.
  • FIG. 5 shows an example of a cross-sectional structure of the diode region 24 and the peripheral region 28.
  • the RC-IGBT 10 includes at least one p-type field region 120 formed in the surface layer of the first main surface 36A as a termination structure that relieves electric field concentration in the outer peripheral region 28.
  • a portion of the field region 120 (the inner peripheral end portion) may extend into the first end diode region 24A.
  • a portion of the field region 120 may extend into the active region 20.
  • the RC-IGBT 10 includes a plurality of field regions 120.
  • the plurality of field regions 120 are formed in a ring shape surrounding the active region 20 in a plan view.
  • the plurality of field regions 120 may have a higher p-type impurity concentration than the base region 42 (see FIG. 4).
  • the plurality of field regions 120 may have a higher p-type impurity concentration than the anode region 70.
  • the plurality of field regions 120 are in an electrically floating state.
  • the field regions 120 are formed deeper than the base region 42. In one example, the field regions 120 are formed deeper than the anode region 70. In one example, the outermost field region 120 of the field regions 120 is formed wider than the other field regions 120.
  • the RC-IGBT 10 includes, as a termination structure, an n-type channel stop region 122 formed in the surface layer of the first main surface 36A in the peripheral region 28.
  • the channel stop region 122 is formed away from the multiple field regions 120 on the peripheral side of the semiconductor substrate 12.
  • the channel stop region 122 has a higher n-type impurity concentration than the semiconductor layer 36.
  • the channel stop region 122 is formed in a ring shape surrounding the multiple field regions 120 in a plan view.
  • the channel stop region 122 may be exposed from the first to fourth side surfaces 18A to 18D (see FIG. 3) of the semiconductor substrate 12.
  • the RC-IGBT 10 includes a peripheral insulating film 124 that covers the first main surface 36A in the peripheral region 28.
  • the peripheral insulating film 124 is composed of the main surface insulating film 98 and the interlayer insulating film 100 in the active region 20.
  • the peripheral insulating film 124 includes at least one field opening 126 that selectively exposes each field region 120.
  • a plurality of field openings 126 expose the field region 120 for one field region 120.
  • Each field opening 126 is formed in a ring shape extending along the corresponding field region 120.
  • the RC-IGBT 10 includes a field connection electrode 128 electrically connected to the field region 120.
  • a plurality of field connection electrodes 128 are provided corresponding to the plurality of field regions 120.
  • the field connection electrodes 128 are in contact with the field region 120 by being embedded in the field opening 126.
  • Each field connection electrode 128 is in an electrically floating state.
  • Each field connection electrode 128 has a layered structure of one metal film or multiple metal films.
  • Each field connection electrode 128 may include at least one of titanium, tungsten, aluminum, and copper.
  • each field connection electrode 128 has a layered structure including a titanium-based metal film and a tungsten-based metal film.
  • the RC-IGBT 10 includes, as a termination structure, a number of field electrodes 130 formed on the peripheral insulating film 124.
  • the multiple field electrodes 130 are formed individually corresponding to the multiple field regions 120.
  • One field electrode 130 is connected to each of the multiple field connection electrodes 128 connected to one field region 120.
  • the multiple field electrodes 130 are individually electrically connected to the multiple field regions 120.
  • Each field electrode 130 is in an electrically floating state.
  • Each field electrode 130 is formed in an annular shape extending along the corresponding field region 120.
  • the outermost field electrode 130 of the multiple field electrodes 130 includes an extension portion 132 that is extended toward the peripheral edge of the semiconductor substrate 12. As a result, the outermost field electrode 130 is formed to be wider than the other field electrodes 130.
  • Each field electrode 130 has a layered structure including one metal film or multiple metal films.
  • Each field electrode 130 may include at least one of titanium, tungsten, aluminum, and copper.
  • each field electrode 130 has a layered structure including a titanium-based metal film and an aluminum-based metal film.
  • the peripheral insulating film 124 includes a channel stop opening 134 that exposes the channel stop region 122.
  • the outer edge of the peripheral insulating film 124 is slightly smaller than the semiconductor substrate 12 in a plan view.
  • the RC-IGBT 10 includes a channel stop electrode 136 formed on the peripheral insulating film 124 as a termination structure.
  • the channel stop electrode 136 penetrates the channel stop opening 134 and contacts the channel stop region 122. This allows the channel stop electrode 136 to be electrically connected to the channel stop region 122.
  • the channel stop electrode 136 is formed in a ring shape extending along the channel stop region 122 in a plan view.
  • the channel stop electrode 136 has a layered structure of one metal film or multiple metal films.
  • the channel stop electrode 136 may include at least one of titanium, tungsten, aluminum, and copper. In one example, the channel stop electrode 136 may have a layered structure including a titanium-based metal film and an aluminum-based metal film.
  • crystal defects 138 are formed in the semiconductor layer 36. Because the lifetime control region 30 is formed across the diode region 24, the boundary region 26, and the peripheral region 28, the crystal defects 138 are present in the second region R2, the third region R3, and the fourth region R4 of the semiconductor layer 36.
  • the crystal defect 138 is formed across the boundary region 26 and the diode region 24. In other words, the crystal defect 138 is formed across the second region R2 and the third region R3. In one example, the crystal defect 138 is formed across the entire area of each of the diode regions 24 and each of the boundary regions 26 in a planar view. In other words, the crystal defect 138 is formed across the entire area of the second region R2 and the third region R3 in a planar view.
  • the crystal defect 138 is formed closer to the second main surface 36B in the Z direction than the third trench electrode structure 72 and the fourth trench electrode structure 84.
  • the crystal defect 138 is separated from the third trench electrode structure 72 and the fourth trench electrode structure 84 in the Z direction.
  • the crystal defect 138 is formed across the first end diode region 24A and the outer peripheral region 28.
  • the crystal defect 138 is formed across the region of the second region R2 corresponding to the first end diode region 24A and the fourth region R4 adjacent to this region.
  • the crystal defect 138 is formed in the entire region of each of the first end diode region 24A and the outer peripheral region 28 in a planar view.
  • the crystal defect 138 is formed in the region of the second region R2 corresponding to the first end diode region 24A and the entire region of the fourth region R4 in a planar view. It can be said that the crystal defect 138 is formed in the entire lifetime control region 30 in a planar view.
  • the crystal defect 138 is formed, for example, in the Z direction closer to the second major surface 36B than the field region 120 and the channel stop region 122.
  • the crystal defect 138 is separated from the field region 120 and the channel stop region 122 in the Z direction.
  • the manufacturing method of the RC-IGBT 10 includes a step of preparing an n-type wafer 200, which is the base of the semiconductor substrate 12.
  • the wafer 200 may be an FZ (Floating Zone) substrate formed through an FZ method.
  • the wafer 200 has a first wafer main surface 202 and a second wafer main surface 204.
  • the first wafer main surface 202 and the second wafer main surface 204 correspond to the first main surface 14 and the second main surface 16 of the semiconductor substrate 12, respectively.
  • an active region 20 and a peripheral region 28 are set in the wafer 200. In other words, the wafer 200 is partitioned into the active region 20 and the peripheral region 28.
  • the manufacturing method of the RC-IGBT 10 includes a process of forming, in the active region 20, IGBT regions 22 and multiple diode regions 24 aligned in the Y direction, and a boundary region 26 formed between the IGBT regions 22 and diode regions 24 adjacent to each other in the Y direction. The details of this process are described below.
  • a plurality of first trenches 46, a plurality of second trenches 54, a plurality of third trenches 74, and a plurality of fourth trenches 86 are formed in the active region 20.
  • a hard mask (not shown) having a predetermined pattern is formed on the first wafer main surface 202.
  • the hard mask exposes the areas of the first wafer main surface 202 where the first to fourth trenches 46, 54, 74, and 86 are to be formed, and covers the other areas.
  • the hard mask may be formed of an inorganic insulating film.
  • unnecessary portions of the wafer 200 are removed by an etching method using the hard mask. At least one of a dry etching method and a wet etching method may be used as the etching method. After the first to fourth trenches 46, 54, 74, and 86 are formed, the hard mask is removed.
  • a base insulating film 206 is formed on the first wafer main surface 202.
  • the base insulating film 206 includes a first insulating film 48, a second insulating film 56, a third insulating film 76, a fourth insulating film 88, and a main surface insulating film 98.
  • the base insulating film 206 may be formed by at least one of a CVD (Chemical Vapor Deposition) method and an oxidation process (e.g., a thermal oxidation process).
  • a base electrode film 208 is formed on the base insulating film 206.
  • the base electrode film 208 is an electrode film that serves as the base for the first buried electrode 50, the second buried electrode 58, the third buried electrode 78, and the fourth buried electrode 90.
  • the base electrode film 208 is embedded in the first to fourth trenches 46, 54, 74, and 86 with the base insulating film 206 in between, and covers the first wafer main surface 202 with the base insulating film 206 in between.
  • the base electrode film 208 includes conductive polysilicon.
  • the base electrode film 208 may be formed by a CVD method.
  • unnecessary portions of the base electrode film 208 are removed by, for example, an etching method. At least one of a dry etching method and a wet etching method is used as the etching method. By removing the unnecessary portions of the base electrode film 208, the main surface insulating film 98 is exposed. Then, the first buried electrode 50, the second buried electrode 58, the third buried electrode 78, and the fourth buried electrode 90 are formed.
  • a p-type base region 42, an n-type emitter region 60, an n-type CS region 62, a p-type anode region 70, and a p-type boundary well region 92 are formed in the surface layer of the first wafer main surface 202 in the active region 20.
  • the base region 42, the emitter region 60, and the CS region 62 are formed in the surface layer of the first wafer main surface 202 of the IGBT region 22, the anode region 70 is formed in the surface layer of the first wafer main surface 202 of the diode region 24, and the boundary well region 92 is formed in the surface layer of the first wafer main surface 202 of the boundary region 26.
  • the order of the formation process of these impurity regions is arbitrary. These impurity regions are formed by implanting n-type or p-type impurities through a resist mask (not shown) having a predetermined pattern.
  • an interlayer insulating film 100 is formed to cover the first insulating film 48, the second insulating film 56, the third insulating film 76, the fourth insulating film 88, and the main surface insulating film 98.
  • the interlayer insulating film 100 may be formed by, for example, a CVD method.
  • a resist mask 210 having a predetermined pattern is formed on the interlayer insulating film 100.
  • the resist mask 210 exposes the areas where the first opening 102, the second opening 104, and the third opening 106 are to be formed, and covers the areas other than those areas.
  • unnecessary portions of the interlayer insulating film 100 are removed by an etching method using the resist mask 210. At least one of a dry etching method and a wet etching method may be used as the etching method.
  • the main surface insulating film 98 is exposed. As a result, a first opening 102, a second opening 104, and a third opening 106 are formed in the interlayer insulating film 100.
  • the first wafer main surface 202 exposed from the first opening 102, the second opening 104, and the third opening 106 is removed by etching.
  • At least one of dry etching and wet etching may be used as the etching method. This results in the formation of a contact hole 64 communicating with the first opening 102, a contact hole 80 communicating with the second opening 104, and a contact hole 94 communicating with the third opening 106.
  • p-type impurities are implanted by ion implantation into the portions of the first wafer main surface 202 exposed through the contact holes 64, 80, 94. This forms p-type contact regions 66, 82, 96.
  • the resist mask 210 is then removed. Note that different resist masks may be used for etching the interlayer insulating film 100 and etching the wafer 200.
  • a plug electrode film 212 is formed on the interlayer insulating film 100.
  • the plug electrode film 212 is an electrode film that serves as the base for the first plug electrode 108, the second plug electrode 110, and the third plug electrode 112.
  • the plug electrode film 212 is also embedded in the multiple contact holes 64, 80, and 94.
  • the plug electrode film 212 may be formed by at least one of a sputtering method and a vapor deposition method.
  • unnecessary portions of the plug electrode film 212 are removed.
  • the unnecessary portions of the plug electrode film 212 may be removed by an etching method. At least one of a dry etching method and a wet etching method is used as the etching method.
  • a dry etching method and a wet etching method is used as the etching method.
  • portions of the plug electrode film 212 located outside the first opening 102, the second opening 104, and the third opening 106 are removed.
  • the first plug electrode 108, the second plug electrode 110, and the third plug electrode 112 are formed.
  • the principal surface electrode film 214 is formed on the interlayer insulating film 100.
  • the principal surface electrode film 214 is an electrode film that serves as the base for the emitter electrode EM and the gate electrode GT (see FIG. 1).
  • the principal surface electrode film 214 may be formed by at least one of a sputtering method and a vapor deposition method.
  • unnecessary portions of the principal surface electrode film 214 are removed by patterning using a resist mask (not shown). This forms the emitter electrode EM and the gate electrode GT.
  • an n-type buffer region 38, a p-type collector region 40, and an n-type cathode region 68 are formed in the surface layer of the second wafer main surface 204.
  • the order of the steps of forming these impurity regions is arbitrary.
  • the buffer region 38 may be formed by injecting n-type impurities into the entire surface layer of the second wafer main surface 204.
  • the collector region 40 may be formed by injecting p-type impurities into the entire IGBT region 22 and boundary region 26 in the surface layer of the second wafer main surface 204.
  • the cathode region 68 may be formed by injecting n-type impurities into the entire diode region 24 in the surface layer of the second wafer main surface 204.
  • the IGBT regions 22 and multiple diode regions 24 aligned in the Y direction, and the boundary region 26 formed between the IGBT regions 22 and diode regions 24 adjacent in the Y direction are formed in the active region 20.
  • first end diode regions 24A, 24B (see FIG. 2) that are continuous with the peripheral region 28 are formed at both ends of the active region 20 in the X direction.
  • the method for manufacturing the RC-IGBT 10 includes a step of providing a peripheral region 28 (see FIG. 5), a plurality of diode regions 24, and a lifetime control region 30 that overlaps with the boundary region 26 in a plan view within the wafer 200.
  • This process includes forming a metal mask 216 that covers the IGBT region 22 on the second wafer main surface 204 and exposes the multiple diode regions 24, the boundary region 26, and the peripheral region 28, and irradiating helium (He) onto the semiconductor layer 36 of the wafer 200 from the second wafer main surface 204 side.
  • a metal mask 216 that covers the IGBT region 22 on the second wafer main surface 204 and exposes the multiple diode regions 24, the boundary region 26, and the peripheral region 28, and irradiating helium (He) onto the semiconductor layer 36 of the wafer 200 from the second wafer main surface 204 side.
  • a metal mask 216 having a predetermined pattern is first formed on the second wafer main surface 204.
  • the metal mask 216 is in contact with the second wafer main surface 204.
  • the metal mask 216 exposes the diode region 24, the boundary region 26, and the peripheral region 28 of the second wafer main surface 204, and covers the IGBT region 22.
  • helium is irradiated toward the second wafer main surface 204.
  • crystal defects 138 are formed in each of the diode region 24, the boundary region 26, and the peripheral region 28, which are regions of the semiconductor layer 36 of the wafer 200 exposed from the metal mask 216.
  • the metal mask 216 prevents helium from being implanted into the semiconductor layer 36 of the IGBT region 22.
  • the metal mask 216 prevents helium from being implanted into the semiconductor layer 36 of the IGBT region 22.
  • no crystal defects 138 are formed in the IGBT region 22. That is, crystal defects 138 are formed in the second region R2 of the semiconductor layer 36 corresponding to the diode region 24, the third region R3 corresponding to the boundary region 26, and the fourth region R4 corresponding to the outer periphery region 28 (see FIG. 5).
  • crystal defects 138 are not formed in the first region R1 of the semiconductor layer 36 corresponding to the IGBT region 22.
  • the lifetime control region 30 is formed so as to span the first end diode regions 24A, 24B (see FIG. 3) formed at both ends of the active region 20 in the Y direction and the portion of the peripheral region 28 that is continuous with the first end diode regions 24A, 24B.
  • the position of the metal mask 216 is set so as to cover at least the IGBT region 22 and expose the diode region 24. For this reason, it is permissible for the boundary region 26 to be covered by the metal mask 216 due to misalignment of the metal mask 216. It is also permissible for a portion of the diode region 24 closer to the boundary region 26 to be covered by the metal mask 216 due to misalignment of the metal mask 216. It is also permissible for a portion of the IGBT region 22 closer to the boundary region 26 to be exposed from the metal mask 216 due to misalignment of the metal mask 216.
  • the method for manufacturing the RC-IGBT 10 includes a step of forming a collector electrode CL on the second wafer main surface 204. This step is performed after the step of providing a lifetime control region 30 in the wafer 200 (see FIG. 18).
  • the collector electrode CL is formed on the second wafer main surface 204 by at least one of a sputtering method and a vapor deposition method. After that, the wafer 200 is cut in its thickness direction by, for example, dicing, to cut out a plurality of RC-IGBTs 10. Through the above steps, the RC-IGBTs 10 are manufactured.
  • first end diode regions 24A, 24B are formed at both ends of the active region 20 in the Y direction.
  • no boundary region 26 is formed at both ends of the active region 20 in the Y direction.
  • the RC-IGBT 10 can be made smaller while maintaining the electrical characteristics of the IGBT and the diode.
  • the RC-IGBT 10 includes a semiconductor substrate 12, an active region 20 provided in the semiconductor substrate 12, and an outer periphery region 28 provided in the semiconductor substrate 12 and surrounding the active region 20 in a plan view.
  • the active region 20 includes an IGBT region 22, a plurality of diode regions 24, and a boundary region 26 formed between adjacent IGBT regions 22 and diode regions 24.
  • the RC-IGBT 10 includes a lifetime control region 30 provided in the semiconductor substrate 12 and overlapping the outer periphery region 28, the plurality of diode regions 24, and the boundary region 26 in a plan view.
  • the plurality of diode regions 24 include first end diode regions 24A, 24B, which are formed at both ends of the active region 20 in the Y direction in a plan view and are continuous with the outer periphery region 28.
  • the lifetime control region 30 includes first end regions 32A, 32B formed across the first end diode regions 24A, 24B and portions of the peripheral region 28 that are continuous with the first end diode regions 24A, 24B.
  • the first end diode regions 24A, 24B are formed at both ends of the active region 20 in the Y direction, thereby preventing the boundary region 26 from being formed at both ends of the active region 20 in the Y direction.
  • This makes it possible to improve the electrical characteristics of at least one of the IGBT and the diode.
  • the RC-IGBT 10 can be made smaller while maintaining the electrical characteristics of the IGBT and the diode.
  • the length of the boundary region 26 in the Y direction is shorter than the length of the IGBT region 22 in the Y direction and the length of the diode region 24 in the Y direction.
  • This configuration makes it possible to increase the ratio of the area of at least one of the IGBT region 22 and the diode region 24 to the area of the active region 20. This makes it possible to improve the electrical characteristics of at least one of the IGBT and the diode.
  • the length of the first end diode regions 24A, 24B in the X direction is equal to the length of the active region 20 in the X direction.
  • the IGBT region 22 is not formed at both ends of the active region 20 in the Y direction, and therefore the boundary region 26 is not formed at both ends of the active region 20 in the Y direction.
  • the RC-IGBT 10 can be made smaller while maintaining the electrical characteristics of the IGBT and the diode.
  • a method for manufacturing an RC-IGBT 10 includes the steps of: preparing a wafer 200 having a first wafer main surface 202 and a second wafer main surface 204 opposite to the first wafer main surface 202, and partitioned into an active region 20 and a peripheral region 28 surrounding the active region 20; forming, in the active region 20, IGBT regions 22 and multiple diode regions 24 aligned in the Y direction, and a boundary region 26 formed between adjacent IGBT regions 22 and diode regions 24 in the X direction; and providing, in the wafer 200, a lifetime control region 30 that overlaps with the peripheral region 28, the multiple diode regions 24, and the boundary region 26 as viewed from the Z direction.
  • the multiple diode regions 24 include first end diode regions 24A, 24B, which are formed at both ends of the active region 20 in the X direction as viewed from the Z direction and are continuous with the peripheral region 28.
  • the lifetime control region 30 is formed so as to span the first end diode regions 24A, 24B and the portion of the outer peripheral region 28 that is continuous with the first end diode regions 24A, 24B.
  • the first end diode regions 24A, 24B are formed at both ends of the active region 20 in the Y direction, thereby preventing the boundary region 26 from being formed at both ends of the active region 20 in the Y direction.
  • This makes it possible to improve the electrical characteristics of at least one of the IGBT and the diode.
  • the RC-IGBT 10 can be made smaller while maintaining the electrical characteristics of the IGBT and the diode.
  • RC-IGBT 10 of the second embodiment will be described with reference to Figures 20 and 21.
  • the RC-IGBT 10 of the second embodiment differs from the RC-IGBT 10 of the first embodiment in the range of the diode region 24 and the lifetime control region 30.
  • components common to the RC-IGBT 10 of the first embodiment are given the same reference numerals, and descriptions thereof will be omitted. Note that the hatched region in Figure 21 indicates the lifetime control region 30.
  • FIG. 20 shows an example of the planar structure of the semiconductor substrate 12 of the RC-IGBT 10.
  • FIG. 21 shows the lifetime control region 30 in FIG. 20.
  • the emitter electrode EM and the gate electrode GT are shown by two-dot chain lines to make the drawing easier to understand.
  • the diode region 24 includes first end diode regions 24A, 24B located at both ends of the active region 20 in the Y direction.
  • the diode region 24 in the second embodiment further includes second end diode regions 24D, 24E located at both ends of the active region 20 in the X direction. In a plan view, the second end diode regions 24D, 24E extend in the Y direction.
  • the second end diode regions 24D, 24E are continuous with the first end diode regions 24A, 24B and the central diode region 24C. Therefore, in the second embodiment, the outer periphery of the active region 20 can be said to be a rectangular frame-shaped diode region 24.
  • the second end diode regions 24D, 24E include regions that overlap with each IGBT region 22 when viewed from the X direction.
  • the second end diode regions 24D, 24E include regions that are aligned with each IGBT region 22 in the X direction.
  • End boundary regions 26A, 26B are formed between the second end diode regions 24D, 24E and each IGBT region 22 in the X direction in the active region 20. It can be said that the boundary region 26 includes an end boundary region 26A formed between the second end diode region 24D and the IGBT region 22 in the X direction, and an end boundary region 26B formed between the second end diode region 24E and the IGBT region 22 in the X direction.
  • the end boundary regions 26A, 26B are continuous with the boundary regions 26 formed on both sides of the IGBT region 22 in the Y direction. For this reason, the boundary region 26 in the second embodiment is formed in a rectangular frame shape surrounding the IGBT region 22 in a plan view.
  • the active region 20 includes a region in which the diode region 24, the boundary region 26, and the IGBT region 22 are aligned in the X direction.
  • the dimension in the X direction of each IGBT region 22 is smaller than the dimension in the X direction of the active region 20.
  • the dimension in the X direction of each IGBT region 22 in the second embodiment is smaller than the dimension in the X direction of each IGBT region 22 in the first embodiment.
  • the ratio of the area of the diode region 24 to the area of the active region 20 in a plan view becomes higher, while the ratio of the area of the IGBT region 22 to the area of the active region 20 becomes lower.
  • the lifetime control region 30 includes the second end diode regions 24D, 24E and the second end regions 32D, 32E formed across the portion of the peripheral region 28 that is continuous with the second end diode regions 24D, 24E.
  • the second end regions 32D, 32E extend along the Y direction in a plan view.
  • the second end regions 32D, 32E are continuous with the first end regions 32A, 32B and the central region 32C.
  • the second end regions 32D, 32E include the portion of the outer peripheral region 28 between the first end regions 32A, 32B in the Y direction, the second end diode regions 24D, 24E, and the end boundary regions 26A, 26B.
  • the second end regions 32D, 32E are formed, and therefore the dimension in the X direction of the region of the lifetime control region 30 adjacent to the first side surface 18A and the second side surface 18B in a plan view becomes larger than that of the first embodiment. Note that the second embodiment provides the same effects as the first embodiment.
  • the RC-IGBT 10 of the third embodiment differs from the RC-IGBT 10 of the first embodiment in the configurations of the emitter electrode EM and the gate electrode GT, and in the ranges of the IGBT region 22, the diode region 24, and the lifetime control region 30.
  • components common to the RC-IGBT 10 of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
  • FIG. 22 shows an example of the planar structure of an RC-IGBT 10.
  • FIG. 23 shows an example of the planar structure of a semiconductor substrate 12 of an RC-IGBT 10.
  • FIG. 24 shows the lifetime control region 30 in FIG. 23. Note that in FIGS. 23 and 24, the emitter electrode EM and the gate electrode GT are shown by two-dot chain lines to make the drawings easier to understand.
  • the gate electrode GT includes a gate pad GP and gate fingers GF1 and GF2.
  • the gate pad GP and the gate fingers GF1 and GF2 are integrally formed.
  • the gate finger GF1 includes a first portion that extends in the X direction from the end of the gate pad GP closest to the first side surface 18A toward the first side surface 18A, and a second portion that extends in the Y direction from the first portion toward the third side surface 18C.
  • the gate finger GF2 includes a third portion that extends in the X direction from the end of the gate pad GP closest to the second side surface 18B toward the second side surface 18B, and a fourth portion that extends in the Y direction from the third portion toward the third side surface 18C.
  • the emitter electrode EM includes a first slit SL1 formed to avoid the second portion of the gate finger GF1, and a second slit SL2 formed to avoid the fourth portion of the gate finger GF2.
  • the active region 20 includes one IGBT region 22, two diode regions 24, and two boundary regions 26.
  • the IGBT region 22, the diode region 24, and the boundary region 26 are arranged in the X direction.
  • the X direction corresponds to the "first direction.” Therefore, the Y direction corresponds to the "second direction.”
  • the diode region 24 is composed of first end diode regions 24A and 24B.
  • the two boundary regions 26 are formed in a distributed manner between the first end diode region 24A and the IGBT region 22 in the X direction and between the first end diode region 24B and the IGBT region 22 in the X direction.
  • the second portion of gate finger GF1 and the fourth portion of gate finger GF2, indicated by the two-dot chain line, are positioned so as to overlap both ends of the IGBT region 22 in the X direction in a plan view.
  • the second portion of gate finger GF1 and the fourth portion of gate finger GF2 are positioned in the IGBT region 22 adjacent to the boundary region 26 in the X direction.
  • the lifetime control region 30 is formed in the peripheral region 28, the first end diode regions 24A and 24B, and the boundary region 26. Therefore, the lifetime control region 30 includes a first end region 32A formed across the first end diode region 24A and a portion of the peripheral region 28 that is continuous with the first end diode region 24A in the X direction, and a first end region 32B formed across the first end diode region 24B and a portion of the peripheral region 28 that is continuous with the first end diode region 24B in the X direction. It can also be said that the gate fingers GF1 and GF2 are formed within the lifetime control region 30 in a plan view.
  • the diode region 24 is composed of first end diode regions 24A and 24B.
  • the diode region 24 and the IGBT region 22 are aligned in only two places, so the number of boundary regions 26 is two. This makes it possible to minimize the number of boundary regions 26.
  • the regions other than both ends of the active region 20 in the X direction become IGBT regions 22, it is possible to improve electrical characteristics such as reducing the on-resistance of the IGBT in the RC-IGBT 10.
  • the Y-direction dimension L2 of the central region 32C of the lifetime control region 30 can be changed arbitrarily.
  • the Y-direction dimension L2 of the central region 32C may be larger than the Y-direction dimensions LA1, LB1 of the first end regions 32A, 32B.
  • the Y-direction dimension of the central diode region 24C may be larger than the Y-direction dimensions of the first end diode regions 24A, 24B.
  • the central diode region 24C may be omitted. Accordingly, the boundary regions 26 formed on both sides of the central diode region 24C in the Y direction are omitted. In this case, the central region 32C is omitted from the lifetime control region 30.
  • the range of the second end regions 32D, 32E of the lifetime control region 30 can be changed arbitrarily.
  • the X-direction dimension of the second end regions 32D, 32E may be smaller than the Y-direction dimension of the first end regions 32A, 32B.
  • the X-direction dimension of the second end regions 32D, 32E may be larger than the Y-direction dimension of the first end regions 32A, 32B.
  • the arrangement of the diode regions 24 can be changed as desired.
  • the diode regions 24 may include a central diode region 24C, as in the first embodiment.
  • the shape of the gate electrode GT can be changed arbitrarily.
  • the number of gate fingers GF1, GF2 may be three or more.
  • at least one of the gate fingers GF1, GF2 may be omitted from the gate electrode GT.
  • the positions of the second portion of gate finger GF1 and the fourth portion of gate finger GF2 can be changed as desired.
  • the second portion of gate finger GF1 and the fourth portion of gate finger GF2 may be positioned so as to overlap boundary region 26 in a plan view.
  • the IGBT structure in the IGBT region 22 can be changed as desired.
  • the second trench electrode structure 52 can be changed to the first trench electrode structure 44.
  • the gate electrode structure is not limited to the trench electrode structure and can be changed as desired.
  • the diode structure in the diode region 24 can be changed as desired.
  • the anode electrode structure in the diode structure is not limited to the third trench electrode structure 72 and can be changed as desired.
  • the fourth trench electrode structure 84 may be omitted in the boundary region 26 .
  • the number of IGBT regions 22, diode regions 24, and boundary regions 26 can be changed as desired.
  • the active region 20 only needs to include the first end diode regions 24A and 24B.
  • the active region 20 only needs to include the first end diode regions 24A and 24B and the second end diode regions 24D and 24E.
  • the width dimensions of the IGBT region 22, the diode region 24, and the boundary region 26 can be changed as desired.
  • the width dimension of the boundary region 26 may be greater than or equal to the width dimension of the diode region 24. In another example, the width dimension of the boundary region 26 may be greater than or equal to the width dimension of the IGBT region 22.
  • the lifetime control region 30 may not include the boundary region 26.
  • the lifetime control region 30 may be configured to include the diode region 24 and the peripheral region 28.
  • the lifetime control region 30 may not include the region of the peripheral region 28 that is separated from the diode region 24.
  • the active region 20 may be formed to avoid the gate electrode GT in plan view.
  • two first end diode regions 24B are formed spaced apart from each other in the X direction.
  • the two first end diode regions 24B can also be said to be formed dispersedly on both sides of the gate electrode GT in the X direction in plan view.
  • the arrangement of the IGBT region 22, diode region 24, and boundary region 26 can be changed as desired.
  • the arrangement of the IGBT region 22, diode region 24, and boundary region 26 may be changed to that of the second or third embodiment.
  • the electrical connection structure between the emitter electrode EM and the anode region 70 in the diode region 24 can be changed as desired.
  • the electrical connection structure between the emitter electrode EM and the boundary well region 92 in the boundary region 26 can be changed as desired.
  • the second plug electrode 110, the interlayer insulating film 100, and the main surface insulating film 98 are omitted in the diode region 24.
  • the emitter electrode EM is formed in the diode region 24 so as to contact the first main surface 36A.
  • the emitter electrode EM is electrically connected to the anode region 70 and the third buried electrode 78 of the third trench electrode structure 72.
  • the third plug electrode 112, the interlayer insulating film 100, and the main surface insulating film 98 are omitted in the boundary region 26.
  • the emitter electrode EM is formed so as to contact the first main surface 36A in the boundary region 26.
  • the emitter electrode EM is electrically connected to the boundary well region 92 and the fourth buried electrode 90 of the fourth trench electrode structure 84.
  • a structure in which the conductivity types of the semiconductor layer 36, the buffer region 38, the collector region 40, the base region 42, the emitter region 60, the CS region 62, and the boundary well region 92 are inverted may be adopted.
  • the p-type regions may be made into n-type regions
  • the n-type regions may be made into p-type regions.
  • the term “on” as used in this disclosure includes the meanings “on” and “above” unless the context clearly indicates otherwise.
  • the expression “a first element is mounted on a second element” is intended to mean that in some embodiments, the first element may be directly disposed on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element.
  • the term “on” does not exclude a structure in which another element is formed between the first element and the second element.
  • the Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to be perfectly aligned with the vertical direction. Therefore, the various structures according to this disclosure are not limited to the "up” and “down” of the Z direction described in this specification being “up” and “down” in the vertical direction.
  • the X direction may be vertical
  • the Y direction may be vertical.
  • the lifetime control region (30) includes a central region (32C) formed closer to the center of the active region (20) than the first end regions (32A, 32B) in the first direction (Y direction), The RC-IGBT described in Appendix 1, wherein a dimension (LA1, LB1) of the first end region (32A, 32B) in the first direction (Y direction) is greater than a dimension (L2) of the central region (32C) in the first direction (Y direction).
  • a direction perpendicular to the first direction (Y direction) when viewed from the thickness direction (Z direction) is defined as a second direction (X direction),
  • the diode region (24) includes second end diode regions (24D, 24E) formed at both ends of the active region (20),
  • the RC-IGBT according to appendix 1 or 2 wherein the lifetime control region (30) includes a second end region (32D, 32E) formed across the second end diode region (24D, 24E) and a portion of the outer circumferential region (28) that is continuous with the second end diode region (24D, 24E).
  • the lifetime control region (30) includes a central region (32C) formed closer to the center of the active region (20) than the first end regions (32A, 32B) in the first direction (Y direction),
  • a direction perpendicular to the first direction (Y direction) when viewed from the thickness direction (Z direction) is defined as a second direction (X direction),
  • the semiconductor substrate (12) includes a semiconductor layer (36) of a first conductivity type (n-type) including a first main surface (36A) and a second main surface (36B) opposite to the first main surface (36A);
  • the IGBT region (22) includes an IGBT structure including a base region (42) of a second conductivity type (p type) formed on the first main surface (36A), an emitter region (60) of a first conductivity type (n type) formed in the base region (42), and a gate electrode (GT) facing the base region (42) and the emitter region (60) via a gate insulating layer (48), and a collector region (40) of the second conductivity type (p type) formed on the second main surface (36B);
  • the diode region (24) includes an anode region (70) of a second conductivity type (p-type) formed on the first main surface (36A) and a cathode region (68) of a first conductivity type (n-type) formed on the second main surface
  • the step of providing the lifetime control region (30) in the wafer (200) comprises: forming a metal mask (216) on the second wafer main surface (204) that covers the IGBT region (22) and exposes the plurality of diode regions (24), the boundary region (26), and the outer periphery region (28); irradiating the semiconductor layer (36) of the wafer (200) with helium from the second wafer main surface (204) side; 12.
  • [Appendix 13] Further comprising a step of forming a collector electrode (CL) on the second wafer main surface (204); The method for manufacturing an RC-IGBT according to claim 11 or 12, wherein the step of forming the collector electrode (CL) on the second wafer main surface (204) is performed after the step of providing the lifetime control region (30) in the wafer (200).
  • second trench electrode structure 54 second trench 56: second insulating film 58: second buried electrode 60: emitter region 62: CS region 64: contact hole 66: contact region 68: cathode region 70: anode region 72: third trench electrode structure 74 . . .
  • base insulating film 208 base electrode film 210... resist mask 212... plug electrode film 214... main surface electrode film 216... metal mask EM... emitter electrode SL1... first slit SL2... second slit GT... gate electrode GP: gate pad GF1, GF2: gate fingers
  • CL collector electrode
  • R1 to R4 first to fourth regions LA1, LB1: dimension of first end region in the Y direction
  • L2 dimension of central region in the Y direction

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014175517A (ja) * 2013-03-11 2014-09-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2016006854A (ja) * 2014-05-28 2016-01-14 パナソニックＩｐマネジメント株式会社 半導体素子およびその製造方法
JP2018046187A (ja) * 2016-09-15 2018-03-22 富士電機株式会社 半導体装置
WO2019098271A1 (ja) * 2017-11-16 2019-05-23 富士電機株式会社 半導体装置
JP2021190639A (ja) * 2020-06-03 2021-12-13 三菱電機株式会社 半導体装置
JP7201093B2 (ja) * 2019-09-05 2023-01-10 富士電機株式会社 半導体装置および半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014175517A (ja) * 2013-03-11 2014-09-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2016006854A (ja) * 2014-05-28 2016-01-14 パナソニックＩｐマネジメント株式会社 半導体素子およびその製造方法
JP2018046187A (ja) * 2016-09-15 2018-03-22 富士電機株式会社 半導体装置
WO2019098271A1 (ja) * 2017-11-16 2019-05-23 富士電機株式会社 半導体装置
JP7201093B2 (ja) * 2019-09-05 2023-01-10 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2021190639A (ja) * 2020-06-03 2021-12-13 三菱電機株式会社 半導体装置

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