WO2024159352A1 - 像素电路、像素驱动方法和显示装置 - Google Patents

像素电路、像素驱动方法和显示装置 Download PDF

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Publication number
WO2024159352A1
WO2024159352A1 PCT/CN2023/073816 CN2023073816W WO2024159352A1 WO 2024159352 A1 WO2024159352 A1 WO 2024159352A1 CN 2023073816 W CN2023073816 W CN 2023073816W WO 2024159352 A1 WO2024159352 A1 WO 2024159352A1
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WO
WIPO (PCT)
Prior art keywords
circuit
node
electrically connected
reset
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/073816
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English (en)
French (fr)
Inventor
袁长龙
张振华
冯靖伊
朱莉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202380008125.6A priority Critical patent/CN118786476A/zh
Priority to US18/558,487 priority patent/US12542106B2/en
Priority to PCT/CN2023/073816 priority patent/WO2024159352A1/zh
Publication of WO2024159352A1 publication Critical patent/WO2024159352A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method and a display device.
  • the pixel circuit cannot achieve high-frequency driving under the premise of fully compensating the threshold voltage of the driving transistor included in the driving circuit.
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a data writing circuit, and a compensation control circuit;
  • a first end of the first energy storage circuit is electrically connected to a first node, a second end of the first energy storage circuit is electrically connected to a second node, and the first energy storage circuit is used to store electrical energy;
  • the first end of the second energy storage circuit is electrically connected to the second node, the second end of the second energy storage circuit is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy;
  • the control end of the driving circuit is electrically connected to the first node, and the driving circuit is used to drive the light emitting element under the control of the potential of the control end;
  • the third node is electrically connected to the first electrode of the light emitting element, and the second electrode of the light emitting element is electrically connected to the first voltage terminal;
  • the data writing circuit is electrically connected to the scan line, the data line and the data writing node respectively, and is used to control the data voltage on the data line to be written into the data writing node under the control of the scan signal provided by the scan line;
  • the compensation control circuit is electrically connected to the first reset terminal, the second node and the compensation node respectively, and is used to control the connection or disconnection between the second node and the compensation node under the control of the first reset signal;
  • the compensation node is electrically connected to the third node, and/or the compensation node is electrically connected to the second end of the driving circuit; the data writing node is the second node or the third node.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first reset circuit and a second reset circuit;
  • the first reset circuit is electrically connected to the first reset terminal, the reference voltage terminal and the first node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the first reset signal provided by the first reset terminal;
  • the second reset circuit is electrically connected to the second reset terminal, the first initial voltage terminal and the reset node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the reset node under the control of the second reset signal provided by the second reset terminal;
  • the reset node is the second node or the third node.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a third reset circuit
  • the third reset circuit is electrically connected to the scan line, the second initial voltage terminal and the reset node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the reset node under the control of the scan signal;
  • the data writing node is the second node, and the reset node is the third node; or, the data writing node is the third node, and the reset node is the second node.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit
  • the first end of the driving circuit is electrically connected to the power supply voltage end through the first light emitting control circuit; the second end of the driving circuit is electrically connected to the first electrode of the light emitting element;
  • the control end of the first light-emitting control circuit is electrically connected to the light-emitting control line, and the first light-emitting control circuit is used to control the connection or disconnection between the power supply voltage end and the first end of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second light emitting control circuit
  • the first end of the driving circuit is electrically connected to the power supply voltage end, and the second end of the driving circuit is electrically connected to the first electrode of the light emitting element through the second light emitting control circuit;
  • the control end of the second light-emitting control circuit is electrically connected to the light-emitting control line, and the second light-emitting control circuit is used to control the connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line.
  • the data writing circuit includes a first transistor, and the compensation control circuit includes a second transistor;
  • the gate of the first transistor is electrically connected to the scan line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the data writing node;
  • a gate of the second transistor is electrically connected to the first reset terminal, a first electrode of the second transistor is electrically connected to the second node, and a second electrode of the second transistor is electrically connected to the compensation node.
  • the driving circuit includes a driving transistor, the first reset circuit includes a third transistor, and the second reset circuit includes a fourth transistor;
  • the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the first end of the driving circuit, and the second electrode of the driving transistor is electrically connected to the second end of the driving circuit;
  • the gate of the third transistor is electrically connected to the first reset terminal, the first electrode of the third transistor is electrically connected to the reference voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;
  • a gate of the fourth transistor is electrically connected to the second reset terminal, a first electrode of the fourth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the reset node.
  • the first energy storage circuit includes a first capacitor
  • the second energy storage circuit includes a second capacitor
  • a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node;
  • a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to a third node.
  • the third reset circuit includes a fifth transistor
  • a gate of the fifth transistor is electrically connected to the scan line, a first electrode of the fifth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fifth transistor is electrically connected to the reset node.
  • the first light emitting control circuit includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the light emitting control line, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the drive circuit. The first end is electrically connected.
  • the second light emitting control circuit includes a seventh transistor
  • the gate of the seventh transistor is electrically connected to the light emitting control line, the first electrode of the seventh transistor is electrically connected to the second end of the driving circuit, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.
  • an embodiment of the present disclosure provides a pixel driving method, which is applied to the above-mentioned pixel circuit, wherein a display period includes a compensation phase, a writing phase, and a light emitting phase which are arranged in sequence, and the pixel driving method includes:
  • the compensation control circuit controls the second node to be connected to the compensation node under the control of the first reset signal
  • the drive circuit controls the first end of the drive circuit to be connected with the second end of the drive circuit under the control of the potential of the control end thereof, so as to charge the first energy storage circuit and the second energy storage circuit through the power supply voltage end, until the drive circuit controls the first end of the drive circuit to be disconnected with the second end of the drive circuit under the control of the potential of the control end thereof;
  • the data writing circuit writes the data voltage on the data line into the data writing node under the control of the scanning signal, and the compensation control circuit controls the second node to be disconnected from the compensation node under the control of the first reset signal;
  • the driving circuit drives the light emitting element.
  • the display cycle further includes a reset phase arranged before the compensation phase; and the pixel driving method further includes:
  • the first reset circuit writes the reference voltage into the first node under the control of the first reset signal
  • the second reset circuit writes the first initial voltage into the reset node under the control of the second reset signal.
  • the pixel driving method described in at least one embodiment of the present disclosure further includes:
  • the compensation control circuit controls the connection between the second node and the compensation node under the control of the first reset signal.
  • the pixel driving method includes:
  • the second reset circuit under the control of the second reset signal, changes the first initial voltage Write to the reset node.
  • the pixel circuit further includes a third reset circuit; and the pixel driving method further includes:
  • the third reset circuit writes the second initial voltage into the reset node under the control of the scan signal.
  • the pixel circuit further includes a first light emitting control circuit; and the pixel driving method further includes:
  • the first light-emitting control circuit controls the power supply voltage terminal to be connected to the first terminal of the driving circuit under the control of the light-emitting control signal.
  • the pixel circuit further includes a second light emitting control circuit; and the pixel driving method further includes:
  • the second light-emitting control circuit controls the second end of the driving circuit to be connected to the first electrode of the light-emitting element under the control of the light-emitting control signal.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned pixel circuit.
  • FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG14 is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG13 of the present disclosure.
  • FIG15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG16 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG15 of the present disclosure.
  • FIG17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG18 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG17 of the present disclosure.
  • FIG19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG20 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG19 of the present disclosure.
  • FIG21 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 22 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure.
  • FIG23 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 24 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure.
  • FIG25 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG26 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 27 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 26 of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain, and the second electrode may be a source; or, the first electrode may be a source, and the second electrode may be a drain.
  • the pixel circuit described in the embodiment of the present disclosure includes a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a data writing circuit and a compensation control circuit;
  • the first end of the first energy storage circuit is electrically connected to the first node.
  • the two ends are electrically connected to the second node, and the first energy storage circuit is used to store electrical energy;
  • the first end of the second energy storage circuit is electrically connected to the second node, the second end of the second energy storage circuit is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy;
  • the control end of the driving circuit is electrically connected to the first node, and the driving circuit is used to drive the light emitting element under the control of the potential of the control end;
  • the third node is electrically connected to the first electrode of the light emitting element, and the second electrode of the light emitting element is electrically connected to the first voltage terminal;
  • the data writing circuit is electrically connected to the scan line, the data line and the data writing node respectively, and is used to control the data voltage on the data line to be written into the second node under the control of the scan signal provided by the scan line;
  • the compensation control circuit is electrically connected to the first reset terminal, the second node and the compensation node respectively, and is used to control the connection or disconnection between the second node and the compensation node under the control of the first reset signal;
  • the compensation node is electrically connected to the third node, and/or the compensation node is electrically connected to the second end of the driving circuit; the data writing node is the second node or the third node.
  • threshold voltage compensation and data voltage writing are performed in a time-sharing manner, so as to achieve high-frequency driving under the premise of fully performing threshold voltage compensation.
  • the threshold voltage compensation and data voltage writing are performed in time-sharing, the threshold voltage compensation can be performed for a longer time, so that the threshold voltage of the driving transistor included in the driving circuit can be fully compensated, and the frequency of the scanning signal provided by the scanning line can be increased, thereby enabling high-frequency driving.
  • the first end of the driving circuit may be electrically connected to the power supply voltage end, and the second end of the driving circuit may be electrically connected to the first electrode of the light emitting element; or,
  • the first end of the driving circuit can be electrically connected to the power supply voltage end through the first light emitting control circuit, and the second end of the driving circuit can be electrically connected to the first electrode of the light emitting element; or,
  • the first end of the driving circuit may be electrically connected to the power supply voltage end, and the second end of the driving circuit may be electrically connected to the first electrode of the light emitting element through a second light emitting control circuit; or,
  • the first end of the driving circuit can be electrically connected to the power supply voltage end through the first light emitting control circuit, and the second end of the driving circuit can be electrically connected to the first electrode of the light emitting element through the second light emitting control circuit. catch;
  • the pixel circuit described in at least one embodiment of the present disclosure includes a light emitting element E0, a driving circuit 10, a first energy storage circuit 11, a second energy storage circuit 12, a data writing circuit 13 and a compensation control circuit 14;
  • a first end of the first energy storage circuit 11 is electrically connected to a first node N1, a second end of the first energy storage circuit 11 is electrically connected to a second node N2, and the first energy storage circuit 11 is used to store electrical energy;
  • the first end of the second energy storage circuit 12 is electrically connected to the second node N2, the second end of the second energy storage circuit 12 is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy;
  • the control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the power supply voltage terminal ELVDD, the second terminal of the driving circuit 10 is electrically connected to the first electrode of the light emitting element E0, and the driving circuit 10 is used to drive the light emitting element E0 under the control of the potential of the control terminal;
  • the second electrode of the light emitting element E0 is electrically connected to the first voltage terminal V1, and the third node N3 is electrically connected to the first electrode of the light emitting element E0;
  • the data writing circuit 13 is electrically connected to the scan line G1, the data line Da and the second node N2 respectively, and is used to control the data voltage Vdata on the data line Da to be written into the second node N2 under the control of the scan signal provided by the scan line G1;
  • the compensation control circuit 14 is electrically connected to the first reset terminal R1, the second node N2 and the compensation node N4 respectively, and is used to control the connection or disconnection between the second node N2 and the compensation node N4 under the control of the first reset signal;
  • the compensation node N4 is electrically connected to the third node N3.
  • the data writing node is the second node N2 .
  • the first voltage line may be a low voltage line, but is not limited thereto.
  • a display cycle includes a compensation phase, a writing phase, and a light emitting phase that are arranged in sequence;
  • the compensation control circuit 14 controls the second node N2 to be connected to the compensation node N4 under the control of the first reset signal
  • the driving circuit 10 controls the potential of its control terminal to The first end of the drive circuit 10 is connected to the second end of the drive circuit 10 to charge the first energy storage circuit 11 and the second energy storage circuit 12 through the power supply voltage end, until the drive circuit 10 controls the first end of the drive circuit 10 to be disconnected from the second end of the drive circuit 10 under the control of the potential of the control end thereof;
  • the data writing circuit 13 writes the data voltage Vdata on the data line Da into the second node N2 under the control of the scanning signal, and the compensation control circuit 14 controls the second node N2 to be disconnected from the compensation node N4 under the control of the first reset signal;
  • the driving circuit 10 drives the light emitting element E0.
  • At least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure performs threshold voltage compensation in the compensation phase and data voltage writing in the writing phase during operation.
  • the threshold voltage compensation and data voltage writing are performed in a time-sharing manner so as to achieve high-frequency driving while fully compensating the threshold voltage.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first reset circuit and a second reset circuit;
  • the first reset circuit is electrically connected to the first reset terminal, the reference voltage terminal and the first node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the first reset signal provided by the first reset terminal;
  • the second reset circuit is electrically connected to the second reset terminal, the first initial voltage terminal and the reset node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the reset node under the control of the second reset signal provided by the second reset terminal;
  • the reset node is a second node or a third node, and the third node is electrically connected to the first electrode of the light emitting element.
  • the pixel circuit may further include a first reset circuit and a second reset circuit.
  • the first reset circuit writes a reference voltage to a first node under the control of a first reset signal
  • the second reset circuit writes a first initial voltage to a reset node under the control of a second reset signal.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a first reset circuit 21 and a second reset circuit 22 ;
  • the first reset circuit 21 is electrically connected to the first reset terminal R1, the reference voltage terminal VR and the first node N1 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1 under the control of the first reset signal provided by the first reset terminal R1;
  • the second reset circuit 22 is electrically connected to the second reset terminal R2, the first initial voltage terminal I1 and the third node N3 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the third node N3 under the control of the second reset signal provided by the second reset terminal 42.
  • the reset node is the third node.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a first reset circuit 21 and a second reset circuit 22 ;
  • the first reset circuit 21 is electrically connected to the first reset terminal R1, the reference voltage terminal VR and the first node N1 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal VR into the first node N1 under the control of the first reset signal provided by the first reset terminal R1;
  • the second reset circuit 22 is electrically connected to the second reset terminal R2 , the first initial voltage terminal I1 and the second node N2 , respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the second reset signal provided by the second reset terminal 42 .
  • the reset node is the second node.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a third reset circuit
  • the third reset circuit is electrically connected to the scan line, the second initial voltage terminal and the reset node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the reset node under the control of the scan signal;
  • the data writing node is the second node, and the reset node is the third node; or, the data writing node is the third node, and the reset node is the second node.
  • the pixel circuit may further include a third reset circuit, and the third reset circuit writes the second initial voltage into the reset node under the control of the scan signal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a third reset circuit 41 ;
  • the third reset circuit 41 is electrically connected to the scan line G1, the second initial voltage terminal I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the scan signal.
  • the reset node is the third node N3 .
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a third reset circuit 41 ;
  • the third reset circuit 41 is electrically connected to the scan line G1, the second initial voltage terminal I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the scan signal.
  • the pixel circuit further includes a first light emitting control circuit
  • the first end of the driving circuit is electrically connected to the power supply voltage end through the first light emitting control circuit; the second end of the driving circuit is electrically connected to the first electrode of the light emitting element;
  • the control end of the first light-emitting control circuit is electrically connected to the light-emitting control line, and the first light-emitting control circuit is used to control the connection or disconnection between the power supply voltage end and the first end of the driving circuit under the control of the light-emitting control signal provided by the light-emitting control line.
  • the pixel circuit may further include a first light emitting control circuit, which controls the connection or disconnection between the power supply voltage terminal and the first terminal of the driving circuit under the control of a light emitting control signal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit 61 ;
  • the first end of the driving circuit 10 is electrically connected to the power supply voltage terminal ELVDD through the first light emitting control circuit 61;
  • the control end of the first light emitting control circuit 61 is electrically connected to the light emitting control line EM, and the first light emitting control circuit 61 is used to control the connection or disconnection between the power supply voltage end ELVDD and the first end of the driving circuit 10 under the control of a light emitting control signal provided by the light emitting control line EM.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit 61 ;
  • the first end of the driving circuit 10 is electrically connected to the power supply voltage terminal ELVDD through the first light emitting control circuit 61;
  • the control end of the first light emitting control circuit 61 is electrically connected to the light emitting control line EM, and the first light emitting control circuit 61 is used to control the connection or disconnection between the power supply voltage end ELVDD and the first end of the driving circuit 10 under the control of a light emitting control signal provided by the light emitting control line EM.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second light emitting control circuit
  • the first end of the driving circuit is electrically connected to the power supply voltage end, and the second end of the driving circuit is electrically connected to the first electrode of the light emitting element through the second light emitting control circuit;
  • the control end of the second light-emitting control circuit is electrically connected to the light-emitting control line, and the second light-emitting control circuit is used to control the connection or disconnection between the second end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line.
  • the pixel circuit may further include a second light emitting control circuit, which controls the connection or disconnection between the second end of the driving circuit and the first pole of the light emitting element under the control of the light emitting control circuit.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second light emitting control circuit 62 ;
  • the second end of the driving circuit 10 is electrically connected to the first electrode of the light emitting element E0 through the second light emitting control circuit 62;
  • the control end of the second light emitting control circuit 62 is electrically connected to the light emitting control line EM, and the second light emitting control circuit 62 is used to control the connection or disconnection between the second end of the driving circuit 10 and the first electrode of the light emitting element E0 under the control of the light emitting control signal provided by the light emitting control line EM;
  • the second reset circuit 22 is electrically connected to the third node N3 , and the compensation node N4 is electrically connected to the third node N3 .
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second light emitting control circuit 62 ;
  • the second end of the driving circuit 10 is electrically connected to the first electrode of the light emitting element E0 through the second light emitting control circuit 62;
  • the control end of the second light emitting control circuit 62 is electrically connected to the light emitting control line EM, and the second light emitting control circuit 62 is used to control the connection or disconnection between the second end of the driving circuit 10 and the first electrode of the light emitting element E0 under the control of the light emitting control signal provided by the light emitting control line EM;
  • the compensation node N4 is electrically connected to the third node N3.
  • the compensation node N4 is electrically connected to the second end of the driving circuit 10 .
  • the compensation node N4 is electrically connected to the second end of the driving circuit 10 .
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 6 of the present disclosure is that the data writing node is the third node N3 and the reset node is the second node N2.
  • the data writing circuit 13 is electrically connected to the scan line G1, the data line Da and the third node N3 respectively, and is used to control the data voltage Vdata on the data line Da to be written into the third node N3 under the control of the scan signal provided by the scan line G1;
  • the third reset circuit 41 is electrically connected to the scan line G1, the second initial voltage terminal I2 and the second node N2 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the second node N2 under the control of the scan signal.
  • the data writing circuit includes a first transistor, and the compensation control circuit includes a second transistor;
  • the gate of the first transistor is electrically connected to the scan line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the data writing node;
  • a gate of the second transistor is electrically connected to the first reset terminal, a first electrode of the second transistor is electrically connected to the second node, and a second electrode of the second transistor is electrically connected to the compensation node.
  • the driving circuit includes a driving transistor, the first reset circuit includes a third transistor, and the second reset circuit includes a fourth transistor;
  • the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the first end of the driving circuit, and the second electrode of the driving transistor is electrically connected to the second end of the driving circuit;
  • the gate of the third transistor is electrically connected to the first reset terminal, the first electrode of the third transistor is electrically connected to the reference voltage terminal, and the second electrode of the third transistor is electrically connected to the first node;
  • a gate of the fourth transistor is electrically connected to the second reset terminal, a first electrode of the fourth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the fourth transistor is electrically connected to the reset node.
  • the first energy storage circuit includes a first capacitor
  • the second energy storage circuit includes a second capacitance
  • a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node;
  • a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to a third node.
  • the third reset circuit includes a fifth transistor
  • a gate of the fifth transistor is electrically connected to the scan line, a first electrode of the fifth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the fifth transistor is electrically connected to the reset node.
  • the first light emitting control circuit includes a sixth transistor
  • the gate of the sixth transistor is electrically connected to the light emitting control line, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first terminal of the driving circuit.
  • the second light emitting control circuit includes a seventh transistor
  • the gate of the seventh transistor is electrically connected to the light emitting control line, the first electrode of the seventh transistor is electrically connected to the second end of the driving circuit, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.
  • the light emitting element is an organic light emitting diode O1 ;
  • the data writing circuit includes a first transistor T1 , and the compensation control circuit includes a second transistor T2 ;
  • the gate of the first transistor T1 is electrically connected to the scan line G1, the drain of the first transistor T1 is electrically connected to the data line Da, and the source of the first transistor T1 is electrically connected to the second node N2;
  • the gate of the second transistor T2 is electrically connected to the first reset terminal R1, the drain of the second transistor T2 is electrically connected to the second node N2, and the source of the second transistor T2 is electrically connected to the compensation node N4; the compensation node N4 is electrically connected to the third node N3, and the third node N3 is electrically connected to the anode of the organic light emitting diode O1;
  • the driving circuit includes a driving transistor T0, the first reset circuit includes a third transistor T3, and the second reset circuit includes a fourth transistor T4;
  • the gate of the driving transistor T0 is electrically connected to the first node N1;
  • the gate of the third transistor T3 is electrically connected to the first reset terminal R1, the drain of the third transistor T3 is electrically connected to the reference voltage terminal VR, and the source of the third transistor T3 is electrically connected to the first node N1;
  • the gate of the fourth transistor T4 is electrically connected to the second reset terminal R2, the drain of the fourth transistor T4 is electrically connected to the first initial voltage terminal I1, and the source of the fourth transistor T4 is electrically connected to the third node N3;
  • the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;
  • a first end of the first capacitor C1 is electrically connected to a first node N1, and a second end of the first capacitor C1 is electrically connected to a second node N2;
  • a first end of the second capacitor C2 is electrically connected to the second node N2, and a second end of the second capacitor C2 is electrically connected to a third node N3;
  • the third reset circuit includes a fifth transistor T5;
  • the gate of the fifth transistor T5 is electrically connected to the scan line G1, the drain of the fifth transistor T5 is electrically connected to the second initial voltage terminal I2, and the source of the fifth transistor T5 is electrically connected to the third node N3;
  • the first light emitting control circuit comprises a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the light emitting control line EM, the drain of the sixth transistor T6 is electrically connected to the power supply voltage terminal ELVDD, and the source of the sixth transistor T6 is electrically connected to the source of the driving transistor T0;
  • the drain of the driving transistor T0 is electrically connected to the anode of the organic light emitting diode O1;
  • the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal ELVSS.
  • all transistors are n-type transistors, but the present invention is not limited thereto.
  • the gate of T2 and the gate of T3 may also be electrically connected to different control terminals, and the gate of T1 and the gate of T5 may also be electrically connected to different control terminals.
  • the voltage value of Vinit1 may be the same as the voltage value of Vinit2, and both may be equal to VSS, and Vref may also be equal to VDD, but the present invention is not limited thereto.
  • VDD is a voltage value of a power supply voltage provided by ELVDD
  • VSS is a voltage value of a low voltage signal provided by ELVSS.
  • a display cycle may include a reset phase S1 , a compensation phase S2 , a writing phase S3 , and a light emitting phase S4 that are successively arranged;
  • EM provides a low voltage signal
  • R1 provides a high voltage signal
  • R2 provides a high voltage signal
  • G1 provides a low voltage signal
  • T2 and T3 are turned on to transfer the reference voltage Vref provided by the reference voltage terminal VR to the first node N1, so that at the beginning of the compensation phase S2, the driving transistor T0 can be turned on, T4 is turned on, and the first initial voltage Vinit1 provided by I1 is written into N2 and N4 to complete the reset of the potential of N2 and the potential of N4. Since there is no transistor between N3 and N4, the anode voltage of O1 and the potential of N3 can be reset at the same time;
  • EM provides a high voltage signal
  • R1 provides a high voltage signal
  • R2 provides a low voltage signal
  • G1 provides a low voltage signal
  • T2, T3, and T6 are turned on;
  • T0 is turned on, and the power supply voltage provided by ELVDD charges the capacitor through T6, T0, and T2 to change the potential of N4 until the potential of N4 becomes Vref-Vth, and then T0 is turned off to complete the threshold voltage compensation of T0;
  • Vref-VDD needs to be less than the threshold voltage Vth of T0 so that T0 can be turned off;
  • EM provides a low voltage signal
  • R1 and R2 provide a low voltage signal
  • G1 provides a high voltage signal
  • Da provides a data voltage Vdata
  • T5 and T1 are turned on
  • the data line Da writes the data voltage Vdata into the second node N2
  • I2 writes the second initial voltage Vinit2 into the third node N3
  • the first node N1 is in a floating state
  • the potential of N1 changes with the change of the potential of N2
  • the change amount is equal
  • Vdata is written into N2 through T1
  • the potential of N2 changes from Vref-Vth to Vdata
  • the change amount of the potential of N2 is Vdata-(Vref-Vth)
  • the potential of N1 becomes Vref+Vdata-(Vref-Vth)
  • T5 is turned on
  • the potential of N3 becomes Vinit2, and the difference between the potential of N1 and the potential of N3 is Vdata+Vth-Vinit2;
  • EM provides a high voltage signal
  • R1 and R2 provide a low voltage signal
  • G1 provides a low voltage signal
  • T0 and T6 are turned on
  • N1 and N2 are in a floating state
  • the potential of N1 and the potential of N2 change with the potential of N3, and the change amount is equal.
  • T0 drives O1 to charge until O1 emits light stably.
  • the potential of N3 is VSS+Voled
  • Voled is the start-up voltage of O1
  • the potential of N3 is VSS+Voled.
  • the bit change is VSS+Voled-Vinit2, the potential of N1 is VSS+Voled-Vinit2+Vdata+Vth; the gate-source voltage of T0 is Vdata+Vth-Vinit2, and T0 works in the saturation working range;
  • the driving current I driven by T0 to drive O1 to emit light is equal to K(Vdata-Vinit2) 2 ;
  • K is the current coefficient of T0. It can be seen that the driving current I is not related to the threshold voltage, VSS and Voled of the driving transistor T0. That is, at least one embodiment of the pixel circuit shown in Figure 13 of the present disclosure can compensate for the uneven threshold voltage of the driving transistor T0, the voltage drop of the low voltage terminal ELVSS, and the uneven display caused by the aging of the organic light emitting diode, thereby improving the display effect.
  • the threshold voltage compensation process and the data voltage writing process are separated, the threshold voltage compensation can be performed for a longer time, thereby ensuring better threshold voltage compensation and improving the driving rate.
  • the driving frequency can be 120Hz, 180Hz or 240Hz, which is beneficial to improving the effects of scenes in fields such as games, and can improve the accuracy of the light-emitting current and the display quality.
  • At least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure only needs to use four groups of GOAs (Gate On Array, a gate driving circuit arranged on an array substrate) to respectively provide a light emitting control signal, a first reset signal, a second reset signal and a scanning signal, thereby reducing the number of GOAs used and facilitating the realization of a narrow frame.
  • GOAs Gate On Array, a gate driving circuit arranged on an array substrate
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure is that the sixth transistor T6 for light emission control is not provided.
  • At least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure may use only three groups of GOAs to further achieve a narrow frame.
  • FIG. 16 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure is that the source of T4 is electrically connected to the second node N2.
  • a display cycle may include a reset phase S1 , a compensation phase S2 , a data writing phase S3 , and a light emitting phase S4 , which are arranged successively;
  • R1 and R2 both provide high voltage signals
  • G1 provides a low voltage signal
  • T2, T3 and T4 are all turned on
  • I1 writes the first initial voltage Vinit1 into N2, N3 and N4, and
  • VR provides a reference voltage Vref into N1;
  • R1 provides a high voltage signal
  • R2 provides a low voltage signal
  • G1 provides a low voltage signal
  • T2 and T3 are turned on;
  • T0 is turned on, and the power supply voltage provided by ELVDD charges the capacitor through T0 and T2 to change the potential of N4 until the potential of N4 becomes Vref-Vth, then T0 is turned off to complete the threshold voltage compensation of T0; Vref-VDD needs to be less than the threshold voltage Vth of T0;
  • R1 and R2 provide low voltage signals
  • G1 provides high voltage signals
  • Da provides data voltage Vdata
  • T5 and T1 are turned on
  • data line Da writes data voltage Vdata into second node N2
  • I2 writes second initial voltage Vinit2 into third node N3
  • potential of N1 changes with potential of N2
  • the change amount is equal
  • Vdata is written into N2 through T1
  • potential of N2 changes from Vref-Vth to Vdata
  • potential of N2 changes by Vdata-(Vref-Vth)
  • potential of N1 changes to Vref+Vdata-(Vref-Vth)
  • T5 is turned on
  • potential of N3 changes to Vinit2
  • the difference between potential of N1 and potential of N3 is Vdata+Vth-Vinit2;
  • R1 and R2 provide low voltage signals
  • G1 provides low voltage signals
  • T0, N1 and N2 are in floating state
  • the potential of N1 and the potential of N2 change with the potential of N3, and the change amount is equal.
  • T0 drives O1 to charge until O1 emits light stably.
  • the potential of N3 is VSS+Voled
  • Voled is the start-up voltage of O1
  • the potential change amount of N3 is VSS+Voled-Vinit2
  • the potential of N1 is VSS+Voled-Vinit2+Vdata+Vth
  • the gate-source voltage of T0 is Vdata+Vth-Vinit2, and T0 works in the saturation working range;
  • the driving current I driven by T0 to drive O1 to emit light is equal to K(Vdata-Vinit2) 2 ;
  • K is the current coefficient of T0. It can be seen that the driving current I is not related to the threshold voltage, VSS and Voled of the driving transistor T0. That is, at least one embodiment of the pixel circuit shown in Figure 17 of the present disclosure can compensate for the uneven threshold voltage of the driving transistor T0, the voltage drop of the low voltage terminal ELVSS, and the uneven display caused by the aging of the organic light emitting diode, thereby improving the display effect.
  • At least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure may use only three groups of GOAs to further achieve a narrow frame.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure is that T5 is not provided.
  • the display cycle includes a reset phase S1, a compensation phase S2, a data writing phase S3 and a light emitting phase S4 which are arranged successively;
  • R1 and R2 both provide high voltage signals
  • G1 provides a low voltage signal
  • T2, T3 and T4 are all turned on
  • I1 writes the first initial voltage Vinit1 into N2, N3 and N4, and
  • VR provides a reference voltage Vref into N1;
  • R1 provides a high voltage signal
  • R2 provides a low voltage signal
  • G1 provides a low voltage signal
  • T2 and T3 are turned on;
  • T0 is turned on, and the power supply voltage provided by ELVDD charges the capacitor through T0 and T2 to change the potential of N4 until the potential of N4 becomes Vref-Vth, then T0 is turned off to complete the threshold voltage compensation of T0; Vref-VDD needs to be less than the threshold voltage Vth of T0;
  • R1 provides a low voltage signal
  • R2 provides a high voltage signal
  • G1 provides a high voltage signal
  • T4 is turned on
  • I1 provides a first initial voltage Vinit1 to N3
  • Da provides a data voltage Vdata
  • T2 is turned on
  • the data line Da writes the data voltage Vdata into the second node N2
  • the first node N1 is in a floating state
  • the potential of N1 changes with the change of the potential of N2
  • the change amount is equal
  • Vdata is written into N2 through T1
  • the potential of N2 changes from Vref-Vth to Vdata
  • the change amount of the potential of N2 is Vdata-(Vref-Vth).
  • the potential of N1 becomes Vref+Vdata-(Vref-Vth), that is, the potential of N1 becomes Vdata+Vth; T4 is turned on, the potential of N3 becomes Vinit1, and the difference between the potential of N1 and the potential of N3 is Vdata+Vth-Vinit1;
  • R1 and R2 provide low voltage signals
  • G1 provides low voltage signals
  • T0, N1 and N2 are in floating state
  • the potential of N1 and the potential of N2 change with the potential of N3, and the change amount is equal.
  • T0 drives O1 to charge until O1 emits light stably.
  • the potential of N3 is VSS+Voled
  • Voled is the start-up voltage of O1
  • the potential change amount of N3 is VSS+Voled-Vinit2
  • the potential of N1 is VSS+Voled-Vinit1+Vdata+Vth
  • the gate-source voltage of T0 is Vdata+Vth-Vinit1, and T0 works in the saturation working range;
  • the driving current I driven by T0 to drive O1 to emit light is equal to K(Vdata-Vinit1) 2 ;
  • K is the current coefficient of T0. It can be seen that the driving current I is not related to the threshold voltage, VSS and Voled of the driving transistor T0. That is, at least one embodiment of the pixel circuit shown in Figure 19 of the present disclosure can compensate for the uneven threshold voltage of the driving transistor T0, the voltage drop of the low voltage terminal ELVSS, and the uneven display caused by the aging of the organic light emitting diode, thereby improving the display effect.
  • At least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure may use only three groups of GOAs to further achieve a narrow frame.
  • the source of T4 may be replaced to be electrically connected to the second node N2.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure is that a sixth transistor T6 is added;
  • a gate of the sixth transistor T6 is electrically connected to the light emitting control line EM, a drain of the sixth transistor T6 is electrically connected to the power supply voltage terminal ELVDD, and a source of the sixth transistor T6 is electrically connected to the source of the driving transistor T0.
  • the display cycle when at least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure is in operation, the display cycle includes a reset phase S1 , a compensation phase S2 , a data writing phase S3 , and a light emitting phase S4 which are successively arranged;
  • EM provides a low voltage signal
  • R1 and R2 both provide high voltage signals
  • G1 provides a low voltage signal
  • T2, T3 and T4 are all turned on
  • I1 writes the first initial voltage Vinit1 into N2, N3 and N4, and VR provides a reference voltage Vref into N1;
  • R1 provides a high voltage signal
  • R2 provides a low voltage signal
  • G1 provides a low voltage signal
  • T2 and T3 are turned on
  • EM provides a high voltage signal
  • T6 is turned on
  • T0 is turned on, and the power supply voltage provided by ELVDD charges the capacitor through T6, T0 and T2 to change the potential of N4 until the potential of N4 becomes Vref-Vth, then T0 is turned off to complete the threshold voltage compensation of T0; Vref-VDD needs to be less than the threshold voltage Vth of T0;
  • EM provides a low voltage signal
  • R1 provides a low voltage signal
  • R2 provides a high voltage signal
  • G1 provides a high voltage signal
  • T4 is turned on
  • I1 provides the first initial voltage Vinit1 to N3
  • Da provides the data voltage Vdata
  • T2 is turned on
  • the data line Da writes the data voltage Vdata into the second node N2
  • the first node N1 is in a floating state
  • the potential of N1 changes with the change of the potential of N2
  • the change amount is equal
  • Vdata is written into N2 through T1
  • the potential of N2 changes from Vref-Vth to Vdata
  • the change amount of the potential of N2 is Vdata-(Vref-Vth).
  • the potential of N1 becomes Vref+Vdata-(Vref-Vth), that is, the potential of N1 becomes Vdata+Vth; T4 is turned on, the potential of N3 becomes Vinit1, and the difference between the potential of N1 and the potential of N3 is Vdata+Vth-Vinit1;
  • EM provides a high voltage signal
  • T6 is turned on
  • R1 and R2 provide a low voltage signal.
  • G1 provides a low voltage signal
  • T0, N1 and N2 are in a floating state
  • the potential of N1 and the potential of N2 change with the potential of N3, and the change amount is equal.
  • T0 drives O1 to charge until O1 emits light stably.
  • the potential of N3 is VSS+Voled
  • Voled is the start-up voltage of O1
  • the potential change of N3 is VSS+Voled-Vinit2
  • the potential of N1 is VSS+Voled-Vinit1+Vdata+Vth
  • the gate-source voltage of T0 is Vdata+Vth-Vinit1
  • T0 works in the saturation working range
  • the driving current I driven by T0 to drive O1 to emit light is equal to K(Vdata-Vinit1) 2 ;
  • K is the current coefficient of T0. It can be seen that the driving current I is not related to the threshold voltage, VSS and Voled of the driving transistor T0. That is, at least one embodiment of the pixel circuit shown in Figure 21 of the present disclosure can compensate for the uneven threshold voltage of the driving transistor T0, the voltage drop of the low voltage terminal ELVSS, and the uneven display caused by the aging of the organic light emitting diode, thereby improving the display effect.
  • At least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure may use only four groups of GOAs to further achieve a narrow frame.
  • At least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure adds a sixth transistor T6 for light emission control.
  • T6 is in a closed state during the reset stage and the data writing stage to avoid generating current between ELVDD and I1 and increasing power consumption during the reset stage and the data writing stage.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure is that: the sixth transistor T6 is not provided; and a seventh transistor T7 is also included;
  • the seventh transistor T7 is disposed between the drain of the driving transistor T0 and the anode of the organic light emitting diode O1;
  • the compensation node N4 is electrically connected to the third node N3; the third node N3 is electrically connected to the anode of O1;
  • the gate of T7 is electrically connected to the light emitting control line EM;
  • the source of T7 is electrically connected to the drain of the driving transistor T0 , and the drain of T7 is electrically connected to the anode of O1 .
  • FIG. 24 At least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure is in operation.
  • the display cycle may include a reset phase S1, a compensation phase S2, a writing phase S3 and a light emitting phase S4 which are arranged successively;
  • EM provides a low voltage signal
  • R1 provides a high voltage signal
  • R2 provides a high voltage signal
  • G1 provides a low voltage signal
  • T2 and T3 are turned on to convert the reference voltage terminal VR to
  • the reference voltage Vref is supplied to the first node N1, so that at the beginning of the compensation phase S2, the driving transistor T0 can be turned on, T4 is turned on, and the first initial voltage Vinit1 provided by I1 is written into N2 and N4, completing the reset of the potential of N2 and the potential of N4. Since there is no transistor between N3 and N4, the anode voltage of O1 and the potential of N3 can be reset at the same time;
  • EM provides a high voltage signal
  • R1 provides a high voltage signal
  • R2 provides a low voltage signal
  • G1 provides a low voltage signal
  • T2, T3, and T7 are turned on;
  • T0 is turned on, and the power supply voltage provided by ELVDD charges the capacitor through T7, T0, and T2 to change the potential of N4 until the potential of N4 becomes Vref-Vth, then T0 is turned off to complete the threshold voltage compensation of T0; Vref-VDD needs to be less than the threshold voltage Vth of T0;
  • EM provides a low voltage signal
  • R1 and R2 provide a low voltage signal
  • G1 provides a high voltage signal
  • Da provides a data voltage Vdata
  • T5 and T1 start
  • the data line Da writes the data voltage Vdata into the second node N2
  • I2 writes the second initial voltage Vinit2 into the third node N3
  • the first node N1 is in a floating state
  • the potential of N1 changes with the change of the potential of N2
  • the change amount is equal
  • Vdata is written into N2 through T1
  • the potential of N2 changes from Vref-Vth to Vdata
  • the change amount of the potential of N2 is Vdata-(Vref-Vth)
  • the potential of N1 becomes Vref+Vdata-(Vref-Vth)
  • T5 is turned on
  • the potential of N3 becomes Vinit2, and the difference between the potential of N1 and the potential of N3 is Vdata+Vth-Vinit2;
  • EM provides a high voltage signal
  • R1 and R2 provide a low voltage signal
  • G1 provides a low voltage signal
  • T0 and T7 are turned on
  • N1 and N2 are in a floating state
  • the potential of N1 and the potential of N2 change with the potential of N3, and the change amount is equal.
  • T0 drives O1 to charge until O1 emits light stably.
  • the potential of N3 is VSS+Voled
  • Voled is the start-up voltage of O1
  • the potential change of N3 is VSS+Voled-Vinit2
  • the potential of N1 is VSS+Voled-Vinit2+Vdata+Vth
  • the gate-source voltage of T0 is Vdata+Vth-Vinit2, and T0 works in the saturation working range
  • the driving current I driven by T0 to drive O1 to emit light is equal to K(Vdata-Vinit2) 2 ;
  • K is the current coefficient of T0. It can be seen that the driving current I is not related to the threshold voltage, VSS and Voled of the driving transistor T0. That is, at least one embodiment of the pixel circuit shown in Figure 23 of the present disclosure can compensate for the uneven threshold voltage of the driving transistor T0, the voltage drop of the low voltage terminal ELVSS, and the uneven display caused by the aging of the organic light emitting diode, thereby improving the display effect.
  • VDD is the voltage value of the power supply voltage provided by ELVDD.
  • VSS is the voltage value of the low voltage signal provided by ELVSS.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 25 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure is that the compensation node N4 is electrically connected to the drain of T0.
  • the difference between at least one embodiment of the pixel circuit shown in FIG. 26 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure is that the data writing node is the third node N3, and the reset node is the second node N2.
  • the gate of the first transistor T1 is electrically connected to the scan line G1, the drain of the first transistor T1 is electrically connected to the data line Da, and the source of the first transistor T1 is electrically connected to the third node N3;
  • a gate of the fifth transistor T5 is electrically connected to the scan line G1 , a drain of the fifth transistor T5 is electrically connected to the second initial voltage terminal I2 , and a source of the fifth transistor T5 is electrically connected to the second node N2 .
  • a display cycle may include a reset phase S1 , a compensation phase S2 , a writing phase S3 , and a light emitting phase S4 that are successively arranged;
  • EM provides a low voltage signal
  • R1 provides a high voltage signal
  • R2 provides a high voltage signal
  • G1 provides a low voltage signal
  • T2 and T3 are turned on to transfer the reference voltage Vref provided by the reference voltage terminal VR to the first node N1, so that at the beginning of the compensation phase S2, the driving transistor T0 can be turned on, T4 is turned on, and the first initial voltage Vinit1 provided by I1 is written into N2 and N4 to complete the reset of the potential of N2 and the potential of N4. Since there is no transistor between N3 and N4, the anode voltage of O1 and the potential of N3 can be reset at the same time;
  • EM provides a high voltage signal
  • R1 provides a high voltage signal
  • R2 provides a low voltage signal
  • G1 provides a low voltage signal
  • T2, T3, and T6 are turned on;
  • T0 is turned on, and the power supply voltage provided by ELVDD charges the capacitor through T6, T0, and T2 to change the potential of N4 until the potential of N4 becomes Vref-Vth, and then T0 is turned off to complete the threshold voltage compensation of T0;
  • Vref-VDD needs to be less than the threshold voltage Vth of T0 so that T0 can be turned off;
  • EM provides a high voltage signal
  • R1 and R2 provide a low voltage signal
  • G1 provides a low voltage signal
  • T0 and T6 are turned on
  • N1 and N2 are in a floating state
  • the potential of N1 and the potential of N2 change with the potential of N3, and the change amount is equal.
  • T0 drives O1 to charge until O1 emits light stably.
  • the potential of N3 is VSS+Voled
  • Voled is the start-up voltage of O1
  • the potential change amount of N3 is VSS+Voled-Vdata;
  • N1 VSS+Voled-Vdata+Vinit2+Vth
  • the gate-source voltage of T0 Vinit2+Vth-Vdata, and T0 works in the saturation working range
  • the driving current I driven by T0 to drive O1 to emit light is equal to K(Vinit2-Vdata) 2 ;
  • K is the current coefficient of T0. It can be seen that the driving current I is not related to the threshold voltage, VSS and Voled of the driving transistor T0. That is, at least one embodiment of the pixel circuit shown in Figure 26 of the present disclosure can compensate for the uneven threshold voltage of the driving transistor T0, the voltage drop of the low voltage terminal ELVSS, and the uneven display caused by the aging of the organic light emitting diode, thereby improving the display effect.
  • the sixth transistor T6 may not be provided.
  • the sixth transistor T6 may not be provided, and a seventh transistor T7 may be provided between the drain of T0 and the anode of O1 , and the compensation node N4 may be electrically connected to the anode of O1 or the drain of T0 .
  • the pixel driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display cycle includes a compensation phase, a writing phase and a light-emitting phase which are arranged in sequence.
  • the pixel driving method includes:
  • the compensation control circuit controls the second node to be connected to the compensation node under the control of the first reset signal
  • the drive circuit controls the connection between the first terminal of the drive circuit and the second terminal of the drive circuit under the control of the potential of the control terminal, so as to charging the first energy storage circuit and the second energy storage circuit until the drive circuit, under the control of the potential of the control terminal, controls the first terminal of the drive circuit to be disconnected from the second terminal of the drive circuit;
  • the data writing circuit writes the data voltage on the data line into the data writing node under the control of the scanning signal, and the compensation control circuit controls the second node to be disconnected from the compensation node under the control of the first reset signal;
  • the driving circuit drives the light emitting element.
  • threshold voltage compensation is performed in the compensation stage, and data voltage writing is performed in the writing stage.
  • Threshold voltage compensation and data voltage writing are performed in a time-sharing manner so as to achieve high-frequency driving while fully compensating the threshold voltage.
  • the display period further includes a reset phase arranged before the compensation phase; and the pixel driving method further includes:
  • the first reset circuit writes the reference voltage into the first node under the control of the first reset signal
  • the second reset circuit writes the first initial voltage into the reset node under the control of the second reset signal.
  • the compensation control circuit controls the connection between the second node and the compensation node under the control of the first reset signal.
  • the pixel driving method described in at least one embodiment of the present disclosure may further include:
  • the second reset circuit writes the first initial voltage into the reset node under the control of the second reset signal.
  • the pixel circuit further includes a third reset circuit; and the pixel driving method further includes:
  • the third reset circuit writes the second initial voltage into the reset node under the control of the scan signal.
  • the pixel circuit further includes a first light emitting control circuit; and the pixel driving method further includes:
  • the first light-emitting control circuit controls the power supply voltage terminal to be connected to the first terminal of the driving circuit under the control of the light-emitting control signal.
  • the pixel circuit further includes a second light emitting control circuit; and the pixel driving method described in at least one embodiment of the present disclosure further includes:
  • the second light-emitting control circuit controls the second end of the driving circuit to be connected to the first electrode of the light-emitting element under the control of the light-emitting control signal.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

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Abstract

本公开提供一种像素电路、像素驱动方法和显示装置。像素电路包括发光元件、驱动电路、第一储能电路、第二储能电路、数据写入电路和补偿控制电路；数据写入电路在扫描信号的控制下，控制将数据线上的数据电压写入数据写入节点；补偿控制电路在第一复位信号的控制下，控制第二节点与补偿节点之间连通或断开；补偿节点与第三节点电连接，和/或，补偿节点与驱动电路的第二端电连接。本公开能在对驱动电路包括的驱动晶体管的阈值电压充分进行补偿的前提下，实现高频驱动。

Description

像素电路、像素驱动方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、像素驱动方法和显示装置。
背景技术
在相关技术中，像素电路不能在对驱动电路包括的驱动晶体管的阈值电压充分进行补偿的前提下，实现高频驱动。
发明内容
在一个方面中，本公开实施例提供一种像素电路，包括发光元件、驱动电路、第一储能电路、第二储能电路、数据写入电路和补偿控制电路；
所述第一储能电路的第一端与第一节点电连接，所述第一储能电路的第二端与第二节点电连接，所述第一储能电路用于储存电能；
所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与第三节点电连接，所述第二储能电路用于储存电能；
所述驱动电路的控制端与所述第一节点电连接，所述驱动电路用于在其控制端的电位的控制下，驱动所述发光元件；
所述第三节点与所述发光元件的第一极电连接，所述发光元件的第二极与第一电压端电连接；
所述数据写入电路分别与扫描线、数据线和数据写入节点电连接，用于在所述扫描线提供的扫描信号的控制下，控制将所述数据线上的数据电压写入所述数据写入节点；
所述补偿控制电路分别与第一复位端、第二节点和补偿节点电连接，用于在所述第一复位信号的控制下，控制所述第二节点与所述补偿节点之间连通或断开；
所述补偿节点与所述第三节点电连接，和/或，所述补偿节点与所述驱动电路的第二端电连接；所述数据写入节点为所述第二节点或所述第三节点。
可选的，本公开至少一实施例所述的像素电路还包括第一复位电路和第二复位电路；
所述第一复位电路分别与第一复位端、参考电压端和所述第一节点电连接，用于在所述第一复位端提供的第一复位信号的控制下，将所述参考电压端提供的参考电压写入所述第一节点；
所述第二复位电路分别与第二复位端、第一初始电压端和复位节点电连接，用于在所述第二复位端提供的第二复位信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述复位节点；
所述复位节点为第二节点或第三节点。
可选的，本公开至少一实施例所述的像素电路还包括第三复位电路；
所述第三复位电路分别与所述扫描线、第二初始电压端和复位节点电连接，用于在所述扫描信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述复位节点；
所述数据写入节点为所述第二节点，所述复位节点为所述第三节点；或者，所述数据写入节点为所述第三节点，所述复位节点为所述第二节点。
可选的，本公开至少一实施例所述的像素电路还包括第一发光控制电路；
所述驱动电路的第一端通过所述第一发光控制电路与电源电压端电连接；所述驱动电路的第二端与所述发光元件的第一极电连接；
所述第一发光控制电路的控制端与发光控制线电连接，所述第一发光控制电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通或断开。
可选的，本公开至少一实施例所述的像素电路还包括第二发光控制电路；
所述驱动电路的第一端与电源电压端电连接，所述驱动电路的第二端通过所述第二发光控制电路与所述发光元件的第一极电连接；
所述第二发光控制电路的控制端与发光控制线电连接，所述第二发光控制电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通或断开。
可选的，所述数据写入电路包括第一晶体管，所述补偿控制电路包括第二晶体管；
所述第一晶体管的栅极与所述扫描线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述数据写入节点电连接；
所述第二晶体管的栅极与所述第一复位端电连接，所述第二晶体管的第一极与所述第二节点电连接，所述第二晶体管的第二极与所述补偿节点电连接。
可选的，所述驱动电路包括驱动晶体管，所述第一复位电路包括第三晶体管，所述第二复位电路包括第四晶体管；
所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；
所述第三晶体管的栅极与所述第一复位端电连接，所述第三晶体管的第一极与所述参考电压端电连接，所述第三晶体管的第二极与所述第一节点电连接；
所述第四晶体管的栅极与所述第二复位端电连接，所述第四晶体管的第一极与所述第一初始电压端电连接，所述第四晶体管的第二极与所述复位节点电连接。
可选的，所述第一储能电路包括第一电容，所述第二储能电路包括第二电容；
所述第一电容的第一端与第一节点电连接，所述第一电容的第二端与第二节点电连接；
所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与第三节点电连接。
可选的，所述第三复位电路包括第五晶体管；
所述第五晶体管的栅极与所述扫描线电连接，所述第五晶体管的第一极与所述第二初始电压端电连接，所述第五晶体管的第二极与所述复位节点电连接。
可选的，所述第一发光控制电路包括第六晶体管；
所述第六晶体管的栅极与所述发光控制线电连接，所述第六晶体管的第一极与所述电源电压端电连接，所述第六晶体管的第二极与所述驱动电路的 第一端电连接。
可选的，所述第二发光控制电路包括第七晶体管；
所述第七晶体管的栅极与所述发光控制线电连接，所述第七晶体管的第一极与所述驱动电路的第二端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
在第二个方面中，本公开实施例提供一种像素驱动方法，应用于上述的像素电路，显示周期包括先后设置的补偿阶段、写入阶段和发光阶段，所述像素驱动方法包括：
在补偿阶段，所述补偿控制电路在第一复位信号的控制下，控制第二节点与补偿节点之间连通；
在所述补偿阶段开始时，驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以通过电源电压端为第一储能电路和第二储能电路充电，直至所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间断开；
在写入阶段，所述数据写入电路在扫描信号的控制下，将数据线上的的数据电压写入数据写入节点，补偿控制电路在第一复位信号的控制下，控制第二节点与补偿节点之间断开；
在发光阶段，驱动电路驱动发光元件。
可选的，所述显示周期还包设置于所述补偿阶段之前的重置阶段；所述像素驱动方法还包括：
在重置阶段和补偿阶段，第一复位电路在第一复位信号的控制下，将参考电压写入第一节点；
在重置阶段，第二复位电路在第二复位信号的控制下，将第一初始电压写入复位节点。
可选的，本公开至少一实施例所述的像素驱动方法还包括：
在所述重置阶段，所述补偿控制电路在所述第一复位信号的控制下，控制控制第二节点与补偿节点之间连通。
可选的，所述像素驱动方法包括：
在写入阶段，第二复位电路在第二复位信号的控制下，将第一初始电压 写入复位节点。
可选的，所述像素电路还包括第三复位电路；所述像素驱动方法还包括：
在所述写入阶段，所述第三复位电路在扫描信号的控制下，将第二初始电压写入复位节点。
可选的，所述像素电路还包括第一发光控制电路；所述像素驱动方法还包括：
在补偿阶段和发光阶段，第一发光控制控制电路在发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通。
可选的，所述像素电路还包括第二发光控制电路；所述像素驱动方法还包括：
在补偿阶段和发光阶段，第二发光控制控制电路在发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间连通。
在第三个方面中，本公开实施例提供一种显示装置，包括上述的像素电路。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的结构图；
图6是本公开至少一实施例所述的像素电路的结构图；
图7是本公开至少一实施例所述的像素电路的结构图；
图8是本公开至少一实施例所述的像素电路的结构图；
图9是本公开至少一实施例所述的像素电路的结构图；
图10是本公开至少一实施例所述的像素电路的结构图；
图11是本公开至少一实施例所述的像素电路的结构图；
图12是本公开至少一实施例所述的像素电路的结构图；
图13是本公开至少一实施例所述的像素电路的电路图；
图14是本公开图13所示的像素电路的至少一实施例的工作时序图；
图15是本公开至少一实施例所述的像素电路的电路图；
图16是本公开图15所示的像素电路的至少一实施例的工作时序图；
图17是本公开至少一实施例所述的像素电路的电路图；
图18是本公开图17所示的像素电路的至少一实施例的工作时序图；
图19是本公开至少一实施例所述的像素电路的电路图；
图20是本公开图19所示的像素电路的至少一实施例的工作时序图；
图21是本公开至少一实施例所述的像素电路的电路图；
图22是本公开图21所示的像素电路的至少一实施例的工作时序图；
图23是本公开至少一实施例所述的像素电路的电路图；
图24是本公开图23所示的像素电路的至少一实施例的工作时序图；
图25是本公开至少一实施例所述的像素电路的电路图；
图26是本公开至少一实施例所述的像素电路的电路图；
图27是本公开图26所示的像素电路的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一电极，另一极称为第二电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一电极可以为漏极，所述第二电极可以为源极；或者，所述第一电极可以为源极，所述第二电极可以为漏极。
本公开实施例所述的像素电路包括发光元件、驱动电路、第一储能电路、第二储能电路、数据写入电路和补偿控制电路；
所述第一储能电路的第一端与第一节点电连接，所述第一储能电路的第 二端与第二节点电连接，所述第一储能电路用于储存电能；
所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与第三节点电连接，所述第二储能电路用于储存电能；
所述驱动电路的控制端与所述第一节点电连接，所述驱动电路用于在其控制端的电位的控制下，驱动所述发光元件；
所述第三节点与所述发光元件的第一极电连接，所述发光元件的第二极与第一电压端电连接；
所述数据写入电路分别与扫描线、数据线和数据写入节点电连接，用于在所述扫描线提供的扫描信号的控制下，控制将所述数据线上的数据电压写入第二节点；
所述补偿控制电路分别与第一复位端、第二节点和补偿节点电连接，用于在所述第一复位信号的控制下，控制所述第二节点与所述补偿节点之间连通或断开；
所述补偿节点与所述第三节点电连接，和/或，所述补偿节点与所述驱动电路的第二端电连接；所述数据写入节点为所述第二节点或所述第三节点。
本公开实施例所述的像素电路在工作时，分时进行阈值电压补偿和数据电压写入，以能够在充分进行阈值电压补偿的前提下，实现高频驱动。
在本公开至少一实施例中，由于分时进行阈值电压补偿和数据电压写入，可以在较长时间内进行阈值电压补偿，从而可以对驱动电路包括的驱动晶体管的阈值电压充分进行补偿，并能够提升所述扫描线提供的扫描信号的频率，从而能够进行高频驱动。
在本公开至少一实施例中，所述驱动电路的第一端可以与电源电压端电连接，所述驱动电路的第二端可以与发光元件的第一极电连接；或者，
所述驱动电路的第一端可以通过第一发光控制电路与电源电压端电连接，所述驱动电路的第二端可以与发光元件的第一极电连接；或者，
所述驱动电路的第一端可以与电源电压端电连接，所述驱动电路的第二端可以通过第二发光控制电路与发光元件的第一极电连接；或者，
所述驱动电路的第一端可以通过第一发光控制电路与电源电压端电连接，所述驱动电路的第二端可以通过第二发光控制电路与发光元件的第一极电连 接；
但不以此为限。
如图1所示，本公开至少一实施例所述的像素电路包括发光元件E0、驱动电路10、第一储能电路11、第二储能电路12、数据写入电路13和补偿控制电路14；
所述第一储能电路11的第一端与第一节点N1电连接，所述第一储能电路11的第二端与第二节点N2电连接，所述第一储能电路11用于储存电能；
所述第二储能电路12的第一端与所述第二节点N2电连接，所述第二储能电路12的第二端与第三节点电连接，所述第二储能电路用于储存电能；
所述驱动电路10的控制端与所述第一节点N1电连接，所述驱动电路10的第一端与电源电压端ELVDD电连接，所述驱动电路10的第二端与发光元件E0的第一极电连接，所述驱动电路10用于在其控制端的电位的控制下，驱动所述发光元件E0；
所述发光元件E0的第二极与第一电压端V1电连接，所述第三节点N3与所述发光元件E0的第一极电连接；
所述数据写入电路13分别与扫描线G1、数据线Da和第二节点N2电连接，用于在所述扫描线G1提供的扫描信号的控制下，控制将所述数据线Da上的数据电压Vdata写入第二节点N2；
所述补偿控制电路14分别与第一复位端R1、第二节点N2和补偿节点N4电连接，用于在所述第一复位信号的控制下，控制所述第二节点N2与补偿节点N4之间连通或断开；
所述补偿节点N4与所述第三节点N3电连接。
在图1所示的至少一实施例中，数据写入节点为所述第二节点N2。
可选的，所述第一电压线可以为低电压线，但不以此为限。
本公开图1所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的补偿阶段、写入阶段和发光阶段；
在补偿阶段，所述补偿控制电路14在第一复位信号的控制下，控制第二节点N2与补偿节点N4之间连通；
在所述补偿阶段开始时，驱动电路10在其控制端的电位的控制下，控制 所述驱动电路10的第一端与所述驱动电路10的第二端之间连通，以通过电源电压端为第一储能电路11和第二储能电路12充电，直至所述驱动电路10在其控制端的电位的控制下，控制所述驱动电路10的第一端与所述驱动电路10的第二端之间断开；
在写入阶段，所述数据写入电路13在扫描信号的控制下，将数据线Da上的的数据电压Vdata写入第二节点N2，补偿控制电路14在第一复位信号的控制下，控制第二节点N2与补偿节点N4之间断开；
在发光阶段，驱动电路10驱动发光元件E0。
本公开图1所示的像素电路的至少一实施例在工作时，在补偿阶段，进行阈值电压补偿，在写入阶段进行数据电压写入，分时进行阈值电压补偿和数据电压写入，以能够在充分补偿阈值电压的同时，实现高频驱动。
本公开至少一实施例所述的像素电路还包括第一复位电路和第二复位电路；
所述第一复位电路分别与第一复位端、参考电压端和所述第一节点电连接，用于在所述第一复位端提供的第一复位信号的控制下，将所述参考电压端提供的参考电压写入所述第一节点；
所述第二复位电路分别与第二复位端、第一初始电压端和复位节点电连接，用于在所述第二复位端提供的第二复位信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述复位节点；
所述复位节点为第二节点或第三节点，所述第三节点与所述发光元件的第一极电连接。
在具体实施时，所述像素电路还可以包括第一复位电路和第二复位电路，第一复位电路在第一复位信号的控制下，将参考电压写入第一节点，第二复位电路在第二复位信号的控制下将第一初始电压写入复位节点。
如图2所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一复位电路21和第二复位电路22；
所述第一复位电路21分别与第一复位端R1、参考电压端VR和所述第一节点N1电连接，用于在所述第一复位端R1提供的第一复位信号的控制下，将所述参考电压端VR提供的参考电压Vref写入所述第一节点N1；
所述第二复位电路22分别与第二复位端R2、第一初始电压端I1和第三节点N3电连接，用于在所述第二复位端42提供的第二复位信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vinit1写入所述第三节点N3。
在图2所示的至少一实施例中，所述复位节点为所述第三节点。
如图3所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一复位电路21和第二复位电路22；
所述第一复位电路21分别与第一复位端R1、参考电压端VR和所述第一节点N1电连接，用于在所述第一复位端R1提供的第一复位信号的控制下，将所述参考电压端VR提供的参考电压Vref写入所述第一节点N1；
所述第二复位电路22分别与第二复位端R2、第一初始电压端I1和第二节点N2电连接，用于在所述第二复位端42提供的第二复位信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vinit1写入所述第二节点N2。
在图3所示的至少一实施例中，所述复位节点为所述第二节点。
本公开至少一实施例所述的像素电路还包括第三复位电路；
所述第三复位电路分别与所述扫描线、第二初始电压端和复位节点电连接，用于在所述扫描信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述复位节点；
所述数据写入节点为所述第二节点，所述复位节点为所述第三节点；或者，所述数据写入节点为所述第三节点，所述复位节点为所述第二节点。
在具体实施时，所述像素电路还可以包括第三复位电路，第三复位电路在扫描信号的控制下，将第二初始电压写入复位节点。
如图4所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第三复位电路41；
所述第三复位电路41分别与所述扫描线G1、第二初始电压端I2和所述第三节点N3电连接，用于在所述扫描信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vinit2写入所述第三节点N3。
在图4所示的至少一实施例中，复位节点为所述第三节点N3。
如图5所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第三复位电路41；
所述第三复位电路41分别与所述扫描线G1、第二初始电压端I2和所述第三节点N3电连接，用于在所述扫描信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vinit2写入所述第三节点N3。
在本公开至少一实施例中，所述像素电路还包括第一发光控制电路；
所述驱动电路的第一端通过所述第一发光控制电路与所述电源电压端电连接；所述驱动电路的第二端与所述发光元件的第一极电连接；
所述第一发光控制电路的控制端与发光控制线电连接，所述第一发光控制电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通或断开。
在具体实施时，所述像素电路还可以包括第一发光控制电路，第一发光控制电路在发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通或断开。
如图6所示，在图4所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一发光控制电路61；
所述驱动电路10的第一端通过所述第一发光控制电路61与所述电源电压端ELVDD电连接；
所述第一发光控制电路61的控制端与发光控制线EM电连接，所述第一发光控制电路61用于在所述发光控制线EM提供的发光控制信号的控制下，控制所述电源电压端ELVDD与所述驱动电路10的第一端之间连通或断开。
如图7所示，在图5所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第一发光控制电路61；
所述驱动电路10的第一端通过所述第一发光控制电路61与所述电源电压端ELVDD电连接；
所述第一发光控制电路61的控制端与发光控制线EM电连接，所述第一发光控制电路61用于在所述发光控制线EM提供的发光控制信号的控制下，控制所述电源电压端ELVDD与所述驱动电路10的第一端之间连通或断开。
本公开至少一实施例所述的像素电路还包括第二发光控制电路；
所述驱动电路的第一端与电源电压端电连接，所述驱动电路的第二端通过所述第二发光控制电路与所述发光元件的第一极电连接；
所述第二发光控制电路的控制端与发光控制线电连接，所述第二发光控制电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通或断开。
在具体实施时，所述像素电路还可以包括第二发光控制电路，第二发光控制电路在发光控制电路的控制下，控制驱动电路的第二端与发光元件的第一极之间连通或断开。
如图8所示，在图4所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二发光控制电路62；
所述驱动电路10的第二端通过所述第二发光控制电路62与所述发光元件E0的第一极电连接；
所述第二发光控制电路62的控制端与发光控制线EM电连接，所述第二发光控制电路62用于在所述发光控制线EM提供的发光控制信号的控制下，控制所述驱动电路10的第二端与所述发光元件E0的第一极之间连通或断开；
第二复位电路22与第三节点N3电连接，所述补偿节点N4与第三节点N3电连接。
如图9所示，在图5所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二发光控制电路62；
所述驱动电路10的第二端通过所述第二发光控制电路62与所述发光元件E0的第一极电连接；
所述第二发光控制电路62的控制端与发光控制线EM电连接，所述第二发光控制电路62用于在所述发光控制线EM提供的发光控制信号的控制下，控制所述驱动电路10的第二端与所述发光元件E0的第一极之间连通或断开；
所述补偿节点N4与第三节点N3电连接。
本公开图10所示的像素电路的至少一实施例与本公开图8所示的像素电路的至少一实施例的区别如下：所述补偿节点N4与驱动电路10的第二端电连接。
本公开图11所示的像素电路的至少一实施例与本公开图9所示的像素电路的至少一实施例的区别如下：所述补偿节点N4与驱动电路10的第二端电连接。
本公开图12所示的像素电路的至少一实施例与本公开图6所示的像素电路的至少一实施例的区别在于：数据写入节点为第三节点N3，复位节点为第二节点N2。
在本公开图12所示的像素电路的至少一实施例中，所述数据写入电路13分别与扫描线G1、数据线Da和第三节点N3电连接，用于在所述扫描线G1提供的扫描信号的控制下，控制将所述数据线Da上的数据电压Vdata写入第三节点N3；
所述第三复位电路41分别与所述扫描线G1、第二初始电压端I2和所述第二节点N2电连接，用于在所述扫描信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vinit2写入所述第二节点N2。
可选的，所述数据写入电路包括第一晶体管，所述补偿控制电路包括第二晶体管；
所述第一晶体管的栅极与所述扫描线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述数据写入节点电连接；
所述第二晶体管的栅极与所述第一复位端电连接，所述第二晶体管的第一极与所述第二节点电连接，所述第二晶体管的第二极与所述补偿节点电连接。
可选的，所述驱动电路包括驱动晶体管，所述第一复位电路包括第三晶体管，所述第二复位电路包括第四晶体管；
所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；
所述第三晶体管的栅极与所述第一复位端电连接，所述第三晶体管的第一极与所述参考电压端电连接，所述第三晶体管的第二极与所述第一节点电连接；
所述第四晶体管的栅极与所述第二复位端电连接，所述第四晶体管的第一极与所述第一初始电压端电连接，所述第四晶体管的第二极与所述复位节点电连接。
可选的，所述第一储能电路包括第一电容，所述第二储能电路包括第二 电容；
所述第一电容的第一端与第一节点电连接，所述第一电容的第二端与第二节点电连接；
所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与第三节点电连接。
可选的，所述第三复位电路包括第五晶体管；
所述第五晶体管的栅极与所述扫描线电连接，所述第五晶体管的第一极与所述第二初始电压端电连接，所述第五晶体管的第二极与所述复位节点电连接。
可选的，所述第一发光控制电路包括第六晶体管；
所述第六晶体管的栅极与所述发光控制线电连接，所述第六晶体管的第一极与所述电源电压端电连接，所述第六晶体管的第二极与所述驱动电路的第一端电连接。
可选的，所述第二发光控制电路包括第七晶体管；
所述第七晶体管的栅极与所述发光控制线电连接，所述第七晶体管的第一极与所述驱动电路的第二端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
如图13所示，在图6所示的像素电路的至少一实施例的基础上，所述发光元件为有机发光二极管O1；所述数据写入电路包括第一晶体管T1，所述补偿控制电路包括第二晶体管T2；
所述第一晶体管T1的栅极与所述扫描线G1电连接，所述第一晶体管T1的漏极与所述数据线Da电连接，所述第一晶体管T1的源极与所述第二节点N2电连接；
所述第二晶体管T2的栅极与所述第一复位端R1电连接，所述第二晶体管T2的漏极与所述第二节点N2电连接，所述第二晶体管T2的源极与补偿节点N4电连接；所述补偿节点N4与第三节点N3电连接，所述第三节点N3与所述有机发光二极管O1的阳极电连接；
所述驱动电路包括驱动晶体管T0，所述第一复位电路包括第三晶体管T3，所述第二复位电路包括第四晶体管T4；
所述驱动晶体管T0的栅极与所述第一节点N1电连接；
所述第三晶体管T3的栅极与所述第一复位端R1电连接，所述第三晶体管T3的漏极与所述参考电压端VR电连接，所述第三晶体管T3的源极与所述第一节点N1电连接；
所述第四晶体管T4的栅极与所述第二复位端R2电连接，所述第四晶体管T4的漏极与所述第一初始电压端I1电连接，所述第四晶体管T4的源极与所述第三节点N3电连接；
所述第一储能电路包括第一电容C1，所述第二储能电路包括第二电容C2；
所述第一电容C1的第一端与第一节点N1电连接，所述第一电容C1的第二端与第二节点N2电连接；
所述第二电容C2的第一端与所述第二节点N2电连接，所述第二电容C2的第二端与第三节点N3电连接；
所述第三复位电路包括第五晶体管T5；
所述第五晶体管T5的栅极与所述扫描线G1电连接，所述第五晶体管T5的漏极与所述第二初始电压端I2电连接，所述第五晶体管T5的源极与所述第三节点N3电连接；
所述第一发光控制电路包括第六晶体管T6；
所述第六晶体管T6的栅极与所述发光控制线EM电连接，所述第六晶体管T6的漏极与所述电源电压端ELVDD电连接，所述第六晶体管T6的源极与所述驱动晶体管T0的源极电连接；
所述驱动晶体管T0的漏极与有机发光二极管O1的阳极电连接；
有机发光二极管O1的阴极与低电压端ELVSS电连接。
在图13所示的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
在本公开至少一实施例中，T2的栅极和T3的栅极也可以与不同的控制端电连接，T1的栅极和T5的栅极也可以与不同的控制端电连接。
可选的，Vinit1的电压值可以与Vinit2的电压值相同，且都可以等于VSS，Vref也可以等于VDD，但不以此为限。
在本公开至少一实施例中，VDD为ELVDD提供的电源电压的电压值，VSS为ELVSS提供的低电压信号的电压值。
如图14所示，本公开图13所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的重置阶段S1、补偿阶段S2、写入阶段S3和发光阶段S4；
在重置阶段S1，EM提供低电压信号，R1提供高电压信号，R2提供高电压信号，G1提供低电压信号，T2和T3打开，以将参考电压端VR提供的参考电压Vref至第一节点N1，以使得在补偿阶段S2开始时，所述驱动晶体管T0能够导通，T4打开，I1提供的第一初始电压Vinit1写入N2和N4，完成对N2的电位和N4的电位的重置，由于N3与N4之间没有晶体管，可以同时完成对O1的阳极电压和N3的电位的重置；
在补偿阶段S2，EM提供高电压信号，R1提供高电压信号，R2提供低电压信号，G1提供低电压信号，T2、T3和T6打开；
在补偿阶段S2开始时，T0打开，ELVDD提供的电源电压通过T6、T0、T2为电容充电，以改变N4的电位，直至N4的电位变为Vref-Vth时，T0关断，完成对T0的阈值电压补偿；Vref-VDD需要小于T0的阈值电压Vth，以使得T0能够关断；
在写入阶段S3，EM提供低电压信号，R1和R2提供低电压信号，G1提供高电压信号，Da提供数据电压Vdata，T5和T1开启，数据线Da将数据电压Vdata写入第二节点N2，I2将第二初始电压Vinit2写入第三节点N3，第一节点N1处于浮空状态，N1的电位随着N2的电位的变化而变化，变化量相等，Vdata通过T1写入N2，N2的电位由Vref-Vth变为Vdata，N2的电位的变化量为Vdata-(Vref-Vth)，此时N1的电位变为Vref+Vdata-(Vref-Vth)，也即N1的电位变为Vdata+Vth；T5开启，N3的电位变为Vinit2，N1的电位与N3的电位的差值为Vdata+Vth-Vinit2；
在发光阶段S4，EM提供高电压信号，R1和R2提供低电压信号，G1提供低电压信号，T0和T6打开，N1和N2处于浮空状态，N1的电位和N2的电位随着N3的电位变化而变化，变化量相等，T0驱动O1充电，直到O1稳定发光，此时N3的电位为VSS+Voled，Voled为O1的启亮电压，N3的电 位变化量为VSS+Voled-Vinit2，N1的电位为VSS+Voled-Vinit2+Vdata+Vth；T0的栅源电压为Vdata+Vth-Vinit2，T0工作于饱和工作区间；
在发光阶段S4，T0驱动O1发光的驱动电流I等于K(Vdata-Vinit2)2；
其中，K为T0的电流系数，可见驱动电流I与驱动晶体管T0的阈值电压、VSS和Voled均不相关，也即，本公开图13所示的像素电路的至少一实施例能够补偿驱动晶体管T0的阈值电压不均匀、低电压端ELVSS的压降，和有机发光二极管老化所导致的显示不均的问题，从而提升显示效果。
本公开图13所示的像素电路的至少一实施例在工作时，由于阈值电压补偿过程和数据电压写入的过程是分离的，阈值电压补偿可以进行较长时间，保证能够更好的进行阈值电压补偿，并可以提升驱动速率，例如，驱动频率可以为120Hz、180Hz或240Hz，有利于游戏等领域场景的效果的改善，且可提高发光电流的精度，改善显示质量。
本公开图13所示的像素电路的至少一实施例在工作时，仅需要采用四组GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)，以分别提供发光控制信号，第一复位信号、第二复位信号和扫描信号，可以减少采用的GOA的数目，利于实现窄边框。
本公开图15所示的像素电路的至少一实施例与本公开图12所示的像素电路的至少一实施例的区别在于：不设置有用于发光控制的第六晶体管T6。
本公开图15所示的像素电路的至少一实施例可以仅采用三组GOA，以能进一步实现窄边框。
图16是本公开图15所示的像素电路的至少一实施例的工作时序图。
本公开图17所示的像素电路的至少一实施例与本公开图15所示的像素电路的至少一实施例的区别在于：T4的源极与第二节点N2电连接。
如图18所示，本公开图17所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的重置阶段S1、补偿阶段S2、数据写入阶段S3和发光阶段S4；
在重置阶段S1，R1和R2都提供高电压信号，G1提供低电压信号，T2、T3和T4都打开，I1将第一初始电压Vinit1写入N2、N3和N4，VR提供参考电压Vref写入N1；
在补偿阶段S2，R1提供高电压信号，R2提供低电压信号，G1提供低电压信号，T2和T3打开；
在补偿阶段S2开始时，T0打开，ELVDD提供的电源电压通过T0和T2为电容充电，以改变N4的电位，直至N4的电位变为Vref-Vth时，T0关断，完成对T0的阈值电压补偿；Vref-VDD需要小于T0的阈值电压Vth；
在写入阶段S3，R1和R2提供低电压信号，G1提供高电压信号，Da提供数据电压Vdata，T5和T1开启，数据线Da将数据电压Vdata写入第二节点N2，I2将第二初始电压Vinit2写入第三节点N3，第一节点N1处于浮空状态，N1的电位随着N2的电位的变化而变化，变化量相等，Vdata通过T1写入N2，N2的电位由Vref-Vth变为Vdata，N2的电位的变化量为Vdata-(Vref-Vth)，此时N1的电位变为Vref+Vdata-(Vref-Vth)，也即N1的电位变为Vdata+Vth；T5开启，N3的电位变为Vinit2，N1的电位与N3的电位的差值为Vdata+Vth-Vinit2；
在发光阶段S4，R1和R2提供低电压信号，G1提供低电压信号，T0和N1和N2处于浮空状态，N1的电位和N2的电位随着N3的电位变化而变化，变化量相等，T0驱动O1充电，直到O1稳定发光，此时N3的电位为VSS+Voled，Voled为O1的启亮电压，N3的电位变化量为VSS+Voled-Vinit2，N1的电位为VSS+Voled-Vinit2+Vdata+Vth；T0的栅源电压为Vdata+Vth-Vinit2，T0工作于饱和工作区间；
在发光阶段S4，T0驱动O1发光的驱动电流I等于K(Vdata-Vinit2)2；
其中，K为T0的电流系数，可见驱动电流I与驱动晶体管T0的阈值电压、VSS和Voled均不相关，也即，本公开图17所示的像素电路的至少一实施例能够补偿驱动晶体管T0的阈值电压不均匀、低电压端ELVSS的压降，和有机发光二极管老化所导致的显示不均的问题，从而提升显示效果。
本公开图17所示的像素电路的至少一实施例可以仅采用三组GOA，以能进一步实现窄边框。
本公开图19所示的像素电路的至少一实施例与本公开图15所示的像素电路的至少一实施例的区别在于：不设置T5。
如图20所示，本公开图19所示的像素电路的至少一实施例在工作时， 显示周期包括先后设置的重置阶段S1、补偿阶段S2、数据写入阶段S3和发光阶段S4；
在重置阶段S1，R1和R2都提供高电压信号，G1提供低电压信号，T2、T3和T4都打开，I1将第一初始电压Vinit1写入N2、N3和N4，VR提供参考电压Vref写入N1；
在补偿阶段S2，R1提供高电压信号，R2提供低电压信号，G1提供低电压信号，T2和T3打开；
在补偿阶段S2开始时，T0打开，ELVDD提供的电源电压通过T0和T2为电容充电，以改变N4的电位，直至N4的电位变为Vref-Vth时，T0关断，完成对T0的阈值电压补偿；Vref-VDD需要小于T0的阈值电压Vth；
在数据写入阶段S3，R1提供低电压信号，R2提供高电压信号，G1提供高电压信号，T4打开，I1提供第一初始电压Vinit1至N3，Da提供数据电压Vdata，T2打开，数据线Da将数据电压Vdata写入第二节点N2，第一节点N1处于浮空状态，N1的电位随着N2的电位的变化而变化，变化量相等，Vdata通过T1写入N2，N2的电位由Vref-Vth变为Vdata，N2的电位的变化量为Vdata-(Vref-Vth)，此时N1的电位变为Vref+Vdata-(Vref-Vth)，也即N1的电位变为Vdata+Vth；T4开启，N3的电位变为Vinit1，N1的电位与N3的电位的差值为Vdata+Vth-Vinit1；
在发光阶段S4，R1和R2提供低电压信号，G1提供低电压信号，T0和N1和N2处于浮空状态，N1的电位和N2的电位随着N3的电位变化而变化，变化量相等，T0驱动O1充电，直到O1稳定发光，此时N3的电位为VSS+Voled，Voled为O1的启亮电压，N3的电位变化量为VSS+Voled-Vinit2，N1的电位为VSS+Voled-Vinit1+Vdata+Vth；T0的栅源电压为Vdata+Vth-Vinit1，T0工作于饱和工作区间；
在发光阶段S4，T0驱动O1发光的驱动电流I等于K(Vdata-Vinit1)2；
其中，K为T0的电流系数，可见驱动电流I与驱动晶体管T0的阈值电压、VSS和Voled均不相关，也即，本公开图19所示的像素电路的至少一实施例能够补偿驱动晶体管T0的阈值电压不均匀、低电压端ELVSS的压降，和有机发光二极管老化所导致的显示不均的问题，从而提升显示效果。
本公开图19所示的像素电路的至少一实施例可以仅采用三组GOA，以能进一步实现窄边框。
在本公开图19所示的像素电路的至少一实施例中，T4的源极可以被替换为与第二节点N2电连接。
本公开图21所示的像素电路的至少一实施例与本公开图19所示的像素电路的至少一实施例的区别在于：增设了第六晶体管T6；
所述第六晶体管T6的栅极与所述发光控制线EM电连接，所述第六晶体管T6的漏极与所述电源电压端ELVDD电连接，所述第六晶体管T6的源极与所述驱动晶体管T0的源极电连接。
如图22所示，本公开图21所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的重置阶段S1、补偿阶段S2、数据写入阶段S3和发光阶段S4；
在重置阶段S1，EM提供低电压信号，R1和R2都提供高电压信号，G1提供低电压信号，T2、T3和T4都打开，I1将第一初始电压Vinit1写入N2、N3和N4，VR提供参考电压Vref写入N1；
在补偿阶段S2，R1提供高电压信号，R2提供低电压信号，G1提供低电压信号，T2和T3打开；EM提供高电压信号，T6打开，
在补偿阶段S2开始时，T0打开，ELVDD提供的电源电压通过T6、T0和T2为电容充电，以改变N4的电位，直至N4的电位变为Vref-Vth时，T0关断，完成对T0的阈值电压补偿；Vref-VDD需要小于T0的阈值电压Vth；
在数据写入阶段S3，EM提供低电压信号，R1提供低电压信号，R2提供高电压信号，G1提供高电压信号，T4打开，I1提供第一初始电压Vinit1至N3，Da提供数据电压Vdata，T2打开，数据线Da将数据电压Vdata写入第二节点N2，第一节点N1处于浮空状态，N1的电位随着N2的电位的变化而变化，变化量相等，Vdata通过T1写入N2，N2的电位由Vref-Vth变为Vdata，N2的电位的变化量为Vdata-(Vref-Vth)，此时N1的电位变为Vref+Vdata-(Vref-Vth)，也即N1的电位变为Vdata+Vth；T4开启，N3的电位变为Vinit1，N1的电位与N3的电位的差值为Vdata+Vth-Vinit1；
在发光阶段S4，EM提供高电压信号，T6打开，R1和R2提供低电压信 号，G1提供低电压信号，T0和N1和N2处于浮空状态，N1的电位和N2的电位随着N3的电位变化而变化，变化量相等，T0驱动O1充电，直到O1稳定发光，此时N3的电位为VSS+Voled，Voled为O1的启亮电压，N3的电位变化量为VSS+Voled-Vinit2，N1的电位为VSS+Voled-Vinit1+Vdata+Vth；T0的栅源电压为Vdata+Vth-Vinit1，T0工作于饱和工作区间；
在发光阶段S4，T0驱动O1发光的驱动电流I等于K(Vdata-Vinit1)2；
其中，K为T0的电流系数，可见驱动电流I与驱动晶体管T0的阈值电压、VSS和Voled均不相关，也即，本公开图21所示的像素电路的至少一实施例能够补偿驱动晶体管T0的阈值电压不均匀、低电压端ELVSS的压降，和有机发光二极管老化所导致的显示不均的问题，从而提升显示效果。
本公开图21所示的像素电路的至少一实施例可以仅采用四组GOA，以能进一步实现窄边框。
本公开图21所示的像素电路的至少一实施例增设了用于发光控制的第六晶体管T6，T6在重置阶段和数据写入阶段处于关闭状态，避免在重置阶段和数据写入阶段，在ELVDD与I1之间产生电流，增加功耗。
本公开图23所示的像素电路的至少一实施例与本公开图13所示的像素电路的至少一实施例的区别在于：不设置有第六晶体管T6；还包括第七晶体管T7；
第七晶体管T7设置于驱动晶体管T0的漏极与有机发光二极管O1的阳极之间；
补偿节点N4与第三节点N3电连接；第三节点N3与O1的阳极电连接；
T7的栅极与发光控制线EM电连接；
T7的源极与驱动晶体管T0的漏极电连接，T7的漏极与O1的阳极电连接。
如图24所示，本公开图23所示的像素电路的至少一实施例在工作时，
显示周期可以包括先后设置的重置阶段S1、补偿阶段S2、写入阶段S3和发光阶段S4；
在重置阶段S1，EM提供低电压信号，R1提供高电压信号，R2提供高电压信号，G1提供低电压信号，T2和T3打开，以将参考电压端VR提供的 参考电压Vref至第一节点N1，以使得在补偿阶段S2开始时，所述驱动晶体管T0能够导通，T4打开，I1提供的第一初始电压Vinit1写入N2和N4，完成对N2的电位和N4的电位的重置，由于N3与N4之间没有晶体管，可以同时完成对O1的阳极电压和N3的电位的重置；
在补偿阶段S2，EM提供高电压信号，R1提供高电压信号，R2提供低电压信号，G1提供低电压信号，T2、T3和T7打开；
在补偿阶段S2开始时，T0打开，ELVDD提供的电源电压通过T7、T0、T2为电容充电，以改变N4的电位，直至N4的电位变为Vref-Vth时，T0关断，完成对T0的阈值电压补偿；Vref-VDD需要小于T0的阈值电压Vth；
在写入阶段S3，EM提供低电压信号，R1和R2提供低电压信号，G1提供高电压信号，Da提供数据电压Vdata，T5和T1开始，数据线Da将数据电压Vdata写入第二节点N2，I2将第二初始电压Vinit2写入第三节点N3，第一节点N1处于浮空状态，N1的电位随着N2的电位的变化而变化，变化量相等，Vdata通过T1写入N2，N2的电位由Vref-Vth变为Vdata，N2的电位的变化量为Vdata-(Vref-Vth)，此时N1的电位变为Vref+Vdata-(Vref-Vth)，也即N1的电位变为Vdata+Vth；T5开启，N3的电位变为Vinit2，N1的电位与N3的电位的差值为Vdata+Vth-Vinit2；
在发光阶段S4，EM提供高电压信号，R1和R2提供低电压信号，G1提供低电压信号，T0和T7打开，N1和N2处于浮空状态，N1的电位和N2的电位随着N3的电位变化而变化，变化量相等，T0驱动O1充电，直到O1稳定发光，此时N3的电位为VSS+Voled，Voled为O1的启亮电压，N3的电位变化量为VSS+Voled-Vinit2，N1的电位为VSS+Voled-Vinit2+Vdata+Vth；T0的栅源电压为Vdata+Vth-Vinit2，T0工作于饱和工作区间；
在发光阶段S4，T0驱动O1发光的驱动电流I等于K(Vdata-Vinit2)2；
其中，K为T0的电流系数，可见驱动电流I与驱动晶体管T0的阈值电压、VSS和Voled均不相关，也即，本公开图23所示的像素电路的至少一实施例能够补偿驱动晶体管T0的阈值电压不均匀、低电压端ELVSS的压降，和有机发光二极管老化所导致的显示不均的问题，从而提升显示效果。
在本公开至少一实施例中，VDD为ELVDD提供的电源电压的电压值， VSS为ELVSS提供的低电压信号的电压值。
本公开图25所示的像素电路的至少一实施例与本公开图23所示的像素电路的至少一实施例的区别在于：补偿节点N4与T0的漏极电连接。
本公开图26所示的像素电路的至少一实施例与本公开图13所示的像素电路的至少一实施例的区别在于：数据写入节点为第三节点N3，复位节点为第二节点N2。
在本公开图26所示的像素电路的至少一实施例中，
所述第一晶体管T1的栅极与所述扫描线G1电连接，所述第一晶体管T1的漏极与所述数据线Da电连接，所述第一晶体管T1的源极与所述第三节点N3电连接；
所述第五晶体管T5的栅极与所述扫描线G1电连接，所述第五晶体管T5的漏极与所述第二初始电压端I2电连接，所述第五晶体管T5的源极与所述第二节点N2电连接。
如图27所示，本公开图26所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的重置阶段S1、补偿阶段S2、写入阶段S3和发光阶段S4；
在重置阶段S1，EM提供低电压信号，R1提供高电压信号，R2提供高电压信号，G1提供低电压信号，T2和T3打开，以将参考电压端VR提供的参考电压Vref至第一节点N1，以使得在补偿阶段S2开始时，所述驱动晶体管T0能够导通，T4打开，I1提供的第一初始电压Vinit1写入N2和N4，完成对N2的电位和N4的电位的重置，由于N3与N4之间没有晶体管，可以同时完成对O1的阳极电压和N3的电位的重置；
在补偿阶段S2，EM提供高电压信号，R1提供高电压信号，R2提供低电压信号，G1提供低电压信号，T2、T3和T6打开；
在补偿阶段S2开始时，T0打开，ELVDD提供的电源电压通过T6、T0、T2为电容充电，以改变N4的电位，直至N4的电位变为Vref-Vth时，T0关断，完成对T0的阈值电压补偿；Vref-VDD需要小于T0的阈值电压Vth，以使得T0能够关断；
在写入阶段S3，EM提供低电压信号，R1和R2提供低电压信号，G1 提供高电压信号，Da提供数据电压Vdata，T5和T1开启，数据线Da将数据电压Vdata写入第三节点N3，I2将第二初始电压Vinit2写入第二节点N2，第一节点N1处于浮空状态，N1的电位随着N2的电位的变化而变化，变化量相等，Vinit2通过T5写入N2，N2的电位由Vref-Vth变为Vinit2，N2的电位的变化量为Vinit2-(Vref-Vth)，此时N1的电位变为Vref+Vinit2-(Vref-Vth)，也即N1的电位变为Vinit2+Vth；T2开启，N3的电位变为Vdata，N1的电位与N3的电位的差值为Vinit2+Vth-Vdata；
在发光阶段S4，EM提供高电压信号，R1和R2提供低电压信号，G1提供低电压信号，T0和T6打开，N1和N2处于浮空状态，N1的电位和N2的电位随着N3的电位变化而变化，变化量相等，T0驱动O1充电，直到O1稳定发光，此时N3的电位为VSS+Voled，Voled为O1的启亮电压，N3的电位变化量为VSS+Voled-Vdata；
N1的电位为VSS+Voled-Vdata+Vinit2+Vth；T0的栅源电压为Vinit2+Vth-Vdata，T0工作于饱和工作区间；
在发光阶段S4，T0驱动O1发光的驱动电流I等于K(Vinit2-Vdata)2；
其中，K为T0的电流系数，可见驱动电流I与驱动晶体管T0的阈值电压、VSS和Voled均不相关，也即，本公开图26所示的像素电路的至少一实施例能够补偿驱动晶体管T0的阈值电压不均匀、低电压端ELVSS的压降，和有机发光二极管老化所导致的显示不均的问题，从而提升显示效果。
在图26所示的像素电路的至少一实施例中，可以不设置第六晶体管T6。
在图26所示的像素电路的至少一实施例中，可以不设置第六晶体管T6，并在T0的漏极与O1的阳极之间可以设置第七晶体管T7，此时补偿节点N4可以与O1的阳极或T0的漏极电连接。
本公开实施例所述的像素驱动方法，应用于上述的像素电路，显示周期包括先后设置的补偿阶段、写入阶段和发光阶段，所述像素驱动方法包括：
在补偿阶段，所述补偿控制电路在第一复位信号的控制下，控制第二节点与补偿节点之间连通；
在所述补偿阶段开始时，驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以通过电源电压端 为第一储能电路和第二储能电路充电，直至所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间断开；
在写入阶段，所述数据写入电路在扫描信号的控制下，将数据线上的的数据电压写入数据写入节点，补偿控制电路在第一复位信号的控制下，控制第二节点与补偿节点之间断开；
在发光阶段，驱动电路驱动发光元件。
在本公开至少一实施例所述的像素驱动方法中，在补偿阶段，进行阈值电压补偿，在写入阶段进行数据电压写入，分时进行阈值电压补偿和数据电压写入，以能够在充分补偿阈值电压的同时，实现高频驱动。
在本公开至少一实施例中，所述显示周期还包设置于所述补偿阶段之前的重置阶段；所述像素驱动方法还包括：
在重置阶段和补偿阶段，第一复位电路在第一复位信号的控制下，将参考电压写入第一节点；
在重置阶段，第二复位电路在第二复位信号的控制下，将第一初始电压写入复位节点。
本公开至少一实施例所述的像素驱动方法还包括：
在所述重置阶段，所述补偿控制电路在所述第一复位信号的控制下，控制控制第二节点与补偿节点之间连通。
可选的，本公开至少一实施例所述的像素驱动方法还可以包括：
在写入阶段，第二复位电路在第二复位信号的控制下，将第一初始电压写入复位节点。
在本公开至少一实施例中，所述像素电路还包括第三复位电路；所述像素驱动方法还包括：
在所述写入阶段，所述第三复位电路在扫描信号的控制下，将第二初始电压写入复位节点。
在本公开至少一实施例中，所述像素电路还包括第一发光控制电路；所述像素驱动方法还包括：
在补偿阶段和发光阶段，第一发光控制控制电路在发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通。
可选的，所述像素电路还包括第二发光控制电路；本公开至少一实施例所述的像素驱动方法还包括：
在补偿阶段和发光阶段，第二发光控制控制电路在发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间连通。
本公开实施例所述的显示装置包括上述的像素电路。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (19)

  1. 一种像素电路，包括发光元件、驱动电路、第一储能电路、第二储能电路、数据写入电路和补偿控制电路；
    所述第一储能电路的第一端与第一节点电连接，所述第一储能电路的第二端与第二节点电连接，所述第一储能电路用于储存电能；
    所述第二储能电路的第一端与所述第二节点电连接，所述第二储能电路的第二端与第三节点电连接，所述第二储能电路用于储存电能；
    所述驱动电路的控制端与所述第一节点电连接，所述驱动电路用于在其控制端的电位的控制下，驱动所述发光元件；
    所述第三节点与所述发光元件的第一极电连接，所述发光元件的第二极与第一电压端电连接；
    所述数据写入电路分别与扫描线、数据线和数据写入节点电连接，用于在所述扫描线提供的扫描信号的控制下，控制将所述数据线上的数据电压写入所述数据写入节点；
    所述补偿控制电路分别与第一复位端、第二节点和补偿节点电连接，用于在所述第一复位信号的控制下，控制所述第二节点与所述补偿节点之间连通或断开；
    所述补偿节点与所述第三节点电连接，和/或，所述补偿节点与所述驱动电路的第二端电连接；所述数据写入节点为所述第二节点或所述第三节点。
  2. 如权利要求1所述的像素电路，其中，还包括第一复位电路和第二复位电路；
    所述第一复位电路分别与第一复位端、参考电压端和所述第一节点电连接，用于在所述第一复位端提供的第一复位信号的控制下，将所述参考电压端提供的参考电压写入所述第一节点；
    所述第二复位电路分别与第二复位端、第一初始电压端和复位节点电连接，用于在所述第二复位端提供的第二复位信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述复位节点；
    所述复位节点为第二节点或第三节点。
  3. 如权利要求2所述的像素电路，其中，还包括第三复位电路；
    所述第三复位电路分别与所述扫描线、第二初始电压端和复位节点电连接，用于在所述扫描信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述复位节点；
    所述数据写入节点为所述第二节点，所述复位节点为所述第三节点；或者，所述数据写入节点为所述第三节点，所述复位节点为所述第二节点。
  4. 如权利要求2所述的像素电路，其中，还包括第一发光控制电路；
    所述驱动电路的第一端通过所述第一发光控制电路与电源电压端电连接；所述驱动电路的第二端与所述发光元件的第一极电连接；
    所述第一发光控制电路的控制端与发光控制线电连接，所述第一发光控制电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述电源电压端与所述驱动电路的第一端之间连通或断开。
  5. 如权利要求2所述的像素电路，其中，还包括第二发光控制电路；
    所述驱动电路的第一端与电源电压端电连接，所述驱动电路的第二端通过所述第二发光控制电路与所述发光元件的第一极电连接；
    所述第二发光控制电路的控制端与发光控制线电连接，所述第二发光控制电路用于在所述发光控制线提供的发光控制信号的控制下，控制所述驱动电路的第二端与所述发光元件的第一极之间连通或断开。
  6. 如权利要求1至5中任一权利要求所述的像素电路，其中，所述数据写入电路包括第一晶体管，所述补偿控制电路包括第二晶体管；
    所述第一晶体管的栅极与所述扫描线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极与所述数据写入节点电连接；
    所述第二晶体管的栅极与所述第一复位端电连接，所述第二晶体管的第一极与所述第二节点电连接，所述第二晶体管的第二极与所述补偿节点电连接。
  7. 如权利要求2至4中任一权利要求所述的像素电路，其中，所述驱动电路包括驱动晶体管，所述第一复位电路包括第三晶体管，所述第二复位电路包括第四晶体管；
    所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一 极与所述驱动电路的第一端电连接，所述驱动晶体管的第二极与所述驱动电路的第二端电连接；
    所述第三晶体管的栅极与所述第一复位端电连接，所述第三晶体管的第一极与所述参考电压端电连接，所述第三晶体管的第二极与所述第一节点电连接；
    所述第四晶体管的栅极与所述第二复位端电连接，所述第四晶体管的第一极与所述第一初始电压端电连接，所述第四晶体管的第二极与所述复位节点电连接。
  8. 如权利要求1至4中任一权利要求所述的像素电路，其中，所述第一储能电路包括第一电容，所述第二储能电路包括第二电容；
    所述第一电容的第一端与第一节点电连接，所述第一电容的第二端与第二节点电连接；
    所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与第三节点电连接。
  9. 如权利要求3所述的像素电路，其中，所述第三复位电路包括第五晶体管；
    所述第五晶体管的栅极与所述扫描线电连接，所述第五晶体管的第一极与所述第二初始电压端电连接，所述第五晶体管的第二极与所述复位节点电连接。
  10. 如权利要求4所述的像素电路，其中，所述第一发光控制电路包括第六晶体管；
    所述第六晶体管的栅极与所述发光控制线电连接，所述第六晶体管的第一极与所述电源电压端电连接，所述第六晶体管的第二极与所述驱动电路的第一端电连接。
  11. 如权利要求5所述的像素电路，其中，所述第二发光控制电路包括第七晶体管；
    所述第七晶体管的栅极与所述发光控制线电连接，所述第七晶体管的第一极与所述驱动电路的第二端电连接，所述第七晶体管的第二极与所述发光元件的第一极电连接。
  12. 一种像素驱动方法，应用于如权利要求1至11中任一权利要求所述的像素电路，显示周期包括先后设置的补偿阶段、写入阶段和发光阶段，所述像素驱动方法包括：
    在补偿阶段，所述补偿控制电路在第一复位信号的控制下，控制第二节点与补偿节点之间连通；
    在所述补偿阶段开始时，驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间连通，以通过电源电压端为第一储能电路和第二储能电路充电，直至所述驱动电路在其控制端的电位的控制下，控制所述驱动电路的第一端与所述驱动电路的第二端之间断开；
    在写入阶段，所述数据写入电路在扫描信号的控制下，将数据线上的的数据电压写入数据写入节点，补偿控制电路在第一复位信号的控制下，控制第二节点与补偿节点之间断开；
    在发光阶段，驱动电路驱动发光元件。
  13. 如权利要求12所述的像素驱动方法，其中，所述显示周期还包设置于所述补偿阶段之前的重置阶段；所述像素驱动方法还包括：
    在重置阶段和补偿阶段，第一复位电路在第一复位信号的控制下，将参考电压写入第一节点；
    在重置阶段，第二复位电路在第二复位信号的控制下，将第一初始电压写入复位节点。
  14. 如权利要求13所述的像素驱动方法，其中，还包括：
    在所述重置阶段，所述补偿控制电路在所述第一复位信号的控制下，控制控制第二节点与补偿节点之间连通。
  15. 如权利要求13所述的像素驱动方法，其中，所述像素驱动方法包括：
    在写入阶段，第二复位电路在第二复位信号的控制下，将第一初始电压写入复位节点。
  16. 如权利要求13或14所述的像素驱动方法，其中，所述像素电路还包括第三复位电路；所述像素驱动方法还包括：
    在所述写入阶段，所述第三复位电路在扫描信号的控制下，将第二初始电压写入复位节点。
  17. 如权利要求13至15中任一权利要求所述的像素驱动方法，其中，所述像素电路还包括第一发光控制电路；所述像素驱动方法还包括：
    在补偿阶段和发光阶段，第一发光控制控制电路在发光控制信号的控制下，控制电源电压端与驱动电路的第一端之间连通。
  18. 如权利要求13至15中任一权利要求所述的像素驱动方法，其中，所述像素电路还包括第二发光控制电路；所述像素驱动方法还包括：
    在补偿阶段和发光阶段，第二发光控制控制电路在发光控制信号的控制下，控制驱动电路的第二端与发光元件的第一极之间连通。
  19. 一种显示装置，包括如权利要求1至11中任一权利要求所述的像素电路。
PCT/CN2023/073816 2023-01-30 2023-01-30 像素电路、像素驱动方法和显示装置 Ceased WO2024159352A1 (zh)

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