WO2024154544A1 - 酸化物半導体膜、薄膜トランジスタ、および電子機器 - Google Patents

酸化物半導体膜、薄膜トランジスタ、および電子機器 Download PDF

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WO2024154544A1
WO2024154544A1 PCT/JP2023/046219 JP2023046219W WO2024154544A1 WO 2024154544 A1 WO2024154544 A1 WO 2024154544A1 JP 2023046219 W JP2023046219 W JP 2023046219W WO 2024154544 A1 WO2024154544 A1 WO 2024154544A1
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Prior art keywords
oxide semiconductor
semiconductor film
film
peak
oxide
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English (en)
French (fr)
Japanese (ja)
Inventor
創 渡壁
将志 津吹
俊成 佐々木
尊也 田丸
真里奈 望月
涼 小野寺
将弘 渡部
大地 佐々木
絵美 川嶋
勇輝 霍間
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Idemitsu Kosan Co Ltd
Japan Display Inc
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Idemitsu Kosan Co Ltd
Japan Display Inc
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Priority to CN202380086602.0A priority Critical patent/CN120513703A/zh
Priority to JP2024571676A priority patent/JPWO2024154544A1/ja
Priority to KR1020257019624A priority patent/KR20250110870A/ko
Priority to DE112023004843.6T priority patent/DE112023004843T5/de
Publication of WO2024154544A1 publication Critical patent/WO2024154544A1/ja
Priority to US19/260,713 priority patent/US20260006848A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/875—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being semiconductor metal oxide, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • One embodiment of the present invention relates to an oxide semiconductor (Poly-OS) film having a polycrystalline structure. Another embodiment of the present invention relates to a thin-film transistor including a Poly-OS film. Another embodiment of the present invention relates to an electronic device including a thin-film transistor.
  • Oxide semiconductor Poly-OS
  • a thin-film transistor including a Poly-OS film.
  • an electronic device including a thin-film transistor.
  • thin-film transistors that use oxide semiconductor films as channels instead of silicon semiconductor films such as amorphous silicon, low-temperature polysilicon, and single-crystal silicon have been developed (see, for example, Patent Documents 1 to 6).
  • Thin-film transistors that include such oxide semiconductor films can be formed with a simple structure and low-temperature process, similar to thin-film transistors that include amorphous silicon films.
  • Thin-film transistors that include oxide semiconductor films are also known to have higher field-effect mobility than thin-film transistors that include amorphous silicon films.
  • the oxide semiconductor film according to one embodiment of the present invention is a crystalline oxide semiconductor film, which contains indium (In) and a first metal element (M1) selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanoid elements, the crystal structure of the oxide semiconductor film is a bixbyite structure, and in the diffraction pattern of the oxide semiconductor film obtained by out-of-plane XRD measurement using Cu-K ⁇ radiation, at least a first peak of the (222) plane and a second peak of the (440) plane are observed, and the ratio of the intensity of the first peak to the intensity of the second peak is 125 or less.
  • M1 selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanoid elements
  • a thin-film transistor according to one embodiment of the present invention includes the above-mentioned oxide semiconductor thin film as a channel.
  • An electronic device includes the above-described thin-film transistor.
  • 1 is an example of a diffraction pattern of an oxide semiconductor film according to an embodiment of the present invention, obtained by out-of-plane XRD measurement.
  • 1 is a schematic cross-sectional view showing a configuration of a thin film transistor according to one embodiment of the present invention.
  • 1 is a schematic plan view illustrating a configuration of a thin film transistor according to an embodiment of the present invention.
  • 2 is a flowchart showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1A to 1C are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1A to 1C are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1A to 1C are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1A to 1C are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1A to 1C are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1A to 1C are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1A to 1C are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1A to 1C are schematic cross-sectional views showing a method for manufacturing a thin film transistor according to an embodiment of the present invention.
  • 1 is a schematic diagram illustrating an electronic device according to an embodiment of the present invention. 1 is a graph in which the field-effect mobility of a thin film transistor is plotted against the (222)/(440)
  • the direction from the substrate toward the oxide semiconductor layer is referred to as “up” or “upper”. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as “down” or “downper”.
  • up or downper are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is reversed from that shown in the figure.
  • the expression “oxide semiconductor layer on a substrate” merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer.
  • Up or “downper” refers to the order of stacking in a structure in which multiple layers are stacked, and when referring to a pixel electrode above a thin film transistor, the thin film transistor and the pixel electrode may not overlap in a planar view. On the other hand, when referring to a pixel electrode vertically above a thin film transistor, the thin film transistor and the pixel electrode may overlap in a planar view.
  • film and “layer” may be used interchangeably in some cases.
  • the term “display device” refers to a structure that displays an image using an electro-optical layer.
  • the term display device may refer to a display panel that includes an electro-optical layer, or may refer to a structure in which other optical components (e.g., polarizing components, backlights, touch panels, etc.) are attached to a display cell.
  • the "electro-optical layer” may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless a technical contradiction occurs.
  • the oxide semiconductor film according to this embodiment includes indium (In) and at least one or more metal elements (M) other than indium. That is, the metal elements other than indium contained in the oxide semiconductor film may be one type of metal element or may be a plurality of types of metal elements.
  • the composition ratio of the oxide semiconductor film is preferably such that the atomic ratio of indium and at least one or more metal elements satisfies formula (1). In other words, the ratio of indium to all metal elements in the oxide semiconductor film is preferably 50% or more.
  • the crystal structure of the oxide semiconductor film preferably has a bixbyite structure. By increasing the ratio of indium, an oxide semiconductor film having a bixbyite structure can be formed.
  • the at least one metal element is preferably, for example, one or more elements selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanoid elements.
  • the first metal element contained in the at least one metal element is preferably gallium.
  • Gallium belongs to the same group 13 element as indium, and therefore does not impair the crystallinity of the oxide semiconductor film. In other words, even if the oxide semiconductor film contains gallium as the first metal element, an oxide semiconductor film having a bixbyite structure can be formed.
  • the oxide semiconductor film may contain a second metal element (M2) selected from the group consisting of aluminum, yttrium, scandium, and lanthanoid elements.
  • M2 a second metal element selected from the group consisting of aluminum, yttrium, scandium, and lanthanoid elements.
  • the atomic ratios of indium, gallium, and the second metal element preferably satisfy formulas (2), (3), and (4). Since the ratio of the second metal element is lower than the ratio of indium or gallium, the second metal element does not inhibit the crystallinity of the oxide semiconductor film.
  • the oxide semiconductor film can be formed by a sputtering method.
  • the composition of the oxide semiconductor film formed by sputtering depends on the composition of the sputtering target.
  • a sputtering target having the above-mentioned composition an oxide semiconductor film without composition deviation of metal elements can be formed by sputtering. Therefore, the composition of the metal elements (indium and other metal elements) of the oxide semiconductor film may be the same as the composition of the metal elements of the sputtering target.
  • the composition of the metal elements of the oxide semiconductor film can be specified based on the composition of the metal elements of the sputtering target. Note that this is not limited to the oxygen element contained in the oxide semiconductor film, as it changes depending on the process conditions of the sputtering.
  • the composition of the metal elements in the oxide semiconductor film can also be determined using X-ray fluorescence analysis or Electron Probe Micro Analyzer (EPMA) analysis. Furthermore, since the oxide semiconductor film has a polycrystalline structure, the composition of the oxide semiconductor film can be determined using X-ray diffraction (XRD) method. Specifically, the composition of the metal elements in the oxide semiconductor film can be determined based on the crystal structure and lattice constant of the oxide semiconductor film obtained by XRD method.
  • XRD X-ray diffraction
  • the oxide semiconductor film according to this embodiment has a polycrystalline structure including a plurality of crystal grains. Although details will be described later, by using a polycrystalline oxide semiconductor (Poly-OS) technique, an oxide semiconductor film having a novel polycrystalline structure different from a conventional one can be formed. Therefore, hereinafter, the oxide semiconductor film having a polycrystalline structure according to this embodiment may be referred to as a Poly-OS film in order to distinguish it from a conventional oxide semiconductor film having a polycrystalline structure.
  • Poly-OS polycrystalline oxide semiconductor
  • the crystal structure of the Poly-OS film is not particularly limited, but is preferably a bixbyite structure.
  • the crystal structure of the Poly-OS film can be identified using the XRD method or the electron beam diffraction method.
  • the crystal structure of the Poly-OS film is different from that of a conventional oxide semiconductor film having a polycrystalline structure.
  • the inventors found that, although the Poly-OS film has a polycrystalline structure, the polycrystalline structure of the Poly-OS film is different from that of a conventional oxide semiconductor film. That is, the inventors, as a result of various trials and errors, have completed an oxide semiconductor film (Poly-OS film) having a novel polycrystalline structure different from that of conventional oxide semiconductor films.
  • the crystallinity characteristics of the Poly-OS film can be obtained by using an XRD method.
  • out-of-plane measurement evaluates lattice planes parallel to the film surface
  • in-plane measurement evaluates lattice planes perpendicular to the film surface.
  • the characteristics of Poly-OS films can be obtained through out-of-plane measurement.
  • the (001) plane includes the (001) plane as well as the equivalent (100) plane and (010) plane.
  • the (101) plane includes the (101) plane as well as the equivalent (110) plane and (011) plane.
  • the (111) plane represents the (111) plane.
  • "1" may be "-1", and is considered to be an equivalent plane to each plane.
  • a peak appears at a certain diffraction angle (2 ⁇ ) in a diffraction pattern obtained by out-of-plane measurement.
  • a conventional crystalline oxide semiconductor film containing 50% or more indium and having a bixbite structure has peaks at diffraction angles of about 31° and about 44° in a diffraction pattern.
  • the peak at the diffraction angle of about 31° is attributed to the (222) plane of the bixbite structure.
  • the peak at the diffraction angle of about 44° is attributed to the (422) plane of the bixbite structure.
  • the peak intensity at the diffraction angle of about 31° is significantly greater than the peak intensity at the diffraction angle of about 44°. This means that many crystals having a (222) plane in a direction parallel to the surface of the oxide semiconductor film are present.
  • the diffraction angle of the diffraction pattern of the oxide semiconductor film may vary depending on the composition of the metal elements contained in the oxide semiconductor film or the manufacturing conditions of the oxide semiconductor film. Therefore, in this specification, the vicinity of the diffraction angle peak is considered to include a range of ⁇ 2°.
  • the diffraction pattern of a Poly-OS film having a bixbite structure also has a peak at a diffraction angle of about 31°, which corresponds to the (222) plane of the bixbite structure.
  • the peak intensity of the diffraction angle of the Poly-OS film at about 31° is smaller than the peak intensity of the diffraction angle of about 31° of a conventional crystalline oxide semiconductor film with the same film thickness.
  • the peak intensity of the diffraction angle of the Poly-OS film at about 31° is less than half the peak intensity of the diffraction angle of about 31° of a conventional crystalline oxide semiconductor film with the same film thickness.
  • a peak may appear at a diffraction angle of about 44° in the diffraction pattern of the Poly-OS film.
  • the ratio of the peak intensity at a diffraction angle of about 31° to the peak intensity at a diffraction angle of about 44° is 3.0 or less.
  • a peak may not appear at a diffraction angle of about 44°.
  • a peak may appear at a diffraction angle of about 52°, which corresponds to the (440) plane of the bixbyite structure.
  • the scanning speed of the goniometer is set to 1.0°/min or less, preferably 0.5°/min or less, to increase the intensity per diffraction angle.
  • the measurement width is, for example, 0.05° or more, but is not limited to this.
  • the above-mentioned ranges of the scanning speed and measurement width are examples of conditions for improving the S/N ratio, and are not limited to these ranges.
  • the S/N ratio is defined as the ratio of the maximum intensity (S) of the peak of the (222) plane to the noise width (N).
  • the maximum intensity (S) of the peak of the (222) plane is obtained from the diffraction pattern of the Poly-OS film from which background removal has been performed.
  • the noise width (N) is calculated by defining a baseline using linear approximation by the least squares method for the intensity data at diffraction angles of 29° to 30° in the diffraction pattern of the Poly-OS film before background subtraction, and doubling the standard deviation of the difference from the baseline (i.e., 2 ⁇ ).
  • FIG. 1 shows an example of a diffraction pattern of an oxide semiconductor film (Poly-OS film) according to one embodiment of the present invention, obtained by out-of-plane XRD measurement.
  • the measurement conditions are a goniometer scanning speed of 0.5°/min and a measurement width of 0.05°.
  • peaks of the (222) plane and the (440) plane can be observed near 31° and near 52°, respectively.
  • the calculated S/N ratio is 27.0, and the intensity of the peak of the (440) plane has sufficiently high reliability.
  • the Poly-OS film exhibits a characteristic diffraction pattern different from that of conventional crystalline oxide semiconductor films.
  • a peak of the (440) plane is more likely to appear than in conventional crystalline oxide semiconductor films. This means that the orientation of the (222) plane with respect to the surface of the Poly-OS film is relaxed, and the (440) plane is aligned in a direction parallel to the surface of the Poly-OS film.
  • the crystals contained in the Poly-OS film have a characteristic crystal arrangement different from that of conventional crystals.
  • One of the parameters indicating the characteristics of the crystallinity of such a Poly-OS film is the ratio of the peak intensity of the (222) plane to the peak intensity of the (440) plane (hereinafter referred to as "(222)/(440) peak intensity ratio").
  • the peak intensity of the (222) plane is large, and a peak of the (440) plane is hardly observed. Therefore, the (222)/(440) peak intensity ratio of a conventional crystalline oxide semiconductor film cannot be calculated or exceeds 500.
  • the (222)/(440) peak intensity ratio of a Poly-OS film is 300 or less.
  • a thin film transistor using the Poly-OS film as a channel has a (222)/(440) peak intensity ratio of 125 or less, a field-effect mobility of 30 cm 2 /Vs or more can be obtained.
  • the (222)/(440) peak intensity ratio of the Poly-OS film is preferably 50 or less, and more preferably 15 or less.
  • a field-effect mobility of 34 cm 2 /Vs or more can be obtained.
  • a field-effect mobility of 38 cm 2 /Vs or more can be obtained in some cases.
  • the lower limit is preferably 1 or more.
  • the (222)/(440) peak intensity ratio of the Poly-OS film is 1 or more, this means that the Poly-OS film has a cubic crystal structure and has both the (222) and (440) planes parallel to the film thickness direction (perpendicular to the film surface), and it can be determined that the long-range atomic order is maintained.
  • the crystal grains in the Poly-OS film may be composed of a plurality of crystallites.
  • the crystallite diameter D can be calculated by the Scherrer formula shown in Equation (5) using the peak width of the diffraction pattern.
  • K is the Scherrer constant
  • ⁇ is the wavelength of the X-ray
  • ⁇ is the half-width of the peak
  • ⁇ is the Bragg angle (corresponding to 1/2 of the diffraction angle 2 ⁇ ).
  • the crystallite diameter D of the crystal grains contained in the Poly-OS film can be calculated using the half-width of the peak corresponding to the (222) plane. In an out-of-plane diffraction pattern using Cu-K ⁇ radiation, it is preferable that the crystallite diameter D is approximately equal to the film thickness t of the Poly-OS.
  • the ratio (D/t) of the crystallite diameter D to the film thickness t of the Poly-OS film is 0.75 or more, preferably 0.85 or more, and more preferably 0.95 or more.
  • the film thickness t of the Poly-OS film is not particularly limited, but as the film thickness t becomes smaller, D/t becomes larger, and a Poly-OS film with a small (222)/(440) peak intensity ratio can be obtained.
  • the film thickness t of the Poly-OS film is, for example, 30 nm or less, preferably 20 nm or less, and more preferably 15 nm or less. In particular, when the film thickness is less than 20 nm, a Poly-OS film having a D/t of 0.95 or more is obtained. Note that when the film thickness of the Poly-OS film is small, a crystallite diameter D exceeding the film thickness t of the Poly-OS film may be obtained.
  • the crystallite diameter D is a value close to the film thickness t of the Poly-OS film, it means that the crystallite diameter D is approximately equal to the film thickness t of the Poly-OS film, and it can be determined that D/t is 0.95 or more.
  • the Poly-OS film As described above, in the Poly-OS film, the peak intensity of the (222) plane in the diffraction pattern is small. However, the crystallite diameter D of the Poly-OS film is almost equal to the film thickness t of the Poly-OS film. Therefore, the Poly-OS film has a novel crystal structure in which the crystal orientation is relaxed while the long-range atomic order is maintained in the film thickness direction (perpendicular to the film surface).
  • the oxide semiconductor film according to one embodiment of the present invention i.e., the Poly-OS film
  • the Poly-OS film has a novel crystal structure.
  • the field effect mobility is not reduced but is actually improved. Therefore, the electrical characteristics of a thin film transistor including a Poly-OS film are improved.
  • the thin film transistor 10 can be used in, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a memory circuit.
  • IC integrated circuit
  • MPU Micro-Processing Unit
  • FIG. 2 is a schematic cross-sectional view showing the configuration of a thin film transistor 10 according to an embodiment of the present invention.
  • Fig. 3 is a schematic plan view showing the configuration of a thin film transistor according to an embodiment of the present invention. Specifically, Fig. 2 is a cross-sectional view taken along line AA' in Fig. 3.
  • the thin film transistor 10 includes a substrate 100, a light-shielding layer 105, a first insulating layer 110, a second insulating layer 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a fourth insulating layer 180, a source electrode 201, and a drain electrode 203.
  • the light-shielding layer 105 is provided on the substrate 100.
  • the first insulating layer 110 covers the upper surface and end surfaces of the light-shielding layer 105 and is provided on the substrate 100.
  • the second insulating layer 120 is provided on the first insulating layer 110.
  • the metal oxide layer 130 is provided on the second insulating layer 120.
  • the oxide semiconductor layer 140 is provided on and in contact with the metal oxide layer 130.
  • the gate insulating layer 150 covers the end faces of the metal oxide layer 130 and the upper surface and end faces of the oxide semiconductor layer 140, and is provided on the second insulating layer 120.
  • the gate electrode 160 overlaps with the oxide semiconductor layer 140 and is provided on the gate insulating layer 150.
  • the third insulating layer 170 covers the upper surface and end faces of the gate electrode 160 and is provided on the gate insulating layer 150.
  • the fourth insulating layer 180 is provided on the third insulating layer 170.
  • the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 are provided with openings 171 and 173 through which a part of the upper surface of the oxide semiconductor layer 140 is exposed.
  • the source electrode 201 is provided on the fourth insulating layer 180 and inside the opening 171, and is in contact with the oxide semiconductor layer 140.
  • the drain electrode 203 is provided on the fourth insulating layer 180 and inside the opening 173, and is in contact with the oxide semiconductor layer 140.
  • the source-drain electrode 200 when there is no particular distinction between the source electrode 201 and the drain electrode 203, they may be collectively referred to as the source-drain electrode 200.
  • the oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH with respect to the gate electrode 160. That is, the oxide semiconductor layer 140 includes the channel region CH overlapping with the gate electrode 160, and the source region S and the drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160.
  • the channel region CH has a semiconductor property.
  • Each of the source region S and the drain region D has a conductor property. Therefore, the electrical conductivity of the source region S and the drain region D is greater than the electrical conductivity of the channel region CH.
  • the source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140.
  • the oxide semiconductor layer 140 may have a single-layer structure or a multilayer structure.
  • each of the light-shielding layer 105 and the gate electrode 160 has a constant width in the D1 direction and extends in the D2 direction perpendicular to the D1 direction.
  • the width of the light-shielding layer 105 is greater than the width of the gate electrode 160.
  • the channel region CH completely overlaps with the light-shielding layer 105.
  • the D1 direction corresponds to the direction in which a current flows from the source electrode 201 to the drain electrode 203 through the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.
  • the substrate 100 can support each layer constituting the thin film transistor 10.
  • a rigid substrate having light transmission properties such as a glass substrate, a quartz substrate, or a sapphire substrate
  • a rigid substrate having no light transmission properties such as a silicon substrate
  • a flexible substrate having light transmission properties such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, can also be used as the substrate.
  • impurities may be introduced into the above-mentioned resin substrate.
  • a substrate in which a silicon oxide film or a silicon nitride film is formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.
  • the light-shielding layer 105 can reflect or absorb external light. As described above, the light-shielding layer 105 is provided with an area larger than the channel region CH of the oxide semiconductor layer 140, and therefore can block external light incident on the channel region CH. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy or compound thereof, can be used as the light-shielding layer 105. In addition, if electrical conductivity is not required, the light-shielding layer 105 does not necessarily need to contain a metal. For example, a black matrix made of a black resin can be used as the light-shielding layer 105.
  • the light-shielding layer 105 may have a single-layer structure or a laminated structure.
  • the light-shielding layer 105 may have a laminated structure of a red color filter, a green color filter, and a blue color filter.
  • the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can prevent impurities from diffusing into the oxide semiconductor layer 140.
  • the first insulating layer 110 and the second insulating layer 120 can prevent the diffusion of impurities contained in the substrate 100
  • the third insulating layer 170 and the fourth insulating layer 180 can prevent the diffusion of impurities (e.g., water) entering from the outside.
  • silicon oxynitride (SiO x N y ) and aluminum oxynitride (AlO x N y ) are silicon compounds and aluminum compounds, respectively, containing nitrogen (N) at a ratio (x>y) smaller than that of oxygen (O).
  • Silicon nitride oxide ( SiNxOy ) and aluminum nitride oxide ( AlNxOy ) are silicon compounds and aluminum compounds that contain a smaller ratio of oxygen than nitrogen (x> y ).
  • the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may each have a single-layer structure or a multilayer structure.
  • the gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive.
  • copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof can be used for each of the gate electrode 160, the source electrode 201, and the drain electrode 203.
  • Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a multilayer structure.
  • the gate insulating layer 150 includes an oxide having insulating properties. Specifically, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), or the like is used as the gate insulating layer 150.
  • the gate insulating layer 150 preferably has a composition close to a stoichiometric ratio.
  • the gate insulating layer 150 preferably has few defects.
  • the gate insulating layer 150 may be made of an oxide in which no defects are observed when evaluated by electron spin resonance (ESR).
  • the metal oxide layer 130 includes a metal oxide having insulating properties. Specifically, a metal oxide having a band gap of 4 eV or more is used as the metal oxide layer 130.
  • a metal oxide containing one or more metal elements selected from aluminum (Al), magnesium (Mg), calcium (Ca), scandium (Sc), gallium (Ga), germanium (Ge), strontium (Sr), nickel (Ni), tantalum (Ta), yttrium (Y), zirconium (Zr), barium (Ba), hafnium (Hf), cobalt (Co), and lanthanoid elements is used.
  • a metal oxide containing aluminum e.g., aluminum oxide, etc.
  • a metal oxide containing aluminum has high barrier properties against gases such as oxygen or hydrogen.
  • the metal oxide layer 130 can also function as a buffer layer for the oxide semiconductor layer 140. For example, by subjecting the oxide semiconductor layer 140 in contact with the metal oxide layer 130 to a heat treatment, the crystallinity of the oxide semiconductor layer 140 can be improved.
  • the thickness of the metal oxide layer 130 is not particularly limited.
  • the thickness of the metal oxide layer 130 may be 20 nm or less, 15 nm or less, or 10 nm or less.
  • the thickness of the metal oxide layer 130 is 2 nm or more and 20 nm or less, preferably 2 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less.
  • the Poly-OS film described in the first embodiment can be used as the oxide semiconductor layer 140.
  • the configuration of the thin film transistor 10 has been described above, but the above-mentioned thin film transistor 10 is a so-called top-gate type transistor.
  • the thin film transistor 10 can be modified in various ways.
  • the thin film transistor 10 may be configured such that the light-shielding layer 105 functions as a gate electrode, and the first insulating layer 110 and the second insulating layer 120 function as gate insulating layers.
  • the thin film transistor 10 is a so-called dual-gate type transistor.
  • the light-shielding layer 105 when the light-shielding layer 105 is conductive, the light-shielding layer 105 may be a floating electrode or may be connected to the source electrode 201.
  • the thin film transistor 10 may be a so-called bottom-gate type transistor in which the light-shielding layer 105 functions as a main gate electrode.
  • FIG. 4 is a flowchart showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention.
  • Figs. 5 to 12 are schematic cross-sectional views showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention.
  • the method for manufacturing the thin-film transistor 10 includes steps S1010 to S1110. Below, steps S1010 to S1110 will be described in order, but the order of the steps may be reversed in the method for manufacturing the thin-film transistor 10. In addition, the method for manufacturing the thin-film transistor 10 may include additional steps.
  • a light-shielding layer 105 having a predetermined pattern is formed on the substrate 100.
  • the light-shielding layer 105 is patterned using a photolithography method.
  • a first insulating layer 110 and a second insulating layer 120 are formed on the light-shielding layer 105 (see FIG. 5).
  • the first insulating layer 110 and the second insulating layer 120 are formed using a CVD method.
  • silicon nitride and silicon oxide are formed as the first insulating layer 110 and the second insulating layer 120, respectively.
  • silicon nitride is used as the first insulating layer 110
  • the first insulating layer 110 can block impurities that are diffused from the substrate 100 side to the oxide semiconductor layer 140.
  • silicon oxide is used as the second insulating layer 120, the second insulating layer 120 can release oxygen by heat treatment.
  • a metal oxide film 135 is formed on the second insulating layer 120 (see FIG. 6).
  • the metal oxide film 135 is formed by a sputtering method.
  • the thickness of the metal oxide film 135 is 2 nm or more and 20 nm or less, preferably 2 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less.
  • an oxide semiconductor film 145 is formed on the metal oxide film 135 (see FIG. 6).
  • the oxide semiconductor film 145 is formed by a sputtering method.
  • the thickness of the oxide semiconductor film 145 is, for example, 10 nm or more and 100 nm or less, preferably 15 nm or more and 70 nm or less, and more preferably 15 nm or more and 40 nm or less.
  • the oxide semiconductor film 145 in step S1020 is amorphous.
  • the oxide semiconductor film 145 is amorphous after film formation and before heat treatment. Therefore, the film formation conditions of the oxide semiconductor film 145 are preferably such that the oxide semiconductor layer 140 immediately after film formation is not crystallized as much as possible.
  • the oxide semiconductor film 145 is formed by a sputtering method, the oxide semiconductor film 145 is formed while controlling the temperature of the film formation target (the substrate 100 and the layer formed on the substrate 100) to 100° C. or less, preferably 80° C. or less, and more preferably 50° C. or less.
  • the oxide semiconductor film 145 is formed under a condition of low oxygen partial pressure.
  • the oxygen partial pressure is 2% or more and 20% or less, preferably 3% or more and 15% or less, and more preferably 3% or more and less than 10%.
  • the oxide semiconductor film 145 is patterned (see FIG. 7).
  • the oxide semiconductor film 145 is patterned using a photolithography method.
  • the oxide semiconductor film 145 may be etched by wet etching or dry etching. In wet etching, an acidic etchant may be used. Examples of the etchant that may be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide, and hydrofluoric acid.
  • step S1040 a heat treatment is performed on the oxide semiconductor film 145.
  • the heat treatment performed in step S1040 is referred to as "OS annealing".
  • OS annealing the oxide semiconductor film 145 is held at a predetermined temperature for a predetermined time.
  • the predetermined temperature is 300° C. or higher and 500° C. or lower, and preferably 350° C. or higher and 450° C. or lower.
  • the predetermined time (holding time) at the temperature is 15 minutes or higher and 120 minutes or lower, and preferably 30 minutes or higher and 60 minutes or lower.
  • the OS annealing crystallizes the oxide semiconductor film 145, and an oxide semiconductor layer 140 having a polycrystalline structure (i.e., an oxide semiconductor layer 140 including a Poly-OS film) is formed.
  • the metal oxide film 135 is patterned to form the metal oxide layer 130 (FIG. 8).
  • the metal oxide film 135 is etched using the oxide semiconductor layer 140 as a mask.
  • the photolithography process can be omitted.
  • the metal oxide film 135 may be etched by wet etching or dry etching. For example, diluted hydrofluoric acid (DHF) is used in wet etching.
  • DHF diluted hydrofluoric acid
  • the gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see FIG. 9).
  • the gate insulating layer 150 is formed using a CVD method.
  • silicon oxide is formed as the gate insulating layer 150.
  • the gate insulating layer 150 may be formed at a film formation temperature of 350° C. or higher.
  • the thickness of the gate insulating layer 150 is 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm.
  • a process of introducing oxygen into a part of the gate insulating layer 150 may be performed.
  • step S1060 a heat treatment is performed on the oxide semiconductor layer 140.
  • the heat treatment performed in step S1060 is referred to as "oxidation annealing.”
  • oxidation annealing When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen defects are generated on the upper and side surfaces of the oxide semiconductor layer 140.
  • oxygen is supplied from the second insulating layer 120 and the gate insulating layer 150 to the oxide semiconductor layer 140, and the oxygen defects are repaired.
  • a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see FIG. 10).
  • the gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned by photolithography.
  • a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see FIG. 10).
  • the source region S and the drain region D are formed by ion implantation.
  • impurities are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150 using the gate electrode 160 as a mask.
  • argon (Ar), phosphorus (P), or boron (B) is used as the implanted impurity.
  • oxygen vacancies are generated by the ion implantation, and hydrogen is trapped in the generated oxygen vacancies. This reduces the resistance of the source region S and the drain region D.
  • impurities are not implanted, so no oxygen vacancies are generated and the resistance of the channel region CH does not decrease.
  • the gate insulating layer 150 may also contain impurities such as argon (Ar), phosphorus (P), or boron (B).
  • a third insulating layer 170 and a fourth insulating layer 180 are formed on the gate insulating layer 150 and the gate electrode 160 (see FIG. 11).
  • the third insulating layer 170 and the fourth insulating layer 180 are formed using a CVD method.
  • silicon oxide and silicon nitride are formed as the third insulating layer 170 and the fourth insulating layer 180, respectively.
  • the thickness of the third insulating layer 170 is 50 nm or more and 500 nm or less.
  • the thickness of the fourth insulating layer 180 is also 50 nm or more and 500 nm or less.
  • openings 171 and 173 are formed in the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 (see FIG. 12). By forming the openings 171 and 173, the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.
  • a source electrode 201 is formed on the fourth insulating layer 180 and inside the opening 171
  • a drain electrode 203 is formed on the fourth insulating layer 180 and inside the opening 173.
  • the source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning a single conductive film that has been deposited. Through these steps, the thin-film transistor 10 shown in FIG. 1 is manufactured.
  • the oxide semiconductor layer 140 includes a Poly-OS film having a novel crystal structure. That is, the Poly-OS film is used as the semiconductor material of the thin film transistor 10. As will be described in detail later, the thin film transistor 10 including the Poly-OS film having such a novel crystal structure has improved electrical characteristics. For example, the field effect mobility of the thin film transistor 10 is improved. Note that the semiconductor material including the Poly-OS film can also be used in electronic devices other than thin film transistors.
  • FIG. 13 is a schematic diagram showing an electronic device 1000 according to one embodiment of the present invention.
  • FIG. 13 shows a smartphone, which is an example of the electronic device 1000.
  • the electronic device 1000 includes a display device 1100 with curved sides.
  • the display device 1100 includes a plurality of pixels for displaying an image, and the plurality of pixels are controlled by a pixel circuit, a drive circuit, and the like.
  • the pixel circuit and drive circuit include the thin-film transistor 10 described in the second embodiment.
  • the thin-film transistor 10 has high field-effect mobility, and therefore improves the responsiveness of the pixel circuit and the drive circuit, and as a result, the performance of the electronic device 1000 can be improved.
  • the electronic device 1000 is not limited to a smartphone.
  • the electronic device 1000 also includes electronic devices having a display device, such as a watch, a tablet, a notebook computer, a car navigation system, or a television.
  • the thin-film transistor 10 described in the first embodiment can be applied to any electronic device, regardless of whether or not it has a display device.
  • the oxide semiconductor films in the thin film samples or thin film transistors were manufactured by a sputtering process and an OS annealing process.
  • a sputtering target in which indium was 70% in terms of atomic ratio to all metal elements contained in the sintered body was used.
  • the chemical composition of the oxide semiconductor film after the OS annealing process was similar to that of the sputtering target.
  • the temperature reached was controlled to be between 350° C. and 450° C.
  • Example 1 [1-1-1. Thin film samples] A laminated film of a silicon oxide film (SiO x ) and an aluminum oxide film (AlO x ) was formed as an undercoat film on a glass substrate.
  • the silicon oxide film was formed on the glass substrate by a plasma CVD method using monosilane (SiH 4 ) gas and dinitrogen monoxide (N 2 O) gas.
  • the aluminum oxide film was formed on the silicon oxide film by a sputtering method using an aluminum (Al) target.
  • An oxide semiconductor film was formed to a thickness of 15 nm by a sputtering process on a glass substrate on which an undercoat film (AlO x /SiO x ) was formed.
  • the oxide semiconductor film was formed under conditions in which the oxygen partial pressure was 3% (Example 1-1) or 5% (Example 1-2). Thereafter, the formed oxide semiconductor film was subjected to an OS annealing process in an air atmosphere.
  • a thin film transistor was fabricated by applying the conditions of Example 1-1 or Example 1-2 in the manufacturing method described in the second embodiment.
  • Examples 1-1-1 to 1-1-9 were fabricated under the conditions of Example 1-1, and two samples (Examples 1-2-1 and 1-2-2) were fabricated under the conditions of Example 1-2.
  • Example 2 [1-2-1. Thin film samples] An oxide semiconductor film was formed to a thickness of 20 nm by a sputtering process on a glass substrate on which an undercoat film (AlO x /SiO x ) was formed. The oxide semiconductor film was formed under conditions in which the oxygen partial pressure was 3% (Example 2-1) or 5% (Example 2-2). Thereafter, the formed oxide semiconductor film was subjected to an OS annealing process in an air atmosphere.
  • AlO x /SiO x undercoat film
  • Example 2-1 the conditions of Example 2-1 or Example 2-2 were applied to fabricate a thin film transistor.
  • Example Sample 2-1-1 and Example Sample 2-1-2 were prepared under the conditions of Example 2-1, and two samples (Example Sample 2-2-1 and Example Sample 2-2-2) were prepared under the conditions of Example 2-2.
  • Example 3 [1-3-1. Thin film samples] An oxide semiconductor film was formed to a thickness of 25 nm by a sputtering process on a glass substrate on which an undercoat film (AlO x /SiO x ) was formed. The oxide semiconductor film was formed under conditions in which the oxygen partial pressure was 3% (Example 3-1) or 4% (Example 3-2). Thereafter, the formed oxide semiconductor film was subjected to an OS annealing process in an air atmosphere.
  • AlO x /SiO x undercoat film
  • a thin film transistor was fabricated by applying the conditions of Example 3-1 or Example 3-2 in the manufacturing method described in the second embodiment.
  • Example Sample 3-1-1 and Example Sample 3-1-2 were prepared under the conditions of Example 3-1, and two samples (Example Sample 3-2-1 and Example Sample 2-2-2) were prepared under the conditions of Example 3-2.
  • Example 4 [1-4-1. Thin film samples] An oxide semiconductor film was formed to a thickness of 30 nm by a sputtering process on a glass substrate on which an undercoat film (AlO x /SiO x ) was formed. The oxide semiconductor film was formed under conditions in which the oxygen partial pressure was 3% (Example 4-1) or 4% (Example 4-2). Thereafter, the formed oxide semiconductor film was subjected to an OS annealing process in an air atmosphere.
  • a thin film transistor was fabricated by applying the conditions of Example 4-1 or Example 4-2 in the manufacturing method described in the second embodiment.
  • Example Sample 4-1-1 and Example Sample 4-1-2 For each of the thin film specimen and thin film transistor, two samples (Example Sample 4-1-1 and Example Sample 4-1-2) were prepared under the conditions of Example 4-1, and two samples (Example Sample 4-2-1 and Example Sample 4-2-2) were prepared under the conditions of Example 4-2.
  • a thin film transistor without a metal oxide layer was fabricated using the manufacturing method described in the second embodiment. That is, the oxide semiconductor layer in the thin film transistor of the comparative example was formed on and in contact with the second insulating layer (SiO x ).
  • Crystal structure analysis by XRD method The crystal structure of the oxide semiconductor film of the thin film sample was analyzed by XRD. The crystal structure analysis by XRD was performed using a SmartLab device (manufactured by Rigaku Corporation) under the conditions shown in Table 2 that can improve the S/N ratio.
  • the (222)/(440) peak intensity ratio of the oxide semiconductor film was calculated from the diffraction pattern of the thin film sample, and the field effect mobility was calculated from the electrical characteristics of the thin film transistor.
  • Table 3 shows the (222)/(440) peak intensity ratio and field effect mobility for each sample.
  • Figure 14 shows a graph plotting the field effect mobility against the (222)/(440) peak intensity ratio.
  • the field-effect mobility of the thin film transistor exceeded 30 cm 2 /Vs.
  • All of the samples were Poly-OS films, and it was found that the field-effect mobility was improved by controlling the crystallinity of the Poly-OS film (more specifically, the (222)/(440) peak intensity ratio).
  • the field-effect mobility of the thin film transistor exceeded 34 cm 2 /Vs.
  • the thin film transistors of Examples 1-1-1 to 1-1-9 which had a (222)/(440) peak intensity ratio of 15 or less, had a field-effect mobility of 38 cm 2 /Vs or more.
  • the (222)/(440) peak intensity ratio of the Poly-OS film varies depending on the underlayer.
  • the (222)/(440) peak intensity ratio of the Poly-OS film decreases.
  • the (222)/(440) peak intensity ratio of the Poly-OS film can be controlled by the film thickness of the Poly-OS film and the oxygen partial pressure during film formation.
  • the film thickness of the Poly-OS film is small or the oxygen partial pressure during film formation is reduced, the (222)/(440) peak intensity ratio of the Poly-OS film decreases. In this way, the electrical characteristics of a thin film transistor can be improved by controlling the (222)/(440) peak intensity ratio of the Poly-OS film.

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