WO2024148796A1 - 一种反熔丝阵列和半导体结构 - Google Patents

一种反熔丝阵列和半导体结构 Download PDF

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Publication number
WO2024148796A1
WO2024148796A1 PCT/CN2023/110842 CN2023110842W WO2024148796A1 WO 2024148796 A1 WO2024148796 A1 WO 2024148796A1 CN 2023110842 W CN2023110842 W CN 2023110842W WO 2024148796 A1 WO2024148796 A1 WO 2024148796A1
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Prior art keywords
programming
wire
gate
conductive
selection device
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PCT/CN2023/110842
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English (en)
French (fr)
Inventor
侯闯明
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Definitions

  • the present disclosure relates to, but is not limited to, an antifuse array and a semiconductor structure.
  • Anti-fuse is a one-time programmable device (OTP) widely used in memories such as dynamic random access memory (DRAM).
  • Anti-fuse devices are semiconductor devices composed of two conductive layers and a dielectric layer (such as a gate oxide layer) between the conductive layers. When not programmed, the two conductive layers are separated by the dielectric layer, and the anti-fuse is open; when programmed, a high voltage is applied to break down the dielectric layer, so that an electrical connection is formed between the two conductive layers, which is also called the anti-fuse device being blown.
  • the unblown and blown states of the anti-fuse device can represent the logical value "0" and the logical value "1" respectively.
  • the related programming wires may be blown, which may cause the failure of other anti-fuse devices in the same row.
  • Embodiments of the present disclosure provide an antifuse array and a semiconductor structure.
  • an embodiment of the present disclosure provides an anti-fuse array, the anti-fuse array comprising:
  • bit lines A plurality of bit lines, the bit lines extending along a second direction, the second ends of the first selection devices in the same column are all connected to the same bit line;
  • a plurality of first word lines wherein the first word lines extend along a first direction, and control terminals of the first selection devices in the same row are all connected to the same first word line;
  • a plurality of first programming wires wherein the first programming wires extend along the first direction, and control terminals of the first programming devices in the same row are all connected to the same first programming wire;
  • the first programming wire has a first auxiliary structure, and when a voltage is applied to the first programming wire, current flows through a first path formed by the first programming wire and the first auxiliary structure, and a cross-sectional area of the first path on a plane perpendicular to the first direction is greater than a cross-sectional area of the first programming wire on a plane perpendicular to the first direction; wherein the first direction and the second direction are perpendicular to each other.
  • the antifuse array further comprises:
  • a plurality of second anti-fuse units are distributed in an array, wherein the second anti-fuse units include a second selection device and a second programming device, wherein a first end of the second selection device is connected to a first end of the second programming device; the first selection device, the first programming device, the second programming device and the second selection device are sequentially arranged in a cycle along the second direction, and a second end of the second selection device and a second end of the first selection device in the same column are both connected to the same bit line;
  • a plurality of second programming wires wherein the second programming wires extend along the first direction, and control terminals of the second programming devices in the same row are all connected to the same second programming wire;
  • the second programming wire has a second auxiliary structure, and when a voltage is applied to the second programming wire, current flows through a second path formed by the second programming wire and the second auxiliary structure, and a cross-sectional area of the second path on a plane perpendicular to the first direction is greater than a cross-sectional area of the second programming wire on a plane perpendicular to the first direction.
  • the first word line is adjacent to the second word line
  • the first programming conductive line is adjacent to the second programming conductive line
  • the first auxiliary structure refers to the second programming wire adjacent to the first programming wire
  • the second auxiliary structure refers to the first programming wire adjacent to the second programming wire
  • the first auxiliary structure specifically includes a connecting structure and an adjacent second programming wire
  • the second auxiliary structure specifically includes the connecting structure and an adjacent first programming wire
  • the connecting structure connects the adjacent first programming wire and the second programming wire, and the first path and the second path overlap; wherein the connecting structure, the first programming wire and the second programming wire are located in the same horizontal plane, and the connecting structure is located in the area between the adjacent first programming wire and the second programming wire.
  • the first programming conductor, the adjacent second programming conductor, and the connection structure therebetween are combined to form an integral conductor; wherein the integral conductor receives a programming control signal; and the first anti-fuse unit and the adjacent second anti-fuse unit share the programming control signal.
  • the first programming conductor, the adjacent second programming conductor, and the connection structure therebetween are independently configured; the first programming conductor receives a first programming control signal of the first anti-fuse unit, and the second programming conductor receives a second programming control signal of the second anti-fuse unit.
  • the first anti-fuse unit also includes a first conductive wire
  • the second anti-fuse unit also includes a second conductive wire; there is an electrical path between the first conductive wire and the first programming wire, and there is an electrical path between the second conductive wire and the second programming wire; the first auxiliary structure is the first conductive wire, and the second auxiliary structure is the second conductive wire.
  • the first auxiliary structure specifically includes a first connection structure and the first conductive line; the first connection structure connects the first programming wire and the first conductive line; the second auxiliary structure specifically includes a second connection structure and the second conductive line; the second connection structure connects the second programming wire and the second conductive line; the first path and the second path do not overlap;
  • the first programming wire and the first conductive wire are located on different horizontal planes, and the first connecting structure passes through the horizontal plane between the first programming wire and the first conductive wire; the second programming wire and the second conductive wire are located on different horizontal planes, and the second connecting structure passes through the horizontal plane between the second programming wire and the second conductive wire.
  • the first conductive wire directly covers the surface of the first programming wire along a third direction, and the first conductive wire and the first connecting structure are combined into a whole; the second conductive wire directly covers the surface of the second programming wire along the third direction, and the second conductive wire and the second connecting structure are combined into a whole.
  • first conductive wire and the first programming wire there is no direct contact between the first conductive wire and the first programming wire, and the first conductive wire, the first connecting structure and the first programming wire are all independently set; there is no direct contact between the second conductive wire and the second programming wire, and the second conductive wire, the second connecting structure and the second programming wire are all independently set.
  • the melting point of the first conductive wire is greater than the melting point of the first programming wire, and the melting point of the second conductive wire is greater than the melting point of the second programming wire; wherein the material of the first conductive wire at least includes metal tungsten, and the material of the second conductive wire at least includes metal tungsten.
  • the first anti-fuse unit and the adjacent second anti-fuse unit share an active region
  • the first anti-fuse unit further includes a first gate and a second gate
  • the second anti-fuse unit further includes a third gate and a fourth gate
  • the first gate, the second gate, the third gate and the fourth gate are all located in the active area, and the first gate, the second gate, the third gate and the fourth gate are arranged along the second direction;
  • the first gate and the active area form the first programming device
  • the second gate and the active area form the first selection device
  • the third gate and the active area form the second selection device
  • the fourth gate and the active area form the second programming device.
  • the first gate forms a control terminal of the first programming device
  • the second gate forms a control terminal of the first selection device
  • the third gate forms a control terminal of the second selection device
  • the fourth gate forms a control terminal of the second programming device
  • the active area located between the first gate and the second gate is used to form a first end of the first programming device and a first end of the first selection device
  • the active area located between the second gate and the third gate is used to form a second end of the first selection device and a second end of the second selection device
  • the active area located between the third gate and the fourth gate is used to form a first end of the second selection device and a first end of the second programming device.
  • an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes an antifuse array as described in the first aspect.
  • FIG1 is a schematic diagram of the structure of an antifuse array
  • FIG2 is a schematic diagram of a fusing of a programming wire
  • FIG3 is a schematic diagram of a partial structure of an antifuse array provided in an embodiment of the present disclosure.
  • FIG4 is a second schematic diagram of a partial structure of an antifuse array provided in an embodiment of the present disclosure.
  • FIG5A is a third schematic diagram of a partial structure of an antifuse array provided in an embodiment of the present disclosure.
  • FIG5B is a fourth schematic diagram of a partial structure of an antifuse array provided in an embodiment of the present disclosure.
  • FIG6 is a fifth schematic diagram of a partial structure of an antifuse array provided in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of the overall structure of an antifuse array provided by an embodiment of the present disclosure.
  • FIG8A is a sixth schematic diagram of a partial structure of an antifuse array provided in an embodiment of the present disclosure.
  • FIG8B is a seventh schematic diagram of a partial structure of an antifuse array provided in an embodiment of the present disclosure.
  • FIG8C is a partial structural schematic diagram 8 of an antifuse array provided in an embodiment of the present disclosure.
  • FIG9 is a ninth schematic diagram of a partial structure of an antifuse array provided in an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of the overall structure of another antifuse array provided in an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure.
  • first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when a second element, component, region, layer, or part is discussed, it does not mean that the present disclosure necessarily has a first element, component, region, layer, or part. element, component, region, layer or section.
  • FIG1 shows a schematic diagram of the structure of an anti-fuse array.
  • every two anti-fuse units (as shown in the dotted box) share an active area
  • the anti-fuse units in the same column are connected to the same bit line BL
  • the anti-fuse units in the same row share the same word line XG and the same programming wire FG.
  • the first anti-fuse unit corresponds to the word line Top XG and the programming wire Top FG
  • the second anti-fuse unit corresponds to the word line Bottom XG and the programming wire Bottom FG.
  • the active region and the first gate (not shown in FIG.
  • Topic AF cell programming device
  • the first gate is connected to Top FG
  • the active region and the second gate (not shown in FIG. 1 ) form a selection device (Top XADD) in the first anti-fuse cell
  • the second gate is connected to Top XG
  • the active region and the third gate (not shown in FIG.
  • FIG. 1 shows an arrangement of a greater number of anti-fuse cells. As shown in FIG. 1 and FIG. 2 , every two programming wires are adjacent, and every two word lines are adjacent.
  • the embodiments of the present disclosure provide an anti-fuse array, which can reduce the current density of the programming wire during the process of the gate oxide of the programming device being broken down, avoid the programming wire from fusing, and improve the failure problem of the programming device.
  • FIG3 a partial structural diagram of an antifuse array 10 provided in an embodiment of the present disclosure is shown.
  • the antifuse array 10 includes:
  • a plurality of first anti-fuse units 11 are arranged in an array (only one is shown in FIG. 3 as an example), and the first anti-fuse unit 11 includes a first selection device 111 and a first programming device 112.
  • the first selection device 111 The first end of is connected to the first end of the first programming device 112;
  • bit lines BL extend along the second direction, and the second ends of the first selection devices 111 in the same column are all connected to the same bit line;
  • a plurality of first word lines XG1 (only one is shown as an example in FIG. 3 ), the first word lines XG1 extend along a first direction, and the control terminals of the first selection devices 111 in the same row are all connected to the same first word line XG1;
  • first programming wires FG1 (only one is shown as an example in FIG3 ), the first programming wire FG1 extends along a first direction, and the control ends of the first programming devices 112 located in the same row are all connected to the same first programming wire FG1; the first programming wire FG1 has a first auxiliary structure 12, and when a voltage is applied to the first programming wire FG1, current flows through a first path formed by the first programming wire FG1 and the first auxiliary structure 12, and a cross-sectional area of the first path on a plane perpendicular to the first direction (hereinafter referred to as the cross-sectional area) is greater than a cross-sectional area of the first programming wire FG1 on a plane perpendicular to the first direction (hereinafter referred to as the cross-sectional area); wherein the first direction and the second direction are perpendicular to each other.
  • the cross-sectional area a cross-sectional area of the first path on a plane perpendicular to the first direction
  • the active region 100 is located in a semiconductor substrate, which may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (G
  • the doping type of the active region 100 directly below the first word line XG1 is different from the doping type of the active region 100 located on both sides of the first word line XG1, thereby forming a first selection device 111; the doping type of the active region 100 directly below the first programming wire FG1 is different from the doping type of the active region 100 located on one side of the first programming wire FG1, thereby forming a first programming device 112.
  • the first selection device 111 can be turned on by applying a voltage to the first word line XG1, and then a strong voltage of 5 to 6 volts is applied to the first programming wire FG1, and at the same time, the bit line BL is set to 0 volts, so that the first programming device 112 can be broken down to achieve the writing of logic 1.
  • the first programming wire FG1 has a first auxiliary structure 12.
  • the current flows through the first path (composed of the first programming wire FG1 and the first auxiliary structure 12), and the cross-sectional area of the first path is greater than the cross-sectional area of the first programming wire FG1.
  • the current density on the first programming wire FG1 is reduced, the Joule heat is reduced, and the temperature rise is reduced, so that the first programming wire FG1 is prevented from fusing, and the failure problem of the anti-fuse array can be improved.
  • the row direction refers to the first direction
  • the column direction refers to the second direction
  • the first direction and the second direction may not be perpendicular, for example, the angle between the first direction and the second direction may be 80 degrees, 60 degrees, etc., in which case the cross-sectional area of the first path is still greater than the cross-sectional area of the first programming wire.
  • the cross-sectional area of the first path refers to the cross-sectional area perpendicular to the extension direction of the first path
  • the cross-sectional area of the first programming wire FG1 refers to the cross-sectional area perpendicular to the extension direction of the first programming wire FG1.
  • FIG4 a partial structural diagram of another antifuse array 10 provided in an embodiment of the present disclosure is shown. As shown in FIG4 , the antifuse array 10 further includes:
  • a plurality of second anti-fuse units 21 are distributed in an array, the second anti-fuse units 21 include a second selection device 211 and a second programming device 212, the first end of the second selection device 211 is connected to the first end of the second programming device 212; the first selection device 111, the first programming device 112, the second programming device 212 and the second selection device 211 are sequentially arranged in a cycle along a second direction, and the second end of the second selection device 211 and the second end of the first selection device 111 located in the same column are both connected to the same bit line;
  • a plurality of second word lines XG2, the second word lines XG2 extending along the first direction, the control terminals of the second selection devices 211 in the same row are all connected to the same second word line XG2;
  • a plurality of second programming wires FG2 extend along a first direction, and control ends of second programming devices 212 located in the same row are all connected to the same second programming wire FG2; the second programming wire FG2 has a second auxiliary structure 22, and when a voltage is applied to the second programming wire FG2, current flows through a second path formed by the second programming wire FG2 and the second auxiliary structure 22, and a cross-sectional area of the second path on a plane perpendicular to the first direction is greater than a cross-sectional area of the second programming wire FG2 on a plane perpendicular to the first direction.
  • first anti-fuse units 11 are located in the same row, and multiple second anti-fuse units 21 are located in the same row; in the second direction, a first anti-fuse unit 11 and a second anti-fuse unit 21 are mirror-symmetrical, thereby constituting a repeating unit of the anti-fuse array 10. In this way, the arrangement of the anti-fuse array is more regular, which is conducive to process manufacturing.
  • first anti-fuse unit 11 and the second anti-fuse unit 21 can form a column along other directions (for example, the angle with the current second direction is 30 degrees, 45 degrees or 60 degrees, etc.), and multiple first anti-fuse units 11 can also form a row along other directions (for example, the angle with the current first direction is 30 degrees, 45 degrees or 60 degrees, etc.), so as to improve the integration density of the anti-fuse array.
  • the second programming wire FG2 has a second auxiliary structure 22.
  • the current flows through the second path (composed of the second programming wire FG2 and the first auxiliary structure 12), and the cross-sectional area of the second path is greater than the cross-sectional area of the second programming wire FG2.
  • the current density on the second programming wire FG2 is reduced, the Joule heat is reduced, and the temperature rise is reduced, so that the second programming wire FG2 is prevented from being blown, and the failure problem is improved.
  • the programming wire FG (or programming wire) is directly used in the following text, it may refer to any one of the first programming wire FG1 and the second programming wire FG2; there is also no essential difference between the first word line XG1 and the second word line XG2.
  • the first programming conductive line FG1 and the second programming conductive line FG2 are adjacent to each other, and the first word line XG1 and the second word line XG2 are adjacent to each other.
  • FIG. 4 is arranged cyclically in the second direction, so the first word line XG1 in FIG. 4 is actually adjacent to another second word line XG2 (not shown in FIG. 4 ), and the second word line XG2 in FIG. 4 is actually adjacent to another first word line XG1 (not shown in FIG. 4 ).
  • first auxiliary structure 12 and the second auxiliary structure 22 are all possible, and the materials (or positions, processes and forms) of the first auxiliary structure 12 and the second auxiliary structure 22 can be the same or different. system.
  • the first auxiliary structure 12 refers to the second programming wire FG2 adjacent to the first programming wire FG1; and the second auxiliary structure 22 refers to the first programming wire FG1 adjacent to the second programming wire FG2.
  • one programming wire serves as an auxiliary structure of the other programming wire, and no additional physical structure is required, thereby reducing costs.
  • the current actually flows through the electrical path formed by the programming wire and the adjacent programming wire, reducing the current density and Joule heat, thereby avoiding failure of the programming wire.
  • the first auxiliary structure specifically includes a connecting structure 120 and an adjacent second programming wire FG2
  • the second auxiliary structure specifically includes the connecting structure 120 and an adjacent first programming wire FG1.
  • the connecting structure 120 connects the adjacent first programming wire FG1 and the second programming wire FG2, and the first path and the second path overlap.
  • the first programming wire FG1, the adjacent second programming wire FG2 and the connection structure therebetween are independently set; the first programming wire FG1 receives the first programming control signal of the first anti-fuse unit 11, and the second programming wire FG2 receives the second programming control signal of the second anti-fuse unit 21.
  • first programming wire FG1 and the second programming wire FG2 are physically independently arranged, but can be regarded as an integral electrical structure.
  • connection structure 120 may be various, that is, the connection structure 120 at least includes a conductive material, and the conductive material may be one or more of the following: tungsten, copper, cobalt, ruthenium, rhodium, etc.
  • connection structure 120 there are many possibilities for the location of the connection structure 120.
  • the connection structure 120, the first programming wire FG1 and the second programming wire FG2 are located in the same horizontal plane, and the connection structure 120 is located in the area between the adjacent first programming wire FG1 and the second programming wire FG2;
  • the connection structure 120, the first programming wire FG1 and the second programming wire FG2 are located in the same horizontal plane, and the connection structure 120 covers a portion of the surface of the first programming wire FG1, the area between the first programming wire FG1 and the second programming wire FG2, and a portion of the surface of the second programming wire FG2;
  • the connection structure may cross other planes along a third direction, for example, using a principle similar to a jumper to achieve the connection between the first programming wire FG1 and the second programming wire FG2.
  • the horizontal plane refers to the plane where the first direction and the second direction are located.
  • connection structure 120 is possible in many ways.
  • the connection structure 120 is rectangular and laid flat between the first programming wire FG1 and the second programming wire FG2; for another example, the connection structure 120 is circular and laid flat between the first programming wire FG1 and the second programming wire FG2; the other side of the connection structure 120 at least covers a portion of the second programming wire FG2; for another example, as shown in FIG5B , the connection structure 120 includes a plurality of substructures, each of which forms an electrical path between the first programming wire FG1 and the second programming wire FG2.
  • the first programming wire FG1, the adjacent second programming wire FG2, and the connection structure therebetween are combined to form an integral wire FG; wherein the integral wire receives a programming control signal; the first anti-fuse unit 11 and the adjacent second anti-fuse unit 21 are connected to each other. Use programming to control the signal.
  • the width of the overall conductor FG along the second direction is significantly greater than the width of the first programming conductor FG1 (or the second programming conductor FG2) along the second direction, thereby reducing the current density during the programming process and improving the problem of programming conductor failure.
  • Fig. 7 shows a schematic diagram of the structure of an anti-fuse array 10 provided by an embodiment of the present disclosure. As shown in Fig. 7, every two rows of anti-fuse units (one row of first anti-fuse units 11 and one row of second anti-fuse units 21) share an integral wire FG, which not only simplifies the manufacturing process, but also reduces the number of programming control signals.
  • two adjacent word lines may also be combined into one word line, so as to further simplify the manufacturing process and reduce the number of related control signals.
  • a first path is formed together with the adjacent second programming wire FG2 to increase the cross-sectional area, reduce the current density, and improve the failure problem;
  • a second path is formed together with the adjacent first programming wire FG1 to increase the cross-sectional area, reduce the current density, and improve the failure problem.
  • the first auxiliary structure 12 may be independent of the second programming wire FG2, and the second auxiliary structure 22 may be independent of the first programming wire FG1.
  • the first anti-fuse unit 11 further includes a first conductive wire 121
  • the second anti-fuse unit 21 further includes a second conductive wire 221; there is an electrical path between the first conductive wire 121 and the first programming wire FG1, and there is an electrical path between the second conductive wire 221 and the second programming wire FG2;
  • the first auxiliary structure 12 is specifically the first conductive wire 121, and the second auxiliary structure 22 is specifically the second conductive wire 221.
  • the first auxiliary structure 12 is realized by additionally setting the first conductive line 121
  • the second auxiliary structure 22 is realized by additionally setting the second conductive line 221, so that the first programming wire FG1 and the second programming wire FG2 are independent of each other, avoiding signal coupling interference and achieving better control effect.
  • first conductive wire 121 and the second conductive wire 221 there are many possible arrangements of the first conductive wire 121 and the second conductive wire 221.
  • the first conductive wire 121 and the first programming wire FG1 are located in the same plane, and the second conductive wire 221 and the second programming wire FG2 are located in the same plane; for another example, the first conductive wire 121 and the first programming wire FG1 are not located in the same plane, specifically, the first programming wire FG1 can be completely surrounded on the surface of the first programming wire FG1, or the first programming wire FG1 can be half-surrounded on the surface of the first programming wire FG1.
  • first conductive line 121 and the second conductive line 221 are both made of a conductive material.
  • the conductive material may be at least one or more of the following materials: tungsten, copper, cobalt, ruthenium, rhodium, etc.
  • the first conductive line 121 may be made of the same material as the second conductive line 221, or the first conductive line 121 may be made of a different material than the second conductive line 221.
  • first conductive line 121 and the second conductive line 221 can be various, and FIG. 8A is only one of them.
  • shape of the first conductive line 121 (or the second conductive line 221) can also be: a circle, a trapezoid, an open figure, an arc, or a combination of multiple sub-figures.
  • the shapes of the first conductive line 121 and the second conductive line 221 can be the same or different.
  • the melting point of the first conductive wire 121 is greater than the melting point of the first programming wire FG1
  • the melting point of the second conductive wire 221 is greater than the melting point of the second programming wire FG2 , which can better alleviate the breakdown problem of the programming wires.
  • the first auxiliary structure 12 specifically includes a first connecting structure 122 and a first conductive line 121; the first connecting structure connects the first programming wire FG1 and the first conductive line 121; the second auxiliary structure 22 specifically includes a second connecting structure 222 and a second conductive line 221; the second connecting structure 222 connects the second programming wire FG2 and the second conductive line 221; the first path and the second path do not overlap.
  • first programming wire FG1 , the first conductive wire 121 , and the first connection structure 122 are located in the same plane
  • second programming wire FG2 , the second conductive wire 221 , and the second connection structure 222 are located in the same plane.
  • FIG. 8C which is a side view of the first anti-fuse unit and the second anti-fuse unit
  • the first programming wire FG1 and the first conductive line 121 are located on different horizontal planes
  • the first connection structure 122 passes through the horizontal plane between the first programming wire FG1 and the first conductive line 121
  • the second programming wire FG2 and the second conductive line 221 are located on different horizontal planes
  • the second connection structure 222 passes through the horizontal plane between the second programming wire FG2 and the second conductive line 221.
  • a shallow trench isolation (STI) structure is provided between two adjacent programming devices, and the structure between the first programming wire FG1 and the active area 100, the structure between the second programming wire FG2 and the active area 100, the structure between the first word line XG1 and the active area 100, and the structure between the second word line XG2 and the active area 100 are all gate structures.
  • STI shallow trench isolation
  • the first conductive wire 121 directly covers the surface of the first programming wire FG1 along the third direction, and the first conductive wire 121 and the first connecting structure are combined into a whole;
  • the second conductive wire 221 directly covers the surface of the second programming wire FG2 along the third direction, and the second conductive wire 221 and the second connecting structure 222 are combined into a whole.
  • the first conductive wire 121 and the second conductive wire 221 will not cause the layout area of the anti-fuse array to increase, and the contact area between the first conductive wire 121 and the first programming wire FG1 is larger, and the contact area between the second conductive wire 221 and the second programming wire FG2 is larger, which is equivalent to the surface of the first programming wire FG1 and the second programming wire FG2 are each covered with a conductive layer, and the preparation process is simple.
  • the first auxiliary structure 12 is realized by additionally providing the first conductive line 121
  • the second auxiliary structure 22 is realized by additionally providing the second conductive line 221, which can also increase the cross-sectional area of the programming wire, reduce the current density, and improve the failure problem.
  • first anti-fuse unit 11 and the adjacent second anti-fuse unit 21 share an active region
  • first anti-fuse unit 11 further includes a first gate and a second gate
  • second anti-fuse unit 21 further includes a third gate and a fourth gate
  • the first gate, the second gate, the third gate and the fourth gate are all located in the active area, and the first gate, the second gate, the third gate and the fourth gate are arranged along the second direction;
  • the first gate and the active region form a first programming device 112
  • the second gate and the active region form a first selection device 111
  • the third gate and the active region form a second selection device 211
  • the fourth gate and the active region form a second programming device 212 .
  • the units shown in Figures 4, 5A, 5B, 6, 8A, 8B and 9 are only partially repeated structures in the anti-fuse array.
  • the first anti-fuse unit actually shares the active area 100 with the second anti-fuse unit above it (not shown in the above figures), and the second anti-fuse unit actually shares the active area with the first anti-fuse unit below it (not shown in the above figures).
  • the doping type, doping concentration and doping depth in the active region may be different and need to be determined according to the actual application scenario.
  • the first to fourth gates can be obtained by a conventional gate formation process.
  • the first gate forms the control terminal (G terminal) of the first programming device 112
  • the second gate forms the control terminal (G terminal) of the first selection device 111
  • the third gate forms the control terminal (G terminal) of the second selection device 211
  • the fourth gate forms the control terminal (G terminal) of the second programming device 212;
  • the active area located between the first gate and the second gate is used to form the first end of the first programming device 112 and the first end of the first selection device 111
  • the active area located between the second gate and the third gate is used to form the second end of the first selection device 111 and the second end of the second selection device 211
  • the active area located between the third gate and the fourth gate is used to form the first end of the second selection device 211 and the first end of the second programming device 212.
  • first end and the second end may be a corresponding one of a drain and a source.
  • the anti-fuse array provided in the present disclosure additionally provides a first auxiliary structure and a second auxiliary structure.
  • the existence of the first auxiliary structure and the second auxiliary structure is equivalent to expanding the cross-sectional area of the programming wire FG, thereby reducing the current density and preventing the programming wire FG from fusing.
  • the first auxiliary structure refers to the second programming wire adjacent to the first programming wire
  • the second auxiliary structure refers to the first programming wire adjacent to the second programming wire.
  • the programming wires (original FG1 and original FG2) of two adjacent rows are merged into a whole programming wire FG, so that the width of the programming wire FG is significantly increased.
  • the first auxiliary structure refers to an additionally provided first conductive layer
  • the second auxiliary structure refers to an additionally provided second conductive line.
  • a metal layer i.e., the aforementioned first conductive line and second conductive line
  • the metal layer may specifically be tungsten. In this way, on the one hand, the current density flowing through the lower programming wire FG (specifically, polysilicon material) can be significantly reduced.
  • the local temperature of the polysilicon does not rise significantly, so the risk of the programming wire FG being completely blown can be significantly reduced.
  • a layer of metal tungsten is added in parallel to the programming wire FG, even if the programming wire FG at a certain place is completely blown due to the excessively high local temperature, it will not be completely blown due to the high melting point of tungsten, thereby avoiding the risk of the programming device AF cell far away from the contact structure (FG contact) of the programming wire being completely failed due to the polysilicon blown at a certain programming wire FG, thereby improving the reliability of the system.
  • the embodiment of the present disclosure provides an anti-fuse array, which includes: a plurality of first anti-fuse units arranged in an array, the first anti-fuse unit includes a first selection device and a first programming device, the first end of the first selection device is connected to the first end of the first programming device; a plurality of bit lines, the bit lines extend along the second direction, the second ends of the first selection devices in the same column are all connected to the same bit line; a plurality of first word lines, the first word lines extend along the first direction, the control ends of the first selection devices in the same row are all connected to the same first word line; a plurality of first programming wires, the first programming wires extend along the first direction, the control ends of the first programming devices in the same row are all connected to the same first programming wire; the first programming wire has a first auxiliary structure.
  • the anti-fuse array provided by the embodiment of the present disclosure can reduce the current density on the programming wire and avoid the programming wire from being blown.
  • a schematic diagram of a semiconductor structure 40 provided by an embodiment of the present disclosure is shown.
  • the semiconductor structure 40 includes the antifuse array 10 described above.
  • the antifuse array 10 includes multiple first antifuse units, multiple bit lines, multiple first word lines, multiple first programming wires, multiple second antifuse units, multiple second word lines, and multiple second programming wires.
  • the first programming wire has a first auxiliary structure. When a voltage is applied to the first programming wire, current flows through a first path formed by the first programming wire and the first auxiliary structure, and a cross-sectional area of the first path on a plane perpendicular to the first direction is larger than a cross-sectional area of the first programming wire on a plane perpendicular to the first direction; the second programming wire has a second auxiliary structure.
  • the embodiment of the present disclosure provides a semiconductor structure which, by means of the first auxiliary structure and the second auxiliary structure, can reduce the current density of the programming wire during the breakdown of the gate oxide of the programming device, thereby avoiding the fusing of the programming wire and improving the failure problem of the programming device.
  • a schematic diagram of the structure of a memory 50 provided in an embodiment of the present disclosure is shown.
  • the memory 50 includes the aforementioned semiconductor structure 40.
  • the memory 50 includes but is not limited to a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the semiconductor structure 40 includes the aforementioned anti-fuse array 10, and the anti-fuse array 10 includes a plurality of first anti-fuse units, a plurality of bit lines, a plurality of first word lines, a plurality of first programming wires, a plurality of a second anti-fuse unit, a plurality of second word lines, and a plurality of second programming conductors, the first programming conductor having a first auxiliary structure, when a voltage is applied to the first programming conductor, current flows through a first path formed by the first programming conductor and the first auxiliary structure, and a cross-sectional area of the first path on a plane perpendicular to the first direction is larger than a cross-sectional area of the first programming conductor on a plane perpendicular to the first direction; the second programming conductor having a second auxiliary structure, when a voltage is applied to the second programming conductor, current flows through a second path formed by the second programming conductor and the second auxiliary structure, and a cross-
  • the embodiment of the present disclosure provides a semiconductor structure which, by means of the first auxiliary structure and the second auxiliary structure, can reduce the current density of the programming wire during the breakdown of the gate oxide of the programming device, thereby avoiding the fusing of the programming wire and improving the failure problem of the programming device.
  • the disclosed devices and methods can be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

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Abstract

本公开提供了一种反熔丝阵列和半导体结构，该反熔丝阵列包括：呈阵列排布的多个第一反熔丝单元，第一反熔丝单元包括第一选择器件和第一编程器件；多个第一编程导线，第一编程导线沿第一方向延伸，位于同一行的第一编程器件的控制端均连接至同一第一编程导线；第一编程导线具有第一辅助结构。

Description

一种反熔丝阵列和半导体结构
相关申请的交叉引用
本公开要求在2023年01月11日提交中国专利局、申请号为202310042066.6、申请名称为“一种反熔丝阵列和半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种反熔丝阵列和半导体结构。
背景技术
反熔丝器件(Anti–fuse，AF)是一次性可编程器件(One Time Program，OTP)，广泛用于动态随机存取存储器(Dynamic Random Access Memory,DRAM)等存储器中。反熔丝器件由两个导电层及介于导电层之间的介质层(例如栅氧化层)构成的半导体器件。未编程时，两个导电层被介质层隔开，反熔丝断路；编程时，外加高电压使介质层被高电压击穿，使得两个导电层之间形成电连接，也称为反熔丝器件被熔断。利用反熔丝器件的未熔断、熔断两种状态可以分别代表逻辑值“0”和逻辑值“1”。目前，在对反熔丝器件进行熔断处理时，可能造成相关的编程导线熔断，进而导致同一行的其他反熔丝器件失效。
发明内容
本公开实施例提供一种反熔丝阵列和半导体结构。
第一方面，本公开实施例提供一种反熔丝阵列，所述反熔丝阵列包括：
呈阵列排布的多个第一反熔丝单元，所述第一反熔丝单元包括第一选择器件和第一编程器件，所述第一选择器件的第一端和所述第一编程器件的第一端连接；
多个位线，所述位线沿第二方向延伸，位于同一列的所述第一选择器件的第二端均连接至同一所述位线；
多个第一字线，所述第一字线沿第一方向延伸，位于同一行的所述第一选择器件的控制端均连接至同一所述第一字线；
多个第一编程导线，所述第一编程导线沿所述第一方向延伸，位于同一行的所述第一编程器件的控制端均连接至同一所述第一编程导线；所述第一编程导线具有第一辅助结构，在向所述第一编程导线施加电压的情况下，电流从所述第一编程导线和所述第一辅助结构形成的第一路径中流过，且所述第一路径在垂直于所述第一方向的平面上的截面积大于所述第一编程导线在垂直于所述第一方向的平面上的截面积；其中，所述第一方向和所述第二方向相互垂直。
在一些实施例中，所述反熔丝阵列还包括：
呈阵列分布的多个第二反熔丝单元，所述第二反熔丝单元包括第二选择器件和第二编程器件，所述第二选择器件的第一端和所述第二编程器件的第一端连接；所述第一选择器件、所述第一编程器件、所述第二编程器件和所述第二选择器件沿所述第二方向依次循环排列，位于同一列的所述第二选择器件的第二端以及所述第一选择器件的第二端均连接至同一所述位线；
多个第二字线，所述第二字线沿所述第一方向延伸，位于同一行的所述第二选择器件的控制端均连接至同一所述第二字线；
多个第二编程导线，所述第二编程导线沿所述第一方向延伸，位于同一行的所述第二编程器件的控制端均连接至同一所述第二编程导线；所述第二编程导线具有第二辅助结构，在向所述第二编程导线施加电压的情况下，电流从所述第二编程导线和所述第二辅助结构形成的第二路径中流过，且所述第二路径在垂直于所述第一方向的平面上的截面积大于所述第二编程导线在垂直于所述第一方向的平面上的截面积。
在一些实施例中，沿所述第二方向，所述第一字线和所述第二字线相邻，所述第一编程导线和所述第二编程导线相邻。
在一些实施例中，所述第一编程导线和所述第二编程导线之间存在电通路；所述第一辅助结构是指与所述第一编程导线相邻的所述第二编程导线；所述第二辅助结构是指与所述第二编程导线相邻的所述第一编程导线。
在一些实施例中，所述第一辅助结构具体包括连接结构和相邻的所述第二编程导线，所述第二辅助结构具体包括所述连接结构和相邻的所述第一编程导线，所述连接结构连接相邻的所述第一编程导线和所述第二编程导线，且所述第一路径和所述第二路径重合；其中，所述连接结构、所述第一编程导线和所述第二编程导线位于同一水平面，且所述连接结构位于相邻的所述第一编程导线和所述第二编程导线之间的区域。
在一些实施例中，所述第一编程导线、相邻的所述第二编程导线以及两者之间的所述连接结构合并设置为一整体导线；其中，所述整体导线接收编程控制信号；所述第一反熔丝单元与相邻的所述第二反熔丝单元共用所述编程控制信号。
在一些实施例中，所述第一编程导线、相邻的所述第二编程导线以及两者之间的所述连接结构各自独立设置；所述第一编程导线接收所述第一反熔丝单元的第一编程控制信号，所述第二编程导线接收所述第二反熔丝单元的第二编程控制信号。
在一些实施例中，所述第一反熔丝单元还包括第一导电线，所述第二反熔丝单元还包括第二导电线；所述第一导电线与所述第一编程导线之间存在电通路，所述第二导电线与所述第二编程导线之间存在电通路；所述第一辅助结构为所述第一导电线，所述第二辅助结构为所述第二导电线。
在一些实施例中，所述第一辅助结构具体包括第一连接结构和所述第一导电线；所述第一连接结构连接所述第一编程导线和所述第一导电线；所述第二辅助结构具体包括第二连接结构和所述第二导电线；所述第二连接结构连接所述第二编程导线和所述第二导电线；所述第一路径和所述第二路径不重合；其 中，所述第一编程导线和所述第一导电线位于不同的水平面上，所述第一连接结构穿过所述第一编程导线和所述第一导电线之间的水平面；所述第二编程导线和所述第二导电线位于不同的水平面上，所述第二连接结构穿过所述第二编程导线和所述第二导电线之间的水平面。
在一些实施例中，所述第一导电线沿第三方向直接覆盖所述第一编程导线的表面，且所述第一导电线和所述第一连接结构合并设置为一整体；所述第二导电线沿第三方向直接覆盖所述第二编程导线的表面，且所述第二导电线和所述第二连接结构合并设置为一整体。
在一些实施例中，所述第一导电线和所述第一编程导线之间无直接接触，所述第一导电线、所述第一连接结构和所述第一编程导线均独立设置；所述第二导电线和所述第二编程导线之间无直接接触，所述第二导电线、所述第二连接结构和所述第二编程导线均独立设置。
在一些实施例中，所述第一导电线的熔点大于所述第一编程导线的熔点，所述第二导电线的熔点大于所述第二编程导线的熔点；其中，所述第一导电线的材料至少包括金属钨，所述第二导电线的材料至少包括金属钨。
在一些实施例中，所述第一反熔丝单元和相邻的所述第二反熔丝单元共用一有源区，所述第一反熔丝单元还包括第一栅极和第二栅极，所述第二反熔丝单元还包括第三栅极和第四栅极；其中，
所述第一栅极、所述第二栅极、所述第三栅极和所述第四栅极均位于所述有源区，且所述第一栅极、所述第二栅极、所述第三栅极、所述第四栅极沿第二方向排列；
其中，所述第一栅极和所述有源区形成所述第一编程器件，所述第二栅极和所述有源区形成所述第一选择器件，所述第三栅极和所述有源区形成所述第二选择器件，所述第四栅极和所述有源区形成所述第二编程器件。
在一些实施例中，所述第一栅极形成所述第一编程器件的控制端，所述第二栅极形成所述第一选择器件的控制端，所述第三栅极形成所述第二选择器件的控制端，所述第四栅极形成所述第二编程器件的控制端；
位于所述第一栅极和所述第二栅极之间的所述有源区用于形成所述第一编程器件的第一端和所述第一选择器件的第一端，位于所述第二栅极和所述第三栅极之间的所述有源区用于形成所述第一选择器件的第二端和所述第二选择器件的第二端，位于所述第三栅极和所述第四栅极之间的所述有源区用于形成所述第二选择器件的第一端和所述第二编程器件的第一端。
第二方面，本公开实施例提供一种半导体结构，所述半导体结构包括如第一方面所述的反熔丝阵列。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为一种反熔丝阵列的结构示意图；
图2为一种编程导线的熔断示意图；
图3为本公开实施例提供的一种反熔丝阵列的局部结构示意图一；
图4为本公开实施例提供的一种反熔丝阵列的局部结构示意图二；
图5A为本公开实施例提供的一种反熔丝阵列的局部结构示意图三；
图5B为本公开实施例提供的一种反熔丝阵列的局部结构示意图四；
图6为本公开实施例提供的一种反熔丝阵列的局部结构示意图五；
图7为本公开实施例提供的一种反熔丝阵列的整体结构示意图；
图8A为本公开实施例提供的一种反熔丝阵列的局部结构示意图六；
图8B为本公开实施例提供的一种反熔丝阵列的局部结构示意图七；
图8C为本公开实施例提供的一种反熔丝阵列的局部结构示意图八；
图9为本公开实施例提供的一种反熔丝阵列的局部结构示意图九；
图10为本公开实施例提供的另一种反熔丝阵列的整体结构示意图；
图11为本公开实施例提供的一种半导体结构的示意图；
图12为本公开实施例提供的一种存储器的结构示意图。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其它的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一 元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
参见图1，其示出了一种反熔丝阵列的结构示意图。如图1所示，在反熔丝阵列中，每2个反熔丝单元(如虚线框所示)共用一有源区，位于同一列的反熔丝单元均连接到同一条位线BL，位于同一行的反熔丝单元共用同一字线XG和同一编程导线FG。以图1为例，第1个反熔丝单元对应字线Top XG和编程导线Top FG，第2个反熔丝单元对应字线Bottom XG和编程导线Bottom FG。有源区和第一栅极(图1未示出)形成第1个反熔丝单元中的编程器件(Top AF cell)，且第一栅极连接至Top FG，有源区和第二栅极(图1未示出)形成第1个反熔丝单元中的选择器件(Top XADD)，且第二栅极连接至Top XG，有源区和第三栅极(图1未示出)形成第2个反熔丝单元中的选择器件(Bottom XADD)，且第三栅极连接到Bottom XG，有源区和第四栅极形成第2个反熔丝单元中的编程器件(Bottom AF cell)，且第四栅极连接至Bottom FG，2个反熔丝单元中的选择晶体管共源极，且位线BL引出该源极。另外，图2示出了更多数量的反熔丝单元的排列方式。如图1和图2所示，每2条编程导线是相邻的，每2条字线是相邻的。
请结合图1和图2，在对反熔丝单元进行熔断(或称为参数写入)时，需要对相应的编程导线FG施加高压(约5.5～6伏)，同时相应的位线BL置0伏，并开启相应的选择器件(XADD)，以此使得编程器件AF cell的薄栅氧化物在高压下被击穿，从而编程器件AF cell的电阻显著下降，实现参数写入。然而，如图1和图2所示，当编程器件AF cell的栅氧化物被击穿时，在编程导线FG上将流经较大的电流，因编程导线FG本身具有一定的电阻，可能由于焦耳热产生极高的温度将编程导线FG完全熔断。
值得注意的是，在电路架构中，所有处于同一行的编程器件(AF cell)共享同一条编程导线FG，并且从连接关系来看，越靠近编程导线FG的接触结构(Contact)的位置电流越大，越容易断开，这将导致一整行的编程器件(AF cell)完全失效。但是，如果过度限制写入时的能量，则可能导致部分编程器件(AF cell)无法被充分写入。
基于此，本公开实施例提供了一种反熔丝阵列，能够降低编程导线在编程器件的栅氧化物被击穿的过程中的电流密度，避免编程导线熔断，改善编程器件的失效问题。
在本公开的一实施例中，参见图3，其示出了本公开实施例提供的一种反熔丝阵列10的局部结构示意图。如图3所示，该反熔丝阵列10包括：
呈阵列排布的多个第一反熔丝单元11(图3仅以1个为例进行示出)，第一反熔丝单元11包括第一选择器件111和第一编程器件112，第一选择器件111 的第一端和第一编程器件112的第一端连接；
多个位线BL(图3仅以1个为例进行示出)，位线BL沿第二方向延伸，位于同一列的第一选择器件111的第二端均连接至同一位线；
多个第一字线XG1(图3仅以1个为例进行示出)，第一字线XG1沿第一方向延伸，位于同一行的第一选择器件111的控制端均连接至同一第一字线XG1；
多个第一编程导线FG1(图3仅以1个为例进行示出)，第一编程导线FG1沿第一方向延伸，位于同一行的第一编程器件112的控制端均连接至同一第一编程导线FG1；第一编程导线FG1具有第一辅助结构12，在向第一编程导线FG1施加电压的情况下，电流从第一编程导线FG1和第一辅助结构12形成的第一路径中流过，且第一路径在垂直于第一方向的平面上的截面积(下称横截面积)大于第一编程导线FG1在垂直于第一方向的平面上的截面积(下称横截面积)；其中，第一方向和第二方向相互垂直。
需要说明的是，如图3所示，第一选择器件111和第一编程器件112共享同一有源区100。有源区100位于半导体衬底中，半导体衬底可以是硅衬底，且半导体衬底也可以包括其它半导体元素，例如：锗(Ge)，或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其它半导体合金，例如：硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、及/或磷砷化铟镓(GaInAsP)或其组合。
在这里，有源区100中存在多个掺杂区，位于第一字线XG1正下方的有源区100的掺杂类型与位于第一字线XG1两侧的有源区100的掺杂类型不同，从而形成第一选择器件111；位于第一编程导线FG1正下方的有源区100的掺杂类型与位于第一编程导线FG1一侧的有源区100的掺杂类型不同，从而形成第一编程器件112。这样，通过对第一字线XG1施加电压可以开启第一选择器件111，然后在第一编程导线FG1上施加5～6伏的强电压，同时位线BL置0伏，能够对第一编程器件112进行击穿，以实现逻辑1的写入。
如前述，在对第一编程器件112进行击穿时，第一编程导线FG1上将流经巨大的电流，可能由于焦耳热导致温度上升，从而熔断第一编程导线FG1。在本公开实施例中，第一编程导线FG1具有第一辅助结构12，在对第一编程器件112进行击穿时，电流从第一路径(第一编程导线FG1和第一辅助结构12共同构成的)中流过，且第一路径的横截面积大于第一编程导线FG1的横截面积。这样，第一编程导线FG1上的电流密度减小，焦耳热降低，温度上升量减少，避免第一编程导线FG1熔断，能够改善反熔丝阵列的失效问题。
在图3中，行方向是指第一方向，列方向是指第二方向。
在另一些实施例中，第一方向和第二方向也可以不垂直，例如第一方向和第二方向之间的夹角可以为80度、60度等等，此时第一路径的横截面积仍然大于第一编程导线的横截面积。但是第一路径的横截面积是指与第一路径的延伸方向垂直的截面积，第一编程导线FG1的横截面积指与第一编程导线FG1的延伸方向垂直的截面积。
在一些实施例中，参见图4，其示出了本公开实施例提供的另一种反熔丝阵列10的局部结构示意图。如图4所示，反熔丝阵列10还包括：
呈阵列分布的多个第二反熔丝单元21，第二反熔丝单元21包括第二选择器件211和第二编程器件212，第二选择器件211的第一端和第二编程器件212的第一端连接；第一选择器件111、第一编程器件112、第二编程器件212和第二选择器件211沿第二方向依次循环排列，位于同一列的第二选择器件211的第二端以及第一选择器件111的第二端均连接至同一位线；
多个第二字线XG2，第二字线XG2沿第一方向延伸，位于同一行的第二选择器件211的控制端均连接至同一第二字线XG2；
多个第二编程导线FG2，第二编程导线FG2沿第一方向延伸，位于同一行的第二编程器件212的控制端均连接至同一第二编程导线FG2；第二编程导线FG2具有第二辅助结构22，在向第二编程导线FG2施加电压的情况下，电流从第二编程导线FG2和第二辅助结构22形成的第二路径中流过，且第二路径在垂直于第一方向的平面上的截面积大于第二编程导线FG2在垂直于第一方向的平面上的截面积。
需要说明的是，第一方向上，多个第一反熔丝单元11位于同一行，多个第二反熔丝单元21位于同一行；在第二方向上，一个第一反熔丝单元11和一个第二反熔丝单元21呈现镜像对称，从而构成反熔丝阵列10的重复单元。这样，反熔丝阵列的排列方式更加规整，有利于工艺制作。在其他实施例中，第一反熔丝单元11和第二反熔丝单元21可以沿其他方向(例如与目前的第二方向的夹角为30度、45度或60度等)形成一列，多个第一反熔丝单元11也可以沿其他方向(例如与目前的第一方向的夹角为30度、45度或60度等)形成一行，提高反熔丝阵列的集成密度。
类似的，在第二反熔丝单元21中，第二编程导线FG2具有第二辅助结构22，在对第二编程器件212进行参数写入时，电流从第二路径(第二编程导线FG2和第一辅助结构12共同构成的)中流过，且第二路径的横截面积大于第二编程导线FG2的横截面积。这样，第二编程导线FG2上的电流密度减小，焦耳热降低，温度上升量减少，避免第二编程导线FG2熔断，改善失效问题。
在本公开实施例中，第一编程导线FG1和第二编程导线FG2无本质区别，若后文中直接采用编程导线FG(或编程导线)则可以是指第一编程导线FG1和第二编程导线FG2中的任意一个；第一字线XG1和第二字线XG2同样无本质区别。
在一些实施例中，如图4所示，沿第二方向，第一编程导线FG1和第二编程导线FG2相邻，第一字线XG1和第二字线XG2相邻。
应理解，图4所示出的结构将在第二方向上循环排列，因此图4中的第一字线XG1实际上与另一第二字线XG2(图4未示出)相邻，因此图4中的第二字线XG2实际上与另一第一字线XG1(图4未示出)相邻。
需要说明的是，第一辅助结构12和第二辅助结构22的材料、位置、工艺和形式均具有多种可能，且第一辅助结构12和第二辅助结构22的材料(或者位置、工艺和形式)可以相同也可以不同。以下给出几种示例但不构成相关限 制。
在一些实施例中，第一编程导线FG1和第二编程导线FG2之间存在电通路；第一辅助结构12是指与第一编程导线FG1相邻的第二编程导线FG2；第二辅助结构22是指与第二编程导线FG2相邻的第一编程导线FG1。
这样，对于相邻的2个编程导线来说，一编程导线作为另一编程导线的辅助结构，无需增加额外的物理结构，降低成本。此时，在向一编程导线施加强电压的情况下，电流实际上从该编程导线和相邻的编程导线共同构成的电路径中流过，降低电流密度和焦耳热量，从而避免编程导线失效。
在后续图5A～图10中，第一方向的定义和第二方向的定义与图3/图4是相同的，不再示出坐标示意。
在一些实施例中，如图5A所示，第一辅助结构具体包括连接结构120和相邻的第二编程导线FG2，第二辅助结构具体包括该连接结构120和相邻的第一编程导线FG1，连接结构120连接相邻的第一编程导线FG1和第二编程导线FG2，且第一路径和第二路径重合。
在一种具体的实施例中，如图5A或5B所示，第一编程导线FG1、相邻的第二编程导线FG2以及两者之间的连接结构各自独立设置；第一编程导线FG1接收第一反熔丝单元11的第一编程控制信号，第二编程导线FG2接收第二反熔丝单元21的第二编程控制信号。
这样，第一编程导线FG1和第二编程导线FG2在物理上是独立设置的，但是可视为一个整体电结构。
需要说明的是，连接结构120的材料具有多种可能，即连接结构120至少包括导电材料，且导电材料可以为以下的一种或几种：钨、铜、钴、钌、铑等。
需要说明的是，连接结构120的位置具有多种可能。例如，连接结构120、第一编程导线FG1和第二编程导线FG2位于同一水平面，且连接结构120位于相邻的第一编程导线FG1和第二编程导线FG2之间的区域；又例如，连接结构120、第一编程导线FG1和第二编程导线FG2位于同一水平面，且连接结构120覆盖第一编程导线FG1的部分表面、第一编程导线FG1和第二编程导线FG2之间的区域、第二编程导线FG2的部分表面；再例如，连接结构可能沿第三方向穿越其他平面，例如采用类似跳线的原理实现第一编程导线FG1和第二编程导线FG2的连接。
在本公开实施例中，水平面是指第一方向和第二方向所在的平面。
还需要说明的是，连接结构120的形状具有多种可能。例如，如图5A所示，连接结构120为矩形，平铺于第一编程导线FG1和第二编程导线FG2之间；又例如，连接结构120为圆形，平铺于第一编程导线FG1和第二编程导线FG2之间；连接结构120的另一侧至少覆盖第二编程导线FG2的部分；再例如，如图5B所示，连接结构120包括多个子结构，每一子结构均在第一编程导线FG1和第二编程导线FG2之间形成一条电通路。
在另一种具体的实施例中，如图6所示，第一编程导线FG1、相邻的第二编程导线FG2以及两者之间的连接结构合并设置为一整体导线FG；其中，整体导线接收编程控制信号；第一反熔丝单元11与相邻的第二反熔丝单元21共 用编程控制信号。
需要说明的是，对于图6和图4可以看出，整体导线FG沿第二方向的宽度明显大于第一编程导线FG1(或第二编程导线FG2)沿第二方向的宽度，从而能够降低编程过程中的电流密度，改善编程导线失效的问题。
参见图7，其示出了本公开实施例提供的一种反熔丝阵列10的结构示意图。如图7所示，每2行反熔丝单元(1行第一反熔丝单元11和1行第二反熔丝单元21)共用一整体导线FG，不仅能够简化制备工艺，而且减少了编程控制信号的数量。
在另一些实施例中，相邻的2个字线也可以合并为一条字线，进一步简化制备工艺同。时减少相关控制信号的数量。
这样，对于第一编程导线FG1来说，通过与相邻的第二编程导线FG2共同形成第一路径以增加横截面积，减小电流密度，改善失效问题；对于第二编程导线FG2来说，通过与相邻的第一编程导线FG1共同形成第二路径以增加横截面积，减小电流密度，改善失效问题。
在另一些实施例中，第一辅助结构12可以与第二编程导线FG2无关，第二辅助结构22可以与第一编程导线FG1无关。此时，如图8A所示，第一反熔丝单元11还包括第一导电线121，第二反熔丝单元21还包括第二导电线221；第一导电线121与第一编程导线FG1之间存在电通路，第二导电线221与第二编程导线FG2之间存在电通路；第一辅助结构12具体为第一导电线121，第二辅助结构22具体为第二导电线221。
这样，通过额外设置第一导电线121实现第一辅助结构12，通过额外设置第二导电线221实现第二辅助结构22，从而第一编程导线FG1和第二编程导线FG2是相互独立的，避免信号耦合干扰，控制效果更好。
需要说明的是，第一导电线121和第二导电线221的设置形式具有多种可能。例如，如图8A所示，第一导电线121与第一编程导线FG1位于同一平面，第二导电线221与第二编程导线FG2位于同一平面；又例如，第一导电线121与第一编程导线FG1并非位于同一平面，具体的，第一编程导线FG1可以全包围环绕在第一编程导线FG1表面，或者第一编程导线FG1可以半包围环绕在第一编程导线FG1表面。
需要说明的是，第一导电线121和第二导电线221均由导电材料构成。该导电材料至少可以是以下材料的一种或几种：钨、铜、钴、钌、铑等。在这里，第一导电线121可以与第二导电线221的材料相同，或者第一导电线121可以与第二导电线221的材料不同。
另外，第一导电线121和第二导电线221的形状和尺寸可以为多种，图8A仅是其中的一种。另外，第一导电线121(或第二导电线221)的形状还可以为：圆形、梯形、非闭合图形、弧形或者包含多个子图形的组合形状。第一导电线121和第二导电线221的形状可以相同或不同。
在一些实施例中，第一导电线121的熔点大于第一编程导线FG1的熔点，第二导电线221的熔点大于第二编程导线FG2的熔点，能够更好的缓解编程导线的击穿问题。
在一些实施例中，如图8B所示，第一辅助结构12具体包括第一连接结构122和第一导电线121；第一连接结构连接第一编程导线FG1和第一导电线121；第二辅助结构22具体包括第二连接结构222和第二导电线221；第二连接结构222连接第二编程导线FG2和第二导电线221；第一路径和第二路径不重合。
需要说明的是，第一编程导线FG1和第一导电线121的位置具有多种可能，第二编程导线FG2和第二导电线221的位置具有多种可能。
例如，第一编程导线FG1、第一导电线121、第一连接结构122位于同一平面，第二编程导线FG2、第二导电线221和第二连接结构222位于同一平面。
又例如，参见图8C，且图8C为第一反熔丝单元和第二反熔丝单元的侧面视图，第一编程导线FG1和第一导电线121位于不同的水平面上，第一连接结构122穿过第一编程导线FG1和第一导电线121之间的水平面；第二编程导线FG2和第二导电线221位于不同的水平面上，第二连接结构222穿过第二编程导线FG2和第二导电线221之间的水平面。在图8C中，相邻的两个编程器件之间为指浅槽隔离结构(shallow trench isolation，STI)，第一编程导线FG1和有源区100之间的结构、第二编程导线FG2和有源区100之间的结构、第一字线XG1和有源区100之间的结构、第二字线XG2和有源区100之间的结构均为栅极结构。
在一种具体的实施例中，如图9所示，第一导电线121沿第三方向直接覆盖第一编程导线FG1的表面，且第一导电线121和第一连接结构合并设置为一整体；第二导电线221沿第三方向直接覆盖第二编程导线FG2的表面，且第二导电线221和第二连接结构222合并设置为一整体。
这样，如图9所示，第一导电线121和第二导电线221不会导致反熔丝阵列的版图面积增大，而且第一导电线121与第一编程导线FG1的接触面积较大，第二导电线221与第二编程导线FG2的接触面积较大，相当于第一编程导线FG1和第二编程导线FG2的表面各自覆盖了一导电层，制备工艺简单。
在另一种具体的实施例中，如图8B所示，第一导电线121和第一编程导线FG1之间无直接接触，第一导电线121、第一连接结构122和第一编程导线FG1均独立设置；第二导电线221和第二编程导线FG2之间无直接接触，第二导电线221、第二连接结构222和第二编程导线FG2均独立设置。也就是说，第一导电线121必须经由第一连接结构122连接到第一编程导线FG1，从而形成前述的第一路径；第二导电线221必须经由第二连接结构222连接到第二编程导线FG2，从而形成前述的第二路径。
这样，通过额外设置第一导电线121实现第一辅助结构12，通过额外设置第二导电线221实现第二辅助结构22，同样可以增加编程导线的横截面积，减小电流密度，改善失效问题。
结合图7和图10可以看出，第一反熔丝单元11和相邻的第二反熔丝单元21共用一有源区，第一反熔丝单元11还包括第一栅极和第二栅极，第二反熔丝单元21还包括第三栅极和第四栅极；其中，
第一栅极、第二栅极、第三栅极和第四栅极均位于有源区，且第一栅极、第二栅极、第三栅极、第四栅极沿第二方向排列；
其中，第一栅极和有源区形成第一编程器件112，第二栅极和有源区形成第一选择器件111，第三栅极和有源区形成第二选择器件211，第四栅极和有源区形成第二编程器件212。
特别的，在图4、图5A、图5B、图6、图8A、图8B和图9所示出的单元仅为反熔丝阵列中的部分重复结构，第一反熔丝单元实际上与其上方的第二反熔丝单元(上述图中没有示出)共用有源区100，第二反熔丝单元实际上与其下方的第一反熔丝单元(上述图中没有示出)共用有源区。
需要说明的是，有源区中的掺杂类型、掺杂浓度、掺杂深度可以不同，具体需要根据实际应用场景确定。另外，第一栅极～第四栅极均可通过常规的栅极形成工艺得到。
需要说明的是，第一栅极形成第一编程器件112的控制端(G端)，第二栅极形成第一选择器件111的控制端(G端)，第三栅极形成第二选择器件211的控制端(G端)，第四栅极形成第二编程器件212的控制端(G端)；
位于第一栅极和第二栅极之间的有源区用于形成第一编程器件112的第一端和第一选择器件111的第一端，位于第二栅极和第三栅极之间的有源区用于形成第一选择器件111的第二端和第二选择器件211的第二端，位于第三栅极和第四栅极之间的有源区用于形成第二选择器件211的第一端和第二编程器件212的第一端。
需要说明的是，第一端和第二端可以是漏极或源极中相应的一个。
综上所述，对于图2所示的反熔丝阵列，在对编程器件AF cell进行击穿时，需要在相应的编程导线FG端加高压，相应的位线BL置0伏，以击穿编程器件AF cell的栅氧化物。然而，当编程器件AF cell的栅氧化物被击穿时，在相应的编程导线FG上将流经巨大的电流，由于编程导线FG本身具有一定的电阻，因此由于焦耳热导致极高的温度将编程导线FG完全熔断。如图2的电路架构中，所有处于一行的编程器件AF cell共享同一条编程导线FG，并且从连接关系来看，越靠近编程导线的接触结构(FG contact)的位置电流越大，越容易断开，这将导致一整行的编程器件AF cell完全失效。如果过度限制写入时的能量，则可能导致部分编程器件AF cell无法被充分写入。对于以上问题，本公开提供的反熔丝阵列中额外提供了第一辅助结构和第二辅助结构，第一辅助结构和第二辅助结构的存在相当于扩展了编程导线FG的横截面积，从而电流密度减小，避免编程导线FG熔断。
在一种解决方案中，第一辅助结构是指与第一编程导线相邻的第二编程导线，第二辅助结构是指与第二编程导线相邻的第一编程导线。示例性的，如图7所示，将相邻两行的编程导线(原FG1和原FG2)合并为一整体的编程导线FG，这样，编程导线FG的宽度明显增加，一方面，在对某一行的编程器件AF cell进行写入时，流经编程导线FG的电流不变，但是电流密度降低，因此局域温度并不会显著上升；另一方面，由于编程导线FG的横截面积增加，因此编程导线FG被完全熔断的风险极大地降低了；又一方面，在图7所示的反熔丝阵列中，减少了一半的编程导线FG的控制端口，并且整个反熔丝阵列的布局并不会使功耗增加，同时简化了高压控制电路及其时序，提高了系统的可靠性。
在另一种解决方案中，第一辅助结构是指额外设置的第一导电层，第二辅助结构是指额外设置的第二导电线。示例性的，如图10所示，在所有的编程导线FG(包括第一编程导线FG1和第二编程导线FG2)并联一层金属层(即前述的第一导电线和第二导电线)，金属层具体可以为钨。这样，一方面，可使流经下层的编程导线FG(具体为多晶硅材料)的电流密度明显变低。因此在对某一行的编程器件AF cell进行写入时，多晶硅的局域温度并不会显著上升，因此编程导线FG被完全熔断的风险能够明显降低。另一方面，由于新增了一层金属钨并联在编程导线FG上，即使某处编程导线FG由于局域温度过高被完全熔断，但是由于钨的熔点高，并不会完全熔断，避免了由于某处编程导线FG多晶硅熔断使得远离编程导线的接触结构(FG contact)的编程器件AF cell完全失效的风险，提高了系统的可靠性。
本公开实施例提供了一种反熔丝阵列，该反熔丝阵列包括：呈阵列排布的多个第一反熔丝单元，第一反熔丝单元包括第一选择器件和第一编程器件，第一选择器件的第一端和第一编程器件的第一端连接；多个位线，位线沿第二方向延伸，位于同一列的第一选择器件的第二端均连接至同一位线；多个第一字线，第一字线沿第一方向延伸，位于同一行的第一选择器件的控制端均连接至同一第一字线；多个第一编程导线，第一编程导线沿第一方向延伸，位于同一行的第一编程器件的控制端均连接至同一第一编程导线；第一编程导线具有第一辅助结构。这样，本公开实施例提供的反熔丝阵列能够降低编程导线上的电流密度，避免编程导线熔断。
在本公开的另一实施例中，参见图11，其示出了本公开实施例提供的一种半导体结构40的示意图。如图11所示，该半导体结构40包括前述的反熔丝阵列10。
需要说明的是，反熔丝阵列10包括多个第一反熔丝单元、多个位线、多个第一字线、多个第一编程导线、多个第二反熔丝单元、多个第二字线、多个第二编程导线，第一编程导线具有第一辅助结构，在向第一编程导线施加电压的情况下，电流从第一编程导线和第一辅助结构形成的第一路径中流过，且第一路径在垂直于第一方向的平面上的截面积大于第一编程导线在垂直于第一方向的平面上的截面积；第二编程导线具有第二辅助结构，在向第二编程导线施加电压的情况下，电流从第二编程导线和第二辅助结构形成的第二路径中流过，且第二路径在垂直于第一方向的平面上的截面积大于第二编程导线在垂直于第一方向的平面上的截面积。
这样，本公开实施例提供了一种半导体结构，借助于第一辅助结构和第二辅助结构，能够降低编程导线在编程器件的栅氧化物被击穿的过程中的电流密度，避免编程导线熔断，改善编程器件的失效问题。
在本公开的又一实施例中，参见图12，其示出了本公开实施例提供的一种存储器50的结构示意图。如图12所示，该存储器50包括前述的半导体结构40。例如，该存储器50包括但不限于动态随机存取存储器(DRAM)。
需要说明的是，半导体结构40包括前述的反熔丝阵列10，反熔丝阵列10包括多个第一反熔丝单元、多个位线、多个第一字线、多个第一编程导线、多 个第二反熔丝单元、多个第二字线、多个第二编程导线，第一编程导线具有第一辅助结构，在向第一编程导线施加电压的情况下，电流从第一编程导线和第一辅助结构形成的第一路径中流过，且第一路径在垂直于第一方向的平面上的截面积大于第一编程导线在垂直于第一方向的平面上的截面积；第二编程导线具有第二辅助结构，在向第二编程导线施加电压的情况下，电流从第二编程导线和第二辅助结构形成的第二路径中流过，且第二路径在垂直于第一方向的平面上的截面积大于第二编程导线在垂直于第一方向的平面上的截面积。
这样，本公开实施例提供了一种半导体结构，借助于第一辅助结构和第二辅助结构，能够降低编程导线在编程器件的栅氧化物被击穿的过程中的电流密度，避免编程导线熔断，改善编程器件的失效问题。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的一些实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种反熔丝阵列，所述反熔丝阵列(10)包括：
    呈阵列排布的多个第一反熔丝单元(11)，所述第一反熔丝单元(11)包括第一选择器件(111)和第一编程器件(112)，所述第一选择器件(111)的第一端和所述第一编程器件(112)的第一端连接；
    多个位线(BL)，所述位线(BL)沿第二方向延伸，位于同一列的所述第一选择器件(111)的第二端均连接至同一所述位线(BL)；
    多个第一字线(XG1)，所述第一字线(XG1)沿第一方向延伸，位于同一行的所述第一选择器件(111)的控制端均连接至同一所述第一字线(XG1)；
    多个第一编程导线(FG1)，所述第一编程导线(FG1)沿所述第一方向延伸，位于同一行的所述第一编程器件(112)的控制端均连接至同一所述第一编程导线(FG1)；所述第一编程导线(FG1)具有第一辅助结构(12)，在向所述第一编程导线(FG1)施加电压的情况下，电流从所述第一编程导线(FG1)和所述第一辅助结构(12)形成的第一路径中流过，且所述第一路径在垂直于所述第一方向的平面上的截面积大于所述第一编程导线(FG1)在垂直于所述第一方向的平面上的截面积；其中，所述第一方向和所述第二方向相互垂直。
  2. 根据权利要求1所述的反熔丝阵列，其中，所述反熔丝阵列(10)还包括：
    呈阵列分布的多个第二反熔丝单元(21)，所述第二反熔丝单元(21)包括第二选择器件(211)和第二编程器件(212)，所述第二选择器件(211)的第一端和所述第二编程器件(212)的第一端连接；所述第一选择器件(111)、所述第一编程器件(112)、所述第二编程器件(212)和所述第二选择器件(211)沿所述第二方向依次循环排列，位于同一列的所述第二选择器件(211)的第二端以及所述第一选择器件(111)的第二端均连接至同一所述位线(BL)；
    多个第二字线(XG2)，所述第二字线(XG2)沿所述第一方向延伸，位于同一行的所述第二选择器件(211)的控制端均连接至同一所述第二字线(XG2)；
    多个第二编程导线(FG2)，所述第二编程导线(FG2)沿所述第一方向延伸，位于同一行的所述第二编程器件(212)的控制端均连接至同一所述第二编程导线(FG2)；所述第二编程导线(FG2)具有第二辅助结构(22)，在向所述第二编程导线(FG2)施加电压的情况下，电流从所述第二编程导线(FG2)和所述第二辅助结构(22)形成的第二路径中流过，且所述第二路径在垂直于所述第一方向的平面上的截面积大于所述第二编程导线(FG2)在垂直于所述第一方向的平面上的截面积。
  3. 根据权利要求2所述的反熔丝阵列，其中，
    沿所述第二方向，所述第一字线(XG1)和所述第二字线(XG2)相邻，所述第一编程导线(FG1)和所述第二编程导线(FG2)相邻。
  4. 根据权利要求3所述的反熔丝阵列，其中，所述第一编程导线(FG1)和所述第二编程导线(FG2)之间存在电通路；
    所述第一辅助结构(12)是指与所述第一编程导线(FG1)相邻的所述第二编程导线(FG2)；
    所述第二辅助结构(22)是指与所述第二编程导线(FG2)相邻的所述第一编程导线(FG1)。
  5. 根据权利要求3或4所述的反熔丝阵列，其中，
    所述第一辅助结构(12)具体包括连接结构和相邻的所述第二编程导线(FG2)，所述第二辅助结构(22)具体包括所述连接结构和相邻的所述第一编程导线(FG1)，所述连接结构连接相邻的所述第一编程导线(FG1)和所述第二编程导线(FG2)，且所述第一路径和所述第二路径重合；
    其中，所述连接结构、所述第一编程导线(FG1)和所述第二编程导线(FG2)位于同一水平面，且所述连接结构位于相邻的所述第一编程导线(FG1)和所述第二编程导线(FG2)之间的区域。
  6. 根据权利要求5所述的反熔丝阵列，其中，
    所述第一编程导线(FG1)、相邻的所述第二编程导线(FG2)以及两者之间的所述连接结构合并设置为一整体导线；
    其中，所述整体导线接收编程控制信号；所述第一反熔丝单元(11)与相邻的所述第二反熔丝单元(21)共用所述编程控制信号。
  7. 根据权利要求5所述的反熔丝阵列，其中，
    所述第一编程导线(FG1)、相邻的所述第二编程导线(FG2)以及两者之间的所述连接结构各自独立设置；
    所述第一编程导线(FG1)接收所述第一反熔丝单元(11)的第一编程控制信号，所述第二编程导线(FG2)接收所述第二反熔丝单元(21)的第二编程控制信号。
  8. 根据权利要求2所述的反熔丝阵列，其中，所述第一反熔丝单元(11)还包括第一导电线(121)，所述第二反熔丝单元(21)还包括第二导电线(221)；
    所述第一导电线(121)与所述第一编程导线(FG1)之间存在电通路，所述第二导电线(221)与所述第二编程导线(FG2)之间存在电通路；
    所述第一辅助结构(12)为所述第一导电线(121)，所述第二辅助结构(22)为所述第二导电线(221)。
  9. 根据权利要求8所述的反熔丝阵列，其中，
    所述第一辅助结构(12)具体包括第一连接结构(122)和所述第一导电线(121)；所述第一连接结构(122)连接所述第一编程导线(FG1)和所述第一导电线(121)；
    所述第二辅助结构(22)具体包括第二连接结构(222)和所述第二导电线(221)；所述第二连接结构(222)连接所述第二编程导线(FG2)和所述第二导电线(221)；所述第一路径和所述第二路径不重合；
    其中，所述第一编程导线(FG1)和所述第一导电线(121)位于不同的水平面上，所述第一连接结构(122)穿过所述第一编程导线(FG1)和所述第一导电线(121)之间的水平面；所述第二编程导线(FG2)和所述第二导电线(221)位于不同的水平面上，所述第二连接结构(222)穿过所述第二编程导线(FG2) 和所述第二导电线(221)之间的水平面。
  10. 根据权利要求9所述的反熔丝阵列，其中，
    所述第一导电线(121)沿第三方向直接覆盖所述第一编程导线(FG1)的表面，且所述第一导电线(121)和所述第一连接结构(122)合并设置为一整体；
    所述第二导电线(221)沿第三方向直接覆盖所述第二编程导线(FG2)的表面，且所述第二导电线(221)和所述第二连接结构(222)合并设置为一整体。
  11. 根据权利要求9或10所述的反熔丝阵列，其中，
    所述第一导电线(121)和所述第一编程导线(FG1)之间无直接接触，所述第一导电线(121)、所述第一连接结构(122)和所述第一编程导线(FG1)均独立设置；
    所述第二导电线(221)和所述第二编程导线(FG2)之间无直接接触，所述第二导电线(221)、所述第二连接结构(222)和所述第二编程导线(FG2)均独立设置。
  12. 根据权利要求8-11任一项所述的反熔丝阵列，其中，
    所述第一导电线(121)的熔点大于所述第一编程导线(FG1)的熔点，所述第二导电线(221)的熔点大于所述第二编程导线(FG2)的熔点；
    其中，所述第一导电线(121)的材料至少包括金属钨，所述第二导电线(221)的材料至少包括金属钨。
  13. 根据权利要求2-12任一项所述的反熔丝阵列，其中，所述第一反熔丝单元(11)和相邻的所述第二反熔丝单元(21)共用一有源区，所述第一反熔丝单元(11)还包括第一栅极和第二栅极，所述第二反熔丝单元(21)还包括第三栅极和第四栅极；其中，
    所述第一栅极、所述第二栅极、所述第三栅极和所述第四栅极均位于所述有源区，且所述第一栅极、所述第二栅极、所述第三栅极、所述第四栅极沿第二方向排列；
    其中，所述第一栅极和所述有源区形成所述第一编程器件(112)，所述第二栅极和所述有源区形成所述第一选择器件(111)，所述第三栅极和所述有源区形成所述第二选择器件(211)，所述第四栅极和所述有源区形成所述第二编程器件(212)。
  14. 根据权利要求13所述的反熔丝阵列，其中，
    所述第一栅极形成所述第一编程器件(112)的控制端，所述第二栅极形成所述第一选择器件(111)的控制端，所述第三栅极形成所述第二选择器件(211)的控制端，所述第四栅极形成所述第二编程器件(212)的控制端；
    位于所述第一栅极和所述第二栅极之间的所述有源区用于形成所述第一编程器件(112)的第一端和所述第一选择器件(111)的第一端，位于所述第二栅极和所述第三栅极之间的所述有源区用于形成所述第一选择器件(111)的第二端和所述第二选择器件(211)的第二端，位于所述第三栅极和所述第四栅极之间的所述有源区用于形成所述第二选择器件(211)的第一端和所述第二编程 器件(212)的第一端。
  15. 一种半导体结构，所述半导体结构(40)包括如权利要求1-14任一项所述的反熔丝阵列(10)。
PCT/CN2023/110842 2023-01-11 2023-08-02 一种反熔丝阵列和半导体结构 Ceased WO2024148796A1 (zh)

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