Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/30—Stacked capacitors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G13/00—Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
  • H01G13/006—Apparatus or processes for applying terminals
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/005—Electrodes
  • H01G4/008—Selection of materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/005—Electrodes
  • H01G4/012—Form of non-self-supporting electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/018—Dielectrics
  • H01G4/06—Solid dielectrics
  • H01G4/08—Inorganic dielectrics
  • H01G4/12—Ceramic dielectrics
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/018—Dielectrics
  • H01G4/06—Solid dielectrics
  • H01G4/08—Inorganic dielectrics
  • H01G4/12—Ceramic dielectrics
  • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
  • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
  • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/018—Dielectrics
  • H01G4/06—Solid dielectrics
  • H01G4/08—Inorganic dielectrics
  • H01G4/12—Ceramic dielectrics
  • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
  • H01G4/1236—Ceramic dielectrics characterised by the ceramic dielectric material based on zirconium oxides or zirconates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/228—Terminals
  • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/002—Details
  • H01G4/228—Terminals
  • H01G4/236—Terminals leading through the housing, i.e. lead-through

Definitions

• the present invention relates to a multilayer ceramic capacitor.
• Patent Document 1 discloses an example of a multilayer capacitor with reduced ESL.
• the multilayer capacitor disclosed in Patent Document 1 includes a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated.
• the capacitor body is provided with a plurality of first via conductors electrically connected to the plurality of first internal electrodes and extending to one main surface of the capacitor body, and a plurality of second via conductors electrically connected to the plurality of second internal electrodes and extending to one main surface of the capacitor body.
• the one main surface of the capacitor body is provided with a plurality of first external electrodes electrically connected to the plurality of first via conductors, respectively, and a plurality of second external electrodes electrically connected to the plurality of second via conductors, respectively.
• a method of forming the first external electrode and the second external electrode by plating using a rotary plating method is considered.
• barrel plating which is an example of a rotary plating method
• a large number of capacitor bodies and a large number of conductive media are placed in a rotatable barrel, and the barrel is rotated in a plating solution and an electric current is applied to form plating in the plating formation area on the surface of the capacitor body where the first via conductor and the second via conductor are exposed.
• the conductive media are, for example, metal spheres. According to the rotary plating method, it is possible to form the first external electrode and the second external electrode on the surface of a large number of capacitor bodies in a single plating process, and form a large number of multilayer capacitors at once.
• the area of the surface of the capacitor body where the first and second via conductors are exposed is small, so there is a possibility that the conductive medium will not come into contact with the plating formation area during the plating process, and a plating film will not be formed, or that a multilayer capacitor will be manufactured in which the plating film is not sufficiently formed.
• the present invention aims to solve the above problems and provide a multilayer ceramic capacitor that allows for more reliable formation of external electrodes using the rotary plating method.
• the multilayer ceramic capacitor of the present invention is a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; a first via conductor provided inside the capacitor body and electrically connected to the first internal electrodes; a second via conductor provided inside the capacitor body and electrically connected to the second internal electrodes; a first external electrode provided on at least one of a first main surface and a second main surface that face each other in a stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode among surfaces of the capacitor body, the first external electrode being connected to the first via conductor; a second external electrode provided on the at least one main surface of the capacitor body and connected to the second via conductor; a first metal layer provided on a side surface of the capacitor body other than the first principal surface and the second principal surface, the first metal layer being electrically connected to the first via conductor;
• the present invention is characterized by comprising:
• a multilayer ceramic capacitor comprises: a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; a first via conductor provided inside the capacitor body and electrically connected to the first internal electrodes; a second via conductor provided inside the capacitor body and electrically connected to the second internal electrodes; a first external electrode provided on at least one of a first main surface and a second main surface that face each other in a stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode among surfaces of the capacitor body, the first external electrode being connected to the first via conductor; a second external electrode provided on the at least one main surface of the capacitor body and connected to the second via conductor; a first metal layer provided on a side surface of the capacitor body other than the first principal surface and the second principal surface, the first metal layer being electrically connected to the first via conductor; a second metal layer provided on the side surface of the capacitor body and electrically connected to the
• FIG. 1A is a top view diagrammatically illustrating a multilayer ceramic capacitor according to a first embodiment of the present invention
• FIG. 1B is a bottom view diagrammatically illustrating the multilayer ceramic capacitor according to the first embodiment
• 2 is a side view of the multilayer ceramic capacitor shown in FIG. 1 as viewed in the direction of arrow Y1.
• 3 is a cross-sectional view showing a schematic structure of the multilayer ceramic capacitor shown in FIG. 1 taken along line III-III.
• FIG. 4A is a plan view diagrammatically showing a first internal electrode
• FIG. 4B is a plan view diagrammatically showing a second internal electrode.
• FIG. 1 is a side view showing a schematic diagram of a state in which the multilayer ceramic capacitor according to the first preferred embodiment is mounted on a mounting board.
• (a) is a plan view showing a schematic of a first internal electrode when a first connection layer and a second connection layer are each provided on a single layer
• (b) is a plan view showing a schematic of a second internal electrode when a first connection layer and a second connection layer are each provided on a single layer.
• FIG. 1A is a plan view showing a schematic view of a first internal electrode and a first connection layer when a first connection layer is provided on a layer on which a first internal electrode is provided, but a second connection layer is not provided; and FIG. 1B is a plan view showing a schematic view of a second internal electrode and a second connection layer when a second connection layer is provided on a layer on which a second internal electrode is provided, but a first connection layer is not provided.
• 4 is a flowchart illustrating an example of a method for manufacturing a multilayer ceramic capacitor.
• 1A is a top view diagrammatically illustrating the multilayer ceramic capacitor according to a second embodiment
• FIG. 1B is a bottom view diagrammatically illustrating the multilayer ceramic capacitor according to the second embodiment.
• FIG. 11 is a side view of the multilayer ceramic capacitor shown in FIG. 10 as viewed in the direction of arrow Y2.
• 10A is a plan view diagrammatically illustrating a first internal electrode of a multilayer ceramic capacitor according to a second preferred embodiment of the present invention
• FIG. 10B is a plan view diagrammatically illustrating a second internal electrode of the multilayer ceramic capacitor according to a second preferred embodiment of the present invention.
• 10A is a top view diagrammatically illustrating a multilayer ceramic capacitor according to a third preferred embodiment of the present invention
• FIG. 10B is a bottom view diagrammatically illustrating the multilayer ceramic capacitor.
• FIG. 10A is a plan view showing a schematic view of a first internal electrode of a multilayer ceramic capacitor according to a third preferred embodiment of the present invention
• FIG. 10B is a plan view showing a schematic view of a second internal electrode of the multilayer ceramic capacitor according to a third preferred embodiment of the present invention
• 10A is a top view diagrammatically illustrating a multilayer ceramic capacitor according to a fourth preferred embodiment of the present invention
• FIG. 10B is a bottom view diagrammatically illustrating the multilayer ceramic capacitor.
• 16 is a side view of the multilayer ceramic capacitor shown in FIG. 15 as viewed in the direction of arrow Y3.
• FIG. 10A is a plan view showing a schematic view of a first internal electrode of a multilayer ceramic capacitor according to a fourth preferred embodiment of the present invention
• FIG. 10B is a plan view showing a schematic view of a second internal electrode of the multilayer ceramic capacitor according to a fourth preferred embodiment of the present invention
• 13A is a plan view showing a schematic diagram of a first internal electrode and a first connection layer in a case where a first connection layer is provided on a layer on which a first internal electrode is provided but a second connection layer is not provided; and FIG.
• 13B is a plan view showing a schematic diagram of a second internal electrode and a second connection layer in a case where a second connection layer is provided on a layer on which a second internal electrode is provided but a first connection layer is not provided;
• 13 is a top view of a multilayer ceramic capacitor, which diagrammatically illustrates another arrangement pattern of the external electrodes when the number of external electrodes in the row direction is an odd number and the number of external electrodes in the column direction is an odd number.
• FIG. 5A and 5B are top views of a multilayer ceramic capacitor, each showing a schematic diagram of another arrangement pattern of the external electrodes when the number of external electrodes in the row direction is an even number and the number of external electrodes in the column direction is an odd number.
• 5A and 5B are top views of a multilayer ceramic capacitor, each showing a schematic diagram of another arrangement pattern of the external electrodes when the number of external electrodes in the row direction is an even number and the number of external electrodes in the column direction is an even number.
• Fig. 1(a) is a top view diagrammatically showing a multilayer ceramic capacitor 100 according to a first embodiment of the present invention
• Fig. 1(b) is a bottom view diagrammatically showing the multilayer ceramic capacitor 100 according to the first embodiment.
• a first main surface 1a of a capacitor body 1 described later is referred to as the top surface
• a second main surface 1b is referred to as the bottom surface.
• Fig. 2 is a side view of the multilayer ceramic capacitor 100 shown in Fig. 1 as viewed in the direction of an arrow Y1.
• Fig. 3 is a cross-sectional view diagrammatically showing the structure of the multilayer ceramic capacitor 100 shown in Fig. 1 when cut along line III-III.
• the multilayer ceramic capacitor 100 includes a capacitor body 1, a first via conductor 5, a second via conductor 6, a first external electrode 11, a second external electrode 12, and a first metal layer 21.
• the multilayer ceramic capacitor 100 in this embodiment further includes a second metal layer 22.
• the multilayer ceramic capacitor 100 in this embodiment further includes a first connection layer 31 and a second connection layer 32.
• the capacitor body 1 has a structure in which a plurality of dielectric layers 2, a plurality of first internal electrodes 3, and a plurality of second internal electrodes 4 are stacked. More specifically, the capacitor body 1 has a structure in which the first internal electrodes 3 and the second internal electrodes 4 are stacked alternately with the dielectric layers 2 interposed therebetween.
• the dielectric layer 2 may be made of any material, and may be made of a ceramic material mainly composed of BaTiO3 , CaTiO3 , SrTiO3 , SrZrO3 , CaZrO3 , etc. These main components may contain minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc., which are contained in smaller amounts than the main components.
• the capacitor body 1 may have any shape.
• the capacitor body 1 has a rectangular parallelepiped shape as a whole.
• a rectangular parallelepiped shape as a whole is not a perfect rectangular parallelepiped shape, for example, a shape in which the corners and edges of the rectangular parallelepiped are rounded, or a shape in which the surface of the rectangular parallelepiped has irregularities, but has six surfaces and can be considered as a rectangular parallelepiped as a whole.
• the capacitor body 1 has a first main surface 1a, a second main surface 1b, a first side surface 1c, a second side surface 1d, a third side surface 1e, and a fourth side surface 1f.
• the first main surface 1a and the second main surface 1b of the capacitor body 1 are surfaces that face the stacking direction T of the dielectric layer 2, the first internal electrode 3, and the second internal electrode 4.
• the first side surface 1c to the fourth side surface 1f of the capacitor body 1 constitute four side surfaces of the capacitor body 1 other than the first main surface 1a and the second main surface 1b.
• the first side surface 1c faces the third side surface 1e
• the second side surface 1d faces the fourth side surface 1f.
• the first side surface 1c to the fourth side surface 1f of the capacitor body 1 are perpendicular to the first main surface 1a and the second main surface 1b, respectively, but they do not have to be perpendicular to each other.
• the dimensions of the capacitor body 1 are arbitrary.
• the vertical dimension of the rectangular capacitor body 1 in plan view in the stacking direction T can be 0.3 mm to 3.0 mm
• the horizontal dimension can be 0.3 mm to 3.0 mm
• the dimension in the stacking direction T can be 50 ⁇ m to 200 ⁇ m.
• the dimension of the capacitor body 1 in the stacking direction T refers to the thickness of the capacitor body 1.
• FIG. 4(a) is a plan view that shows a schematic of the first internal electrode 3
• FIG. 4(b) is a plan view that shows a schematic of the second internal electrode 4.
• the dielectric layer 2 and the first and second via conductors 5 and 6 are also shown.
• FIG. 4(a) also shows the second connection layer 32, which will be described later
• FIG. 4(b) also shows the first connection layer 31, which will be described later.
• the shape of the dielectric layer 2 when viewed in the stacking direction T is rectangular.
• the shape of the first internal electrode 3 when viewed in the stacking direction T is not rectangular.
• the first internal electrode 3 has a shape obtained by removing a pair of corners from a rectangle.
• the shape of the removed corners is, for example, rectangular.
• the shape of the second internal electrode 4 when viewed in the stacking direction T is not rectangular.
• the second internal electrode 4 has a shape obtained by removing a pair of corners from a rectangle.
• the shape of the removed corners is, for example, rectangular.
• the shape of the first internal electrode 3 is not limited to the shape shown in Figure 4(a), and the shape of the second internal electrode 4 is not limited to the shape shown in Figure 4(b).
• the first internal electrode 3 and the second internal electrode 4 may be made of any material, and may be, for example, a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing these metals.
• the first internal electrode 3 and the second internal electrode 4 may contain, as a common material, the same ceramic material as the dielectric ceramic contained in the dielectric layer 2. In that case, the proportion of the common material contained in the first internal electrode 3 and the second internal electrode 4 is, for example, 20 vol % or less.
• the thickness of the first internal electrode 3 and the second internal electrode 4 is arbitrary, and can be, for example, about 0.3 ⁇ m or more and 1.0 ⁇ m or less.
• the number of layers of the first internal electrode 3 and the second internal electrode 4 is arbitrary.
• the total number of layers of the first internal electrode 3 and the second internal electrode 4 can be about 10 layers or more and 150 layers or less.
• a capacitance is formed by the first internal electrode 3 and the second internal electrode 4 facing each other via the dielectric layer 2.
• the first via conductors 5 and the second via conductors 6 are provided inside the capacitor body 1.
• a plurality of first via conductors 5 and a plurality of second via conductors 6 are provided in a matrix. More specifically, four via conductors including two first via conductors 5 and two second via conductors 6 are provided at positions corresponding to the four corners of the rectangular capacitor body 1 in a plan view in the stacking direction T.
• the arrangement of the first via conductors 5 and the second via conductors 6 is not limited to a matrix arrangement.
• the number of first via conductors 5 and the number of second via conductors 6 are not limited to two, and can be any number.
• the first via conductor 5 is provided inside the capacitor body 1 in a manner extending in the stacking direction T from the first main surface 1a to the second main surface 1b of the capacitor body 1, and is electrically connected to the multiple first internal electrodes 3.
• the first via conductor 5 is separated from the second internal electrode 4 and is insulated from the second internal electrode 4.
• the second via conductor 6 is provided inside the capacitor body 1 in a manner extending in the stacking direction T from the first main surface 1a to the second main surface 1b of the capacitor body 1, and is electrically connected to a plurality of second internal electrodes 4.
• the second via conductor 6 is separated from the first internal electrode 3 and is insulated from the first internal electrode 3.
• the first via conductor 5 and the second via conductor 6 are not exposed to the second main surface 1b of the capacitor body 1, but may be exposed.
• the first via conductor 5 and the second via conductor 6 may be made of any material, for example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals.
• the first external electrode 11 is provided on at least one of the first and second main surfaces 1a and 1b of the surface of the capacitor body 1, and is connected to the first via conductor 5.
• the first via conductor 5 is exposed to the first main surface 1a of the capacitor body 1, and the first external electrode 11 is provided on the first main surface 1a of the capacitor body 1. More specifically, the first external electrode 11 is provided at a position overlapping the first via conductor 5 in the stacking direction T.
• the number of the first external electrodes 11 is the same as the number of the first via conductors 5, and is two in the example shown in FIG. 1. However, the number of the first external electrodes 11 is not limited to two.
• the first via conductor 5 is electrically connected to a plurality of first internal electrodes 3, and therefore the first external electrode 11 is electrically connected to a plurality of first internal electrodes 3.
• the second external electrode 12 is provided on at least one of the above-mentioned main surfaces of the capacitor body 1 and is connected to the second via conductor 6.
• the second via conductor 6 is exposed to the first main surface 1a of the capacitor body 1, and like the first external electrode 11, the second external electrode 12 is provided on the first main surface 1a of the capacitor body 1. More specifically, the second external electrode 12 is provided at a position overlapping the second via conductor 6 in the stacking direction T.
• the number of second external electrodes 12 is the same as the number of second via conductors 6, and is two in the example shown in FIG. 1. However, the number of second external electrodes 12 is not limited to two.
• the second via conductor 6 is electrically connected to a plurality of second internal electrodes 4, and therefore the second external electrode 12 is electrically connected to a plurality of second internal electrodes 4.
• the first connection layer 31 is in contact with the first via conductor 5 but is spaced apart from the second internal electrode 4.
• the second connection layer 32 is in contact with the second via conductor 6 but is spaced apart from the first internal electrode 3.
• the conductive first connection layer 31 and second connection layer 32 may be made of any material, for example, the same material as the first internal electrode 3 and second internal electrode 4.
• the first metal layer 21 and the second metal layer 22 can also be joined to the land electrodes of the mounting substrate via solder.
• the first metal layer 21 and the second metal layer 22 are not provided in the areas where soldering is not performed when mounting the multilayer ceramic capacitor 100, so the configuration can be simplified and manufacturing costs can be reduced.
• the first connection layer 31 is not in direct contact with the first internal electrode 3, it is possible to suppress the intrusion of plating solution from the outside to the inside during manufacturing, and also to suppress the intrusion of moisture, etc. from the outside to the inside of the finished product. That is, in a configuration in which the first connection layer 31 is in direct contact with the first internal electrode 3, plating solution, moisture, etc. easily infiltrate from the outside of the capacitor body 1 through the first connection layer 31 and the first internal electrode 3 to the inside, but since the first connection layer 31 is separated from the first internal electrode 3, it is possible to suppress the intrusion of plating solution, moisture, etc. into the inside. Similarly, since the second connection layer 32 is not in direct contact with the second internal electrode 4, it is possible to suppress the intrusion of plating solution, moisture, etc. from the outside to the inside of the capacitor body 1.
• step S6 following step S5, the unsintered chip is sintered to produce the capacitor body 1.
• the first via conductor 5 and the second via conductor 6 are exposed on the first main surface 1a of the produced capacitor body 1, and the first connection layer 31 and the second connection layer 32 are exposed on the side surfaces.
• the first metal layer 21 and the second metal layer 22 are provided at positions that span two side surfaces of the capacitor body 1. Therefore, compared to a configuration in which the first metal layer 21 and the second metal layer 22 are provided only on one side surface of the capacitor body 1, there are more opportunities for the conductive medium to come into contact with the first metal layer 21 and the second metal layer 22 during spin plating, and the formation of the first external electrode 11 and the second external electrode 12 can be more reliably performed.
• each of the first external electrodes 11 and the second external electrodes 12 are provided.
• a total of 12 external electrodes including the first external electrodes 11 and the second external electrodes 12 are arranged in a matrix.
• four external electrodes are arranged in the row direction (horizontal direction in the figure) and three external electrodes are arranged in the column direction (vertical direction in the figure), but the number of external electrodes in the row direction is not limited to four, and the number of external electrodes in the column direction is not limited to three.
• FIG. 12(a) is a plan view that typically shows the first internal electrode 3
• FIG. 12(b) is a plan view that typically shows the second internal electrode 4.
• the dielectric layer 2, the first via conductor 5, and the second via conductor 6 are also shown.
• FIG. 12(a) also shows the first connection layer 31, and
• FIG. 12(b) also shows the second connection layer 32.
• the first connection layer 31 is provided on the layer on which the first internal electrode 3 is provided.
• the first connection layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 through the first via conductor 5.
• the first connection layer 31 is not in direct contact with the first internal electrode 3.
• the second connection layer 32 is not provided on the layer on which the first internal electrode 3 is provided.
• the second connection layer 32 is provided on the layer on which the second internal electrode 4 is provided.
• the second connection layer 32 is in contact with the second via conductor 6 and is electrically connected to the second internal electrode 4 through the second via conductor 6.
• the second connection layer 32 is not in direct contact with the second internal electrode 4.
• the first connection layer 31 is not provided on the layer on which the second internal electrode 4 is provided.
• the multilayer ceramic capacitor 100A in this embodiment like the multilayer ceramic capacitor 100 in the first embodiment, has a first metal layer 21 electrically connected to the first via conductor 5 and a second metal layer 22 electrically connected to the second via conductor 6 on the side of the capacitor body 1, so that the first external electrode 11 and the second external electrode 12 can be formed more reliably by spin plating.
• the first metal layer 21 and the second metal layer 22 are provided on the side surfaces of the capacitor body 1, but it is also possible to configure the capacitor body 1 so that only the first metal layer 21 is provided.
• FIG. 13(a) is a top view that shows a schematic of a multilayer ceramic capacitor 100B according to the third embodiment
• FIG. 13(b) is a bottom view that shows a schematic of a multilayer ceramic capacitor 100B according to the third embodiment.
• first external electrodes 11 and four second external electrodes 12 are provided in the multilayer ceramic capacitor 100B of the third embodiment.
• a total of nine external electrodes including the first external electrodes 11 and the second external electrodes 12 are arranged in a matrix.
• three external electrodes are arranged in the row direction and three in the column direction, but the number of external electrodes in the row direction is not limited to three, and the number of external electrodes in the column direction is not limited to three.
• the first external electrodes 11 are provided at the four corner positions and the center position out of the nine positions in the three rows and three columns, and the second external electrodes 12 are provided at the other positions.
• the multilayer ceramic capacitor 100B in this embodiment has a first metal layer 21 provided on the side of the capacitor body 1, but does not have a second metal layer.
• the first metal layers 21 are provided at four locations: a corner position spanning from the first side 1c to the second side 1d of the capacitor body 1, a corner position spanning from the second side 1d to the third side 1e, a corner position spanning from the third side 1e to the fourth side 1f, and a corner position spanning from the fourth side 1f to the first side 1c.
• the locations at which the first metal layers 21 are provided are not limited to the above-mentioned locations, and the number of first metal layers 21 is not limited to four.
• FIG. 14(a) is a plan view that shows a schematic of the first internal electrode 3
• FIG. 14(b) is a plan view that shows a schematic of the second internal electrode 4.
• the dielectric layer 2, the first via conductor 5, the second via conductor 6, and the first connection layer 31 are also shown.
• the first internal electrode 3 has a plurality of first through holes 3a for inserting the second via conductors 6 therethrough.
• the second internal electrode 4 has a second through hole 4a for inserting the first via conductors 5 therethrough.
• the first via conductor 5 provided at a position overlapping the second internal electrode 4 in the stacking direction T passes through the second through hole 4a formed in the second internal electrode 4, and is insulated from the second internal electrode 4.
• the second via conductor 6 provided at a position overlapping the first internal electrode 3 in the stacking direction T passes through the first through hole 3a formed in the first internal electrode 3, and is insulated from the first internal electrode 3.
• the first connection layer 31 is provided on each of the layers on which the first internal electrode 3 is provided and the second internal electrode 4 is provided.
• the first connection layer 31 is provided at the four corner positions of the rectangular dielectric layer 2 when viewed in the stacking direction T.
• the first connection layer 31 is in contact with the nearest first via conductor 5 and is electrically connected to the first internal electrode 3 through the first via conductor 5.
• the first connection layer 31 is not in direct contact with the first internal electrode 3.
• the first metal layer 21 electrically connected to the first via conductor 5 is provided on the side of the capacitor body 1, so that the first external electrode 11 can be formed more reliably by rotary plating.
• a total of nine external electrodes are provided in a matrix, and only the first metal layer 21 is provided on the side surface of the capacitor body 1.
• a total of nine external electrodes are arranged in a matrix, and a first metal layer 21 and a second metal layer 22 are provided on the side of the capacitor body 1.
• FIG. 15(a) is a top view that shows a schematic of a multilayer ceramic capacitor 100C according to the fourth embodiment
• FIG. 15(b) is a bottom view that shows a schematic of the multilayer ceramic capacitor 100C
• FIG. 16 is a side view of the multilayer ceramic capacitor 100C shown in FIG. 15 as viewed in the direction of the arrow Y3.
• the multilayer ceramic capacitor 100C in the fourth embodiment also has five first external electrodes 11 and four second external electrodes 12. As shown in FIG. 15(a), the positions of the multiple first external electrodes 11 and multiple second external electrodes 12 are the same as those of the multilayer ceramic capacitor 100B in the third embodiment.
• the positions of the first metal layers 21 are also the same as those of the multilayer ceramic capacitor 100B in the third embodiment. That is, the first metal layers 21 are provided at four corner positions that span the two side surfaces of the capacitor body 1.
• the second metal layer 22 is provided between two first metal layers 21 on each of the first side 1c, the second side 1d, the third side 1e, and the fourth side 1f of the capacitor body 1. That is, as shown in FIG. 16, the second metal layer 22 provided on the first side 1c of the capacitor body 1 is located between the two first metal layers 21 provided on the first side 1c. Similarly, the second metal layer 22 provided on the second side 1d of the capacitor body 1 is located between the two first metal layers 21 provided on the second side 1d. The second metal layer 22 provided on the third side 1e of the capacitor body 1 is located between the two first metal layers 21 provided on the third side 1e. The second metal layer 22 provided on the fourth side 1f of the capacitor body 1 is located between the two first metal layers 21 provided on the fourth side 1f.
• FIG. 17(a) is a plan view that shows a schematic of the first internal electrode 3
• FIG. 17(b) is a plan view that shows a schematic of the second internal electrode 4.
• FIGS. 17(a) and (b) also show the dielectric layer 2, the first via conductor 5, the second via conductor 6, the first connection layer 31, and the second connection layer 32.
• the first internal electrode 3 has a plurality of first through holes 3a for inserting the second via conductors 6 therethrough.
• the second internal electrode 4 has a second through hole 4a for inserting the first via conductors 5 therethrough.
• the first via conductor 5 provided at a position overlapping the second internal electrode 4 in the stacking direction T passes through the second through hole 4a formed in the second internal electrode 4, and is insulated from the second internal electrode 4.
• the second via conductor 6 provided at a position overlapping the first internal electrode 3 in the stacking direction T passes through the first through hole 3a formed in the first internal electrode 3, and is insulated from the first internal electrode 3.
• the first connection layer 31 and the second connection layer 32 are provided on the layer on which the first internal electrode 3 is provided and the layer on which the second internal electrode 4 is provided, respectively.
• the first connection layer 31 is provided at the four corner positions of the rectangular dielectric layer 2 when viewed in the stacking direction T.
• the first connection layer 31 is in contact with the nearest first via conductor 5 and is electrically connected to the first internal electrode 3 through the first via conductor 5.
• the first connection layer 31 is not in direct contact with the first internal electrode 3.
• the second connection layer 32 is provided at the center of each of the four sides of the rectangular dielectric layer 2 when viewed in the stacking direction T.
• the second connection layer 32 is in contact with the closest second via conductor 6 and is electrically connected to the second internal electrode 4 through the second via conductor 6.
• the second connection layer 32 is not in direct contact with the second internal electrode 4.
• the dielectric layer 2, the first via conductor 5, and the second via conductor 6 are also shown.
• the number and arrangement positions of the first via conductor 5 and the second via conductor 6 are the same as the number and arrangement positions of the first via conductor 5 and the second via conductor 6 shown in Fig. 17.
• the first connection layer 31 is in contact with the nearest first via conductor 5 and is electrically connected to the first internal electrode 3 through the first via conductor 5.
• the first connection layer 31 is not in direct contact with the first internal electrode 3.
• the position of the first connection layer 31 when viewed in the stacking direction T is the same as the position shown in FIG. 17(a).
• the second connection layer 32 is not provided on the layer on which the first internal electrode 3 is provided.
• the second connection layer 32 is in contact with the closest second via conductor 6 and is electrically connected to the second internal electrode 4 through the second via conductor 6.
• the second connection layer 32 is not in direct contact with the second internal electrode 4.
• the position of the second connection layer 32 when viewed in the stacking direction T is the same as the position shown in FIG. 17(b).
• the first connection layer 31 is not provided on the layer on which the second internal electrode 4 is provided.
• the configuration shown in Figures 18(a) and (b) allows the number of first connection layers 31 and second connection layers 32 to be reduced by approximately half compared to the configuration shown in Figures 17(a) and (b), making it possible to prevent the intrusion of plating solution from the outside into the inside during manufacturing, and to prevent the intrusion of moisture, etc. from the outside into the inside of the finished product.
• plating solution and moisture are likely to infiltrate into the positions on the side of the capacitor body 1 where the first connection layers 31 and second connection layers 32 are exposed, but the small number of first connection layers 31 and second connection layers 32 prevents the intrusion of plating solution, moisture, etc. into the inside.
• the arrangement patterns shown in Figures 20(a) and 20(b) can be used.
• the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the row direction, and the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the column direction.
• the same type of external electrodes are arranged in the row direction, and the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the column direction.
• the first metal layer 21 and the second metal layer 22 are provided on the side of the capacitor body 1, and in the arrangement pattern shown in Figure 20(b), only the first metal layer 21 is provided on the side of the capacitor body 1.
• the external electrodes even if the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is even, it is possible to arrange the external electrodes in the same arrangement pattern as when the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd.
• the arrangement patterns shown in Figures 21(a) and 21(b) can be used.
• the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the row direction, and the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the column direction.
• the same type of external electrodes are arranged in the row direction, and the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the column direction.
• first external electrodes 11 and the second external electrodes 12 are alternate in the row direction, and arrange the same type of external electrodes in the column direction.
• first metal layer 21 and the second metal layer 22 are provided on the side surfaces of the capacitor body 1.
• the first metal layer 21 and the second metal layer 22 may not be joined to the land electrodes of the mounting substrate. In that case, the first metal layer 21 and the second metal layer 22 are unnecessary for practical use as a finished product, so the first metal layer 21 and the second metal layer 22 may be covered with a resin or the like.
• the multilayer ceramic capacitor in this application is as follows. ⁇ 1>.
• a multilayer ceramic capacitor comprising:
• the multilayer ceramic capacitor described in ⁇ 1> further comprising a first connection layer provided inside the capacitor body and electrically connecting the first via conductor and the first metal layer.
• a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; a first via conductor provided inside the capacitor body and electrically connected to the first internal electrodes; a second via conductor provided inside the capacitor body and electrically connected to the second internal electrodes; a first external electrode provided on at least one of a first main surface and a second main surface that face each other in a stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode among surfaces of the capacitor body, the first external electrode being connected to the first via conductor; a second external electrode provided on the at least one main surface of the capacitor body and connected to the second via conductor; a first metal layer provided on a side surface of the capacitor body other than the first principal surface and the second principal surface, the first metal layer being electrically connected to the first via conductor; a second metal layer provided on the side surface of the capacitor body and electrically connected to the second via conductor;
• a multilayer ceramic capacitor comprising
• the capacitor body has four side surfaces
• the first connection layer is provided on a layer on which the second internal electrodes are provided,
• the multilayer ceramic capacitor described in ⁇ 4> characterized in that the first connection layer and the second connection layer are provided on the layer on which the first internal electrode is provided and the layer on which the second internal electrode is provided, respectively.
• the first connection layer is in contact with the first via conductor but is not in contact with the first internal electrode

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• 2023
  • 2023-12-20 JP JP2024567669A patent/JP7831647B2/ja active Active
  • 2023-12-20 CN CN202380084288.2A patent/CN120266236A/zh active Pending
  • 2023-12-20 WO PCT/JP2023/045609 patent/WO2024143087A1/ja not_active Ceased
• 2025
  • 2025-04-07 US US19/171,466 patent/US20250232920A1/en active Pending

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