Classifications

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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/43—Layouts of interconnections
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  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
  • H10D84/851—Complementary IGFETs, e.g. CMOS comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
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  • H10D30/501—FETs having stacked nanowire, nanosheet or nanoribbon channels
  • H10D30/502—FETs having stacked nanowire, nanosheet or nanoribbon channels characterised by the stacked channels
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  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
  • H10D62/118—Nanostructure semiconductor bodies
  • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
  • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
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  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
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  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/832—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels
• • H—ELECTRICITY
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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/42—Vias, e.g. via plugs
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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/427—Power or ground buses
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/435—Cross-sectional shapes or dispositions of interconnections
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/019—Manufacture or treatment of FETs having stacked nanowire, nanosheet or nanoribbon channels
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/501—FETs having stacked nanowire, nanosheet or nanoribbon channels
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
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  • H10D84/90—Masterslice integrated circuits
  • H10D84/903—Masterslice integrated circuits comprising field effect technology
  • H10D84/907—CMOS gate arrays
  • H10D84/968—Macro-architecture
  • H10D84/974—Layout specifications, i.e. inner core regions
  • H10D84/981—Power supply lines
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  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts

Definitions

• This disclosure relates to a semiconductor integrated circuit device.
• the standard cell method is known as a method for forming semiconductor integrated circuits on a semiconductor substrate.
• the standard cell method is a method for designing an LSI chip by preparing basic units with specific logical functions (e.g. inverters, latches, flip-flops, full adders, etc.) as standard cells in advance, placing multiple standard cells on a semiconductor substrate, and connecting these standard cells with wiring.
• basic units with specific logical functions e.g. inverters, latches, flip-flops, full adders, etc.
• transistors which are the basic building blocks of LSIs, have achieved increased integration density, lower operating voltages, and faster operating speeds through the reduction of gate length (scaling). In recent years, however, excessive scaling has caused problems with off-current and the resulting dramatic increase in power consumption. To solve this problem, there has been active research into three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type.
• One example of a three-dimensional transistor is the nanosheet FET (Field Effect Transistor).
• Patent document 1 discloses a technique for achieving even higher integration by providing wiring on the back surface of the substrate directly below the transistor and connecting the source/drain of the transistor to this wiring.
• nanosheet FETs In order to improve manufacturing precision, suppress manufacturing variability, and improve yields in semiconductor integrated circuit devices having nanosheet FETs, it is preferable to form multiple nanosheet FETs without discontinuous portions. To achieve this, nanosheet FETs must also be formed between adjacent standard cells. However, in this configuration, it is necessary to ensure that the nanosheet FETs formed between adjacent standard cells do not affect circuit operation.
• This disclosure provides a layout structure for a semiconductor integrated circuit device configured with wiring directly under a transistor, forming a nanosheet FET between adjacent standard cells that does not affect circuit operation.
• the semiconductor integrated circuit device comprises a first and a second standard cell arranged adjacent to each other in a first direction, the first standard cell constituting a channel, source and drain of a first transistor of a first conductivity type, a first active region including a nanosheet extending in the first direction as the channel, a first power supply wiring formed on the back side of the first transistor, extending in the first direction and overlapping with the first active region in a planar view, and supplying a first power supply voltage, a first region constituting a source or drain in the first active region, and a first via formed at a position where the first power supply wiring overlaps with the first region, constituting the source or drain in the first active region, and connecting the first region and the first power supply wiring, and at the boundary between the first standard cell and the second standard cell, a first nanosheet extending in the first direction and continuing to the first active region, and a first gate wiring extending in a second direction perpendicular to the first direction and perpendicular to the
• the first and second standard cells are arranged adjacent to each other in the first direction.
• the first standard cell includes a first active region that constitutes the channel, source, and drain of the transistor, and a first power supply wiring formed on the back side of the transistor.
• the first region in the first active region is connected to the first power supply wiring through a first via.
• a first nanosheet that is continuous with the first active region is formed at the boundary between the first and second standard cells.
• the first gate wiring that is perpendicular to the first nanosheet in a planar view is electrically connected to the first region and is supplied with a first power supply voltage.
• the transistor constituted by the first gate wiring and the first nanosheet becomes an off transistor and does not affect the circuit operation of the semiconductor integrated circuit device.
• a nanosheet FET in a semiconductor integrated circuit device in which wiring is provided directly under a transistor, can be formed between adjacent standard cells that does not affect circuit operation.
• FIG. 2 is a plan view showing an example of a layout structure of an inverter cell included in the semiconductor integrated circuit device according to the embodiment; 2A and 2B are cross-sectional views in a lateral direction in a plan view of the inverter cell of FIG. 2A and 2B are cross-sectional views in the vertical direction of the inverter cell shown in FIG. Circuit diagram of the inverter cell shown in Figs.
• FIG. 2 is a cross-sectional view showing another example of the configuration of the inverter cell of FIG. 1 .
• 1A and 1B are diagrams illustrating another example of the configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.
• FIG. 1A and 1B are plan views showing examples of layout structures of cells included in a semiconductor integrated circuit device according to an embodiment, in which (a) is a two-input NAND cell, and (b) is a two-input NOR cell; (a) is a circuit diagram of a two-input NAND cell, and (b) is a circuit diagram of a two-input NOR cell.
• 8A is a plan view showing a modified example of the configuration of FIG. 7, and FIG. 8B is a plan view showing a modified example of the configuration of FIG. 7, where FIG. 8A is a two-input NAND cell, and FIG. 8B is a plan view showing a two-input NOR cell.
• FIG. 1A and 1B are plan views showing an example of a layout structure of a buffer cell included in a semiconductor integrated circuit device according to an embodiment.
• Buffer cell circuit diagram 1A and 1B are plan views showing an example of a layout structure of a double-height cell included in a semiconductor integrated circuit device according to an embodiment, in which FIG. 1A shows an inverter cell, and FIG. 1B shows a buffer cell;
• Modification of the inverter cell configuration of FIG. 1A to 1C are plan views showing examples of layout structures of filler cells included in a semiconductor integrated circuit device according to an embodiment.
• FIG. 1 is a plan view showing an example of a block layout of a semiconductor integrated circuit device according to an embodiment;
• a semiconductor integrated circuit device includes a plurality of standard cells (in this specification, simply referred to as cells, as appropriate), and at least some of the plurality of standard cells include nanosheet FETs (field effect transistors).
• a nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows.
• the nanosheet is formed of silicon, for example. Note that in this disclosure, the transistors included in the standard cells are not limited to nanosheet FETs.
• VDD and VVSS refer to the power supply voltage or the power supply itself.
• expressions such as “same wiring width” that mean that the width, etc., is the same are considered to include the range of manufacturing variation.
• FIGS. 1 to 3 are diagrams showing examples of the layout structure of inverter cells included in a semiconductor integrated circuit device according to an embodiment, with Fig. 1 being a plan view, Figs. 2(a) and (b) being cross-sectional views in the horizontal direction as viewed in a plan view, and Figs. 3(a) and (b) being cross-sectional views in the vertical direction as viewed in a plan view.
• Fig. 2(a) is a cross-section along line X1-X1'
• Fig. 2(b) is a cross-section along line X2-X2'.
• Fig. 3(a) is a cross-section along line Y1-Y1'
• Fig. 3(b) is a cross-section along line Y2-Y2'.
• the horizontal direction of the drawing is the X direction (corresponding to the first direction)
• the vertical direction of the drawing is the Y direction (corresponding to the second direction)
• the direction perpendicular to the substrate surface is the Z direction.
• FIG. 4 is a circuit diagram of the inverter cell shown in FIGS. 1 to 3. As shown in FIG. 4, the inverter cell shown in FIGS. 1 to 3 has a P-type transistor P1 and an N-type transistor N1.
• the inverter cells in Figures 1 to 3 are arranged together with other standard cells in the X direction with their cell frames CF touching, forming a cell row.
• multiple cell rows are arranged in the Y direction with their cell frames CF touching. However, every other row of multiple cell rows is flipped upside down.
• Power supply wiring 11, 12 extending in the X direction are formed in a wiring layer provided on the back surface of a semiconductor chip on which transistors are formed. Power supply wiring 11 supplies power supply voltage VDD, and power supply wiring 12 supplies power supply voltage VSS. Power supply wiring 11, 12 are shared with other cells in a cell row including an inverter cell, and become power supply wiring extending in the X direction. Power supply wiring 11, 12 are also shared between cell rows adjacent in the Y direction.
• An active region 2P that constitutes the channel, source, and drain of the P-type transistor is formed in the P-type transistor region on the N-type well (NWell).
• the active region 2P overlaps with the power supply wiring 11 in a plan view.
• a P-type transistor P1 is formed in the P-type transistor region.
• the transistor P1 has a nanosheet 21a as a channel, which is made up of three overlapping sheets in a plan view and extends in the X direction.
• the transistor P1 is a nanosheet FET.
• the portion (region 2Ps) that serves as the source of the transistor P1 is connected to the power supply wiring 11 through a via 61.
• the active region 2P is continuous with the nanosheets 22a and 22b formed at the positions of the cell frames CF on both sides in the X direction.
• the nanosheets 22a and 22b are made up of three overlapping sheets in a plan view and extend in the X direction.
• the nanosheet 22a is shared with another adjacent cell on the left side of the drawing.
• the nanosheet 22b is shared with another adjacent cell on the right side of the drawing. Because the nanosheets 22a and 22b are formed at the positions of the cell frames CF, the active region 2P is formed continuously in a cell row consisting of multiple cells lined up in the X direction. This makes it possible to form multiple P-type nanosheet FETs without any discontinuous parts.
• An active region 2N that constitutes the channel, source, and drain of the N-type transistor is formed in an N-type transistor region on a P-type substrate (PSub). In a plan view, the active region 2N overlaps with the power supply wiring 12.
• the N-type transistor region may be formed on a P-type well.
• Transistor N1 has a nanosheet 26a as a channel, which is made up of three overlapping sheets in a plan view and extends in the X-direction. In other words, transistor N1 is a nanosheet FET.
• the portion (region 2Ns) that serves as the source of transistor N1 is connected to the power supply wiring 12 via a via 62.
• the active region 2N is continuous with nanosheets 27a and 27b formed at the positions of the cell frames CF on both sides in the X direction.
• nanosheets 27a and 27b are made up of three overlapping sheets in a plan view and extend in the X direction.
• Nanosheet 27a is shared with another adjacent cell on the left side of the drawing.
• Nanosheet 27b is shared with another adjacent cell on the right side of the drawing. Because nanosheets 27a and 27b are formed at the positions of the cell frames CF, active region 2N is formed continuously in a cell row consisting of multiple cells lined up in the X direction. This makes it possible to form multiple N-type nanosheet FETs without discontinuous parts.
• the active region which is the source and drain on both sides of the nanosheet, is formed, for example, by epitaxial growth from the nanosheet.
• a gate wiring 31 is formed extending in the Y direction from the P-type transistor region to the N-type transistor region.
• the gate wiring 31 surrounds the outer periphery in the Y direction and Z direction of the nanosheet 21a of transistor P1 and the nanosheet 26a of transistor N1 via a gate insulating film (not shown).
• the gate wiring 31 corresponds to the gates of transistors P1 and N1.
• dummy gate wirings 32a and 32b are formed on the cell frame CF on both sides in the X direction.
• the dummy gate wiring 32a surrounds the outer periphery of the nanosheet 22a in the Y direction and the Z direction via a gate insulating film (not shown).
• the dummy gate wiring 32b surrounds the outer periphery of the nanosheet 22b in the Y direction and the Z direction via a gate insulating film (not shown).
• dummy gate wirings 33a and 33b are formed on the cell frame CF on both sides in the X direction.
• the dummy gate wiring 33a surrounds the outer periphery of the nanosheet 27a in the Y direction and the Z direction via a gate insulating film (not shown).
• the dummy gate wiring 33b surrounds the outer periphery of the nanosheet 27b in the Y direction and the Z direction via a gate insulating film (not shown).
• Dummy gate wiring 32a, 33a is shared with other cells arranged on the left side of the drawing.
• Dummy gate wiring 32b, 33b is shared with other cells arranged on the right side of the drawing.
• Local wiring 41a, 41b, and 41c extending in the Y direction are formed in the local wiring layer.
• Local wiring 41a is connected to region 2Ps in active region 2P.
• Local wiring 41b is connected to region 2Ns in active region 2N.
• Local wiring 41c extends from the P-type transistor region to the N-type transistor region, and is connected to the portion that becomes the drain of transistor P1 in active region 2P and the portion that becomes the drain of transistor N1 in active region 2N.
• metal wirings 51, 52, 53, and 54 extending in the X direction are formed.
• Metal wiring 51 is connected to local wiring 41a through a via, and is also connected to dummy gate wiring 32a through a via.
• Metal wiring 52 is connected to local wiring 41b through a via, and is also connected to dummy gate wiring 33a through a via.
• Metal wiring 53 is connected to gate wiring 31 through a via.
• Metal wiring 54 is connected to local wiring 41c through a via.
• Metal wiring 53 corresponds to node A
• metal wiring 54 corresponds to node Y.
• a via 61 is placed in the active region 2P at a position that overlaps in plan view with region 2Ps, which is the source of transistor P1.
• the via 61 connects the power supply wiring 11 formed on the back surface of the semiconductor chip to region 2Ps. This allows VDD to be supplied to region 2Ps.
• local wiring 41a is connected to region 2Ps, and dummy gate wiring 32a on cell frame CF is connected to local wiring 41a via M0 wiring 51. This allows VDD to be supplied to dummy gate wiring 32a.
• Region 2Ps is adjacent to dummy gate wiring 32a and nanosheet 22a in plan view.
• a via 62 is arranged in the active region 2N at a position overlapping in plan view with the region 2Ns which is the source of the transistor N1.
• the via 62 connects the power supply wiring 12 formed on the back surface of the semiconductor chip to the region 2Ns. This allows VSS to be supplied to the region 2Ns.
• a local wiring 41b is connected to the region 2Ns, and the dummy gate wiring 33a on the cell frame CF is connected to the local wiring 41b via the M0 wiring 52. This allows VSS to be supplied to the dummy gate 33a.
• the region 2Ns is adjacent to the dummy gate wiring 33a and the nanosheet 27a in plan view.
• transistor P0 having nanosheet 22a becomes an off transistor and does not affect the logical operation of the semiconductor integrated circuit device.
• VSS is supplied to the dummy gate wiring 33a, transistor N0 having nanosheet 27a becomes an off transistor and does not affect the logical operation of the semiconductor integrated circuit device.
• the power supply wiring 11, 12 is formed in a wiring layer provided on the back surface of the semiconductor chip, this is not limited to this.
• the power supply wiring may be formed on the back surface side of the transistor.
• the back surface side of the transistor refers to the side opposite to the side on which the local wiring, metal wiring, etc. connected to the transistor are stacked.
• the power supply wiring 11, 12 may also be formed in multiple wiring layers.
• Fig. 5 is a diagram showing another configuration example, and is a cross-sectional view taken along line X1-X1' in the horizontal direction in plan view in Fig. 1.
• the dummy gate wiring 32a is connected to the local wiring 41a via a contact 71 (shared contact) instead of the M0 wiring 51 and a via.
• the dummy gate wiring 33a and the local wiring 41b may be connected via a shared contact instead of the M0 wiring 52 and a via.
• the power supply wiring formed on the back surface side of the transistor may be formed using a semiconductor chip separate from the semiconductor chip on which the transistor is formed.
• FIG. 6(a) is another configuration example of a semiconductor integrated circuit device according to an embodiment.
• the semiconductor integrated circuit device 100 shown in FIG. 6(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A.
• Chip B has power wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps or the like.
• FIG. 6(b) shows a cross section of the inverter cell of FIG. 1 along line Y2-Y2' in this configuration example.
• a power supply wiring 11 that supplies VDD and a power supply wiring 12 that supplies VSS are formed in a wiring layer provided on the surface of chip B.
• Power supply wiring 11 is connected to region 2Ps of chip A via via 61.
• Power supply wiring 12 is connected to region 2Ns of chip A via via 62.
• This configuration example also provides the same effect as the inverter cell described above. Note that in this configuration example, the power supply wiring 11, 12 may also be formed in multiple wiring layers.
• Fig. 7 is a plan view showing an example of a layout structure of cells included in a semiconductor integrated circuit device according to an embodiment, in which Fig. 7(a) is a two-input NAND cell and Fig. 7(b) is a two-input NOR cell.
• Fig. 8(a) is a circuit diagram of a two-input NAND cell
• Fig. 8(b) is a circuit diagram of a two-input NOR cell.
• the layout structure of Fig. 7 the description of the inverter cell described above and the configuration that can be easily inferred from the circuit diagram of Fig. 8 may be omitted or simplified.
• the via 161 is arranged in a position that overlaps in plan view with the portion (region 2Pa) that is to be the source of the transistor P11 in the active region 2P.
• the region 2Pa is adjacent to the nanosheet 122a and dummy gate wiring 132a formed on the cell frame CF.
• the via 161 connects the region 2Pa to the power supply wiring 11 formed on the back surface of the semiconductor chip, and thus VDD is supplied to the region 2Pa.
• the local wiring 141a is connected to the region 2Pa
• the dummy gate wiring 132a is connected to the local wiring 141a via the M0 wiring 151.
• VDD is supplied to the dummy gate wiring 132a. Therefore, the transistor P0 having the nanosheet 122a becomes an off transistor and does not affect the circuit operation of the semiconductor integrated circuit device.
• the via 162 is arranged at a position in the active region 2N that overlaps with the portion (region 2Na) that becomes the source of the transistor N11 in a planar view.
• the region 2Na is adjacent to the nanosheet 127a and dummy gate wiring 133a formed on the cell frame CF.
• the via 162 connects the region 2Na to the power supply wiring 12 formed on the back surface of the semiconductor chip, and thus VSS is supplied to the region 2Na.
• the local wiring 141b is also connected to the region 2Na, and the dummy gate wiring 133a is connected to the local wiring 141b via the M0 wiring 152.
• VSS is supplied to the dummy gate wiring 133a. Therefore, the transistor N0 having the nanosheet 127a becomes an off transistor and does not affect the circuit operation of the semiconductor integrated circuit device.
• VDD is supplied to dummy gate wiring 132b
• VSS is supplied to dummy gate wiring 133b.
• FIG. 9 is a plan view showing a modified example of the configuration of FIG. 7, where FIG. 9(a) is a two-input NAND cell, and FIG. 9(b) is a two-input NOR cell.
• the dummy gate wiring 132a is connected to the portion (region 2Pb) that serves as the source of the transistors P11 and P12 in the active region 2P.
• Region 2Pb is between the transistors P11 and P12, and is separated from the nanosheet 122a and dummy gate wiring 132a formed on the cell frame CF.
• a via 163 is disposed at a position that overlaps with region 2Pb in a plan view, and connects region 2Pb to the power supply wiring 11 formed on the back surface of the semiconductor chip.
• a local wiring 141c is connected to region 2Pb, and the dummy gate wiring 132a is connected to the local wiring 141c via the M0 wiring 153. As a result, VDD is supplied to the dummy gate 132a.
• the dummy gate wiring 133b is connected to the portion (region 2Nb) that serves as the source of the transistors N11 and N12 in the active region 2N.
• the region 2Nb is between the transistors N11 and N12, and is separated from the nanosheet 127a and the dummy gate wiring 133b formed on the cell frame CF.
• the via 164 is disposed at a position that overlaps with the region 2Nb in a planar view, and connects the region 2Nb to the power supply wiring 12 formed on the back surface of the semiconductor chip.
• the local wiring 141d is connected to the region 2Nb, and the dummy gate wiring 133b is connected to the local wiring 141d via the M0 wiring 154. As a result, the dummy gate wiring 133b is supplied with VSS.
• ⁇ Buffer cell> 10(a) and 10(b) are plan views showing an example of a layout structure of a buffer cell included in a semiconductor integrated circuit device according to an embodiment.
• Fig. 11 is a circuit diagram of the buffer cell. With regard to the layout structure of Fig. 10, the description of each cell described above and the configuration that can be easily inferred from the circuit diagram of Fig. 11 may be omitted or simplified.
• the dummy gate wiring 232a is connected to the portion (region 2Pc) that serves as the source of the transistors P11 and P12 in the active region 2P.
• the region 2Pc is between the transistors P11 and P12, and is separated from the nanosheet 222a and the dummy gate wiring 232a formed on the cell frame CF.
• the via 261 is disposed at a position that overlaps with the region 2Pc in a plan view, and connects the region 2Pc to the power supply wiring 11 formed on the back surface of the semiconductor chip.
• the local wiring 241 is connected to the region 2Pc, and the dummy gate wiring 232a is connected to the local wiring 241 via the M0 wiring 251. As a result, the dummy gate wiring 232a is supplied with VDD.
• the dummy gate wiring 233a is connected to a portion (region 2Nc) in the active region 2N that serves as the source of the transistors N11 and N12.
• the region 2Nc is between the transistors N11 and N12, and is separated from the nanosheet 227a and the dummy gate wiring 233a formed on the cell frame CF.
• the via 262 is disposed at a position that overlaps with the region 2Nc in a plan view, and connects the region 2Nc to the power supply wiring 12 formed on the back surface of the semiconductor chip.
• the local wiring 242 is connected to the region 2Nc, and the dummy gate wiring 233a is connected to the local wiring 242 via the M0 wiring 252. As a result, the dummy gate wiring 233a is supplied with VSS.
• FIG. 10(b) shows a modified example of the configuration in FIG. 10(a).
• a dummy transistor P01 including a dummy gate wiring 232b is arranged to the left of transistor P12 in the drawing.
• a dummy transistor N01 including a dummy gate wiring 233b is arranged to the left of transistor N12 in the drawing.
• the region 2Pd between the dummy gate wirings 232a, 232b is a region that becomes the source or drain of the dummy transistor P01 that does not constitute a logic circuit, and does not contribute to the circuit operation.
• a via 263 is disposed at a position that overlaps with the region 2Pd in a planar view, and connects the region 2Pd to the power supply wiring 11.
• a local wiring 243 is connected to the region 2Pd, and the dummy gate wirings 232a, 232b are connected to the local wiring 243 via the M0 wiring 253. As a result, VDD is supplied to the dummy gate wirings 232a, 232b.
• the region 2Nd between the dummy gate wirings 233a and 233b is a region that becomes the source or drain of the dummy transistor N01 that does not constitute a logic circuit, and does not contribute to the circuit operation.
• a via 264 is disposed at a position that overlaps with the region 2Nd in a planar view, and connects the region 2Nd to the power supply wiring 12.
• a local wiring 244 is connected to the region 2Nd, and the dummy gate wirings 233a and 233b are connected to the local wiring 244 via the M0 wiring 254. As a result, VSS is supplied to the dummy gate wirings 233a and 233b.
• the regions 2Pd, 2Nd which are the source or drain of the dummy transistors P01, N01 that do not constitute a logic circuit and do not contribute to the circuit operation, are used. This makes it possible to reduce the influence of the adjacent cell on the left side in the X direction on the operating characteristics of the buffer cell.
• ⁇ Double height cell> 12A and 12B are plan views showing examples of the layout structure of double-height cells included in the semiconductor integrated circuit device according to the embodiment, where Fig. 12A shows an inverter cell, and Fig. 12B shows a buffer cell.
• the double-height cell in Fig. 12(a) is based on a configuration in which an inverter cell with the configuration in Fig. 1 reversed vertically is placed adjacent to the lower side of the inverter cell in Fig. 1.
• the double-height cell in Fig. 12(b) is based on a configuration in which a buffer cell with the configuration in Fig. 10(b) reversed vertically is placed adjacent to the lower side of the buffer cell in Fig. 10(b).
• unnecessary wiring has been deleted and the placement position of the M0 wiring has been changed.
• FIG. 13 shows a modified example of the configuration of the inverter cell in Fig. 1.
• a dummy transistor P01 including a dummy gate wiring 32c is arranged on the right side of transistor P1 in the X direction in the drawing.
• a dummy transistor N01 including a dummy gate wiring 33c is arranged on the right side of transistor N1 in the X direction in the drawing.
• the region 2Px between the dummy gate wirings 32b and 32c is a region that becomes the source or drain of the dummy transistor P01 that does not constitute a logic circuit, and does not contribute to the circuit operation.
• a via 63 is disposed at a position that overlaps with the region 2Px in a planar view, and connects the region 2Px to the power supply wiring 11.
• a local wiring 41d is connected to the region 2Px, and the dummy gate wirings 32b and 32c are connected to the local wiring 41d via the M0 wiring 53. As a result, VDD is supplied to the dummy gate wirings 32b and 32c.
• the region 2Nx between the dummy gate wirings 33b and 33c is a region that serves as the source or drain of the dummy transistor N01 that does not constitute a logic circuit, and does not contribute to circuit operation.
• a via 64 is disposed at a position that overlaps with the region 2Nx in a planar view, and connects the region 2Nx to the power supply wiring 12.
• a local wiring 41e is connected to the region 2Nx, and the dummy gate wirings 33b and 33c are connected to the local wiring 41e via the M0 wiring 54. As a result, VSS is supplied to the dummy gate wirings 33b and 33c.
• VDD is supplied to dummy gate wiring 32b, so transistor P02 on cell frame CF becomes an off transistor and does not affect the logical operation of the semiconductor integrated circuit device.
• VSS is supplied to dummy gate wiring 33b, so transistor N02 on cell frame CF becomes an off transistor and does not affect the logical operation of the semiconductor integrated circuit device. That is, in the configuration of FIG. 13, transistors P0, P02, N0, and N02 on both sides of cell frame CF in the X direction all become off transistors.
• the transistor on the left side of the cell frame CF can be turned off. For this reason, if a cell row is constructed by arranging the cells without inverting them in the X direction, it is possible to turn off all of the transistors on the cell boundaries. However, since the cells cannot be inverted in the X direction, there are significant constraints on the cell layout. In contrast, in the configuration of this modified example, since both the transistors on the left and right sides can be turned off, no problems arise even if the cells are inverted in the X direction when constructing a cell row. Therefore, this modified example can increase the degree of freedom in cell layout.
• FIG. 14(a) to (c) are examples of layout structures of filler cells included in a semiconductor integrated circuit device according to an embodiment.
• Filler cells are cells for filling spaces between logic cells.
• FIG. 14(a) is an example of the configuration of a filler cell with a cell width of one grid
• FIG. 14(b) is an example of the configuration of a filler cell with a cell width of four grids.
• a grid is a virtual line used for component placement during design, and also represents the spacing between the lines. For example, in this example, gate wiring is placed on a grid.
• FIG. 14(c) is a modified example of the configuration of FIG. 14(a).
• dummy gate wirings 332a and 332b are formed on the cell frame CF on both sides in the X direction in the P-type transistor region.
• a region 2Pf between the dummy gate wirings 332a and 332b in the active region 2P is connected to the power supply wiring 11 through a via 361.
• a local wiring 341a is connected to the region 2Pf, and the dummy gate wirings 332a and 332b are connected to the local wiring 341a through an M0 wiring 351.
• VDD is supplied to the dummy gate wirings 332a and 332b.
• dummy gate wirings 333a and 333b are formed on the cell frame CF on both sides in the X direction.
• a region 2Nf between the dummy gate wirings 333a and 333b is connected to the power supply wiring 12 via a via 362.
• a local wiring 341b is connected to the region 2Nf, and the dummy gate wirings 333a and 333b are connected to the local wiring 341b via an M0 wiring 352.
• VSS is supplied to the dummy gate wirings 333a and 333b.
• VDD is supplied to the dummy gate wirings 332a and 332b and VSS is supplied to the dummy gate wirings 333a and 333b, all the transistors on the cell frame CF become off transistors and do not affect the logical operation of the semiconductor integrated circuit device.
• all transistors on the cell frame CF can be turned off, similar to the configuration of FIG. 14(a).
• VDD is supplied to dummy gate wirings 334a and 334b
• VSS is supplied to dummy gate wirings 335a and 335b.
• the filler cells in this embodiment can be arranged with different grid widths depending on the space width between the logic cells.
• the dummy gate wiring on the cell frame CF on both sides in the X direction is fixed to the power supply potential, but it is also possible to fix only the dummy gate wiring on one side to the power supply potential.
• the dummy gate wirings 332a, 333a formed on the cell frame CF on the left side in the X direction are fixed to the power supply potential. It is also possible to fix only the dummy gate wiring formed on the cell frame on the right side in the X direction to the power supply potential.
• the dummy gate wiring on the cell frame CF is fixed to the power supply potential for both the P-type transistor region and the N-type transistor region.
• the dummy gate wiring on the cell frame CF may be fixed to the power supply potential, i.e., VDD, for only the P-type transistor region.
• the dummy gate wiring on the cell frame CF may be fixed to the power supply potential, i.e., VSS, for only the N-type transistor region.
• Fig. 15 is a plan view showing an example of a block layout of a semiconductor integrated circuit device according to the embodiment.
• the block layout of Fig. 15 is composed of three rows of cells, and is configured by arranging the cells described above.
• Cells C1A to C1N are single-height cells, and cells C2A and C2B are double-height cells.
• cells C2A, C1A, C1C, C1D, and C2B are arranged from left to right in the drawing.
• Cell C2A is the inverter cell of FIG. 12(a).
• Cell C1A is the inverter cell of FIG. 1.
• Cell C1B is the two-input NAND cell of FIG. 7(a).
• Cell C1C is the filler cell of FIG. 14(a).
• Cell C1D is the two-input NOR cell of FIG. 7(b) flipped left to right.
• Cell C2B is the buffer cell of FIG. 12(b).
• cells C2A, C1E, C1F, C1G, C1H, C1I, and C2B are arranged from left to right in the drawing.
• Cell C1E is the filler cell in FIG. 14(a) flipped upside down.
• Cell C1F is the buffer cell in FIG. 10(b) flipped upside down.
• Cells C1G and C1H are the filler cell in FIG. 14(a) flipped upside down.
• Cell C1I is the inverter cell in FIG. 1 flipped upside down and left to right.
• cells C1J, C1K, C1L, C1M, and C1N are arranged from left to right in the drawing.
• Cell C1J is the filler cell of FIG. 14(b).
• Cell C1K is the buffer cell of FIG. 10(a) reversed left to right.
• Cell C1L is the buffer cell of FIG. 10(b).
• Cell C1M is the filler cell of FIG. 14(a).
• Cell C1N is the two-input NAND cell of FIG. 7(a) reversed left to right.
• the active area is formed continuously in the X direction.
• the dummy gate wiring at the cell boundary is supplied with the power supply potential VDD or VSS from at least one of the cells on either side of it.
• the transistors formed by the dummy gate wiring at the cell boundary are off transistors and do not affect the logical operation of the circuit.
• the dummy gate wiring at the cell boundary between cells C2A and C1A is supplied with VDD or VSS from cell C1A to its right.
• the dummy gate wiring at the cell boundary between cells C1C and C1D is supplied with VDD or VSS from cell C1C to its left. Because cell C1D is mirror-inverted, a filler cell, i.e. cell C1C, that supplies power to the dummy gate wiring on both sides is placed to its left.
• the dummy gate wiring at the cell boundary between cells C1E and C1F is supplied with VDD or VSS from cell C1F to the right of it.
• Cell C1F is the buffer cell in FIG. 10(b) turned upside down, and as described above, the potential of the dummy gate wiring at the cell boundary is fixed using an area of the active region that does not contribute to circuit operation. This reduces the effect of cell C1E on the operating characteristics of cell C1F.
• each standard cell has an active region that constitutes the channel, source, and drain of the transistor, and a power supply wiring formed on the back side of the transistor.
• a nanosheet that is continuous with the active region is formed at the boundary of the standard cells.
• the active region is continuous in multiple standard cells, so that multiple nanosheet FETs can be formed without discontinuous parts.
• the first region that becomes the source or drain in the active region is connected to the power supply wiring through a via.
• the gate wiring formed at the boundary of the standard cell is electrically connected to the first region and is supplied with a power supply voltage.
• the transistor constituted by the gate wiring and the nanosheet at the boundary of the standard cell becomes an off transistor and does not affect the circuit operation of the semiconductor integrated circuit device.
• a layout structure can be realized that forms nanosheet FETs between adjacent standard cells without affecting circuit operation.
• the nanosheet is illustrated as having three overlapping sheet structures in a plan view, and the cross-sectional shape of the sheet structure is rectangular, but the number of sheet structures of the nanosheet and the cross-sectional shape are not limited to this.
• the transistors are nanosheet FETs, but this is not limited to this.
• they may be fin FETs or other types of transistors.
• This disclosure provides a layout structure for semiconductor integrated circuit devices configured with wiring directly under transistors that improves manufacturing precision, suppresses manufacturing variability, and improves yields, and is therefore useful, for example, for reducing costs and improving performance of semiconductor integrated circuit devices.

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• 2023
  • 2023-12-04 JP JP2024565752A patent/JPWO2024135324A1/ja active Pending
  • 2023-12-04 WO PCT/JP2023/043310 patent/WO2024135324A1/ja not_active Ceased
• 2025
  • 2025-05-13 US US19/206,640 patent/US20250273567A1/en active Pending

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